Gallium nitride power device

Abstract

The utility model provides a gallium nitride power device, from below to above includes successively: substrate, first nucleation layer, first buffer layer, a plurality of nano particles, second buffer layer, active layer and P type layer. Nano particle can block the defect longitudinal extension, namely the growth quality, crystal structure and stress distribution of gallium nitride power device provided by the utility model are all improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a gallium nitride power device. Background Technology

[0002] With the increasing demand for high-efficiency power conversion, traditional silicon-based power devices are unable to meet the requirements of higher frequencies, higher voltages, and higher power densities due to their physical limitations. GaN (gallium nitride) material, with its wide bandgap, high electron saturation velocity, and good thermal conductivity, enables GaN power devices to operate under high voltage and high frequency conditions, and is widely used in power converters, RF power amplifiers, motor drives, and other fields. However, one of the challenges faced by GaN power devices in practical applications is leakage defects and their impact on device reliability.

[0003] Leakage defects directly impact the reliability and performance of GaN power devices. High leakage current can lead to increased power consumption, reduced efficiency, and potentially thermal runaway and device failure. Leakage problems are exacerbated, especially under high voltage, high temperature, and high humidity environments, further affecting device stability and lifespan. Therefore, addressing leakage defects is a crucial task for improving the reliability of GaN power devices. High-density dislocations and defects are generated during GaN epitaxial growth and device fabrication, and these defects can affect device performance.

[0004] For optimizing defects in GaN epitaxial growth, existing technologies either use homogeneous GaN substrates, but GaN substrates are expensive and have small crystal sizes, making it impossible to fabricate and apply 8-inch and 12-inch devices. Another approach uses heterogeneous substrates, which are less expensive and enable the fabrication and application of 8-inch and 12-inch devices. These technologies employ multilayered AlN / GaN to buffer and release the lattice mismatch caused by the heterogeneous substrate and filter through dislocations. However, the AlN / GaN thickness needs precise control, and the lattice and thermal mismatches between AlN and GaN themselves introduce more defects, dislocations, and stress.

[0005] Moreover, in the growth of GaN epitaxial structures on heterogeneous substrates, a single nucleation layer is formed between the existing heterogeneous substrate and the first buffer layer. Because the heterogeneous substrate does not have high-quality GaN seed crystals, it is difficult to crystallize high-quality GaN epitaxial structures. In addition, most of them use a thicker AlN / AlGaN / GaN cumulative buffer layer, which causes lattice distortion, dislocations and stress caused by lattice mismatch to accumulate layer by layer. At the same time, the thermal stress caused by thermal mismatch will also increase the stress of the thin film. Utility Model Content

[0006] The purpose of this invention is to provide a gallium nitride power device that improves the growth quality, crystal structure, and stress distribution of the gallium nitride power device.

[0007] To achieve the above and other related objectives, this utility model provides a gallium nitride power device, which, from bottom to top, comprises: a substrate, a first nucleation layer, a first buffer layer, a plurality of nanoparticles, a second buffer layer, an active layer, and a P-type layer.

[0008] Optionally, in the gallium nitride power device, the first buffer layer and the nanoparticles form a second nucleation layer.

[0009] Optionally, in the gallium nitride power device, the nanoparticles are SiC nanoparticles, SiN nanoparticles, or composite nanoparticles composed of SiC and SiN, and the nanoparticles are spaced apart on the first buffer layer.

[0010] Optionally, in the gallium nitride power device, the thickness of the nanoparticles is 0.5 nm to 5 nm.

[0011] Optionally, in the gallium nitride power device, the first nucleation layer is an AlN layer.

[0012] Optionally, in the gallium nitride power device, the thickness of the first nucleation layer is 100nm to 300nm.

[0013] Optionally, in the gallium nitride power device, the substrate is a heterogeneous substrate.

[0014] Optionally, in the gallium nitride power device, the first buffer layer is a GaN layer or a composite layer composed of a GaN layer and an AlGaN layer.

[0015] Optionally, in the gallium nitride power device, the thickness of the first buffer layer is 500nm to 2000nm.

[0016] Optionally, in the gallium nitride power device, the second buffer layer is a GaN layer.

[0017] Optionally, in the gallium nitride power device, the thickness of the second buffer layer is 0.8 μm to 2 μm.

[0018] Optionally, in the gallium nitride power device, the P-type layer covers a portion of the active layer, and the gallium nitride power device further includes: a passivation layer, a gate electrode, a source electrode, and a drain electrode, wherein the passivation layer covers the P-type layer and the active layer, the gate electrode penetrates the passivation layer and contacts the P-type layer, and the source electrode and drain electrode penetrate the passivation layer and contact the active layer, and the source electrode and drain electrode are located on both sides of the gate electrode.

[0019] Optionally, in the gallium nitride power device, the gallium nitride power device is a HEMT device.

[0020] Compared with the prior art, the technical solution of this utility model has the following beneficial effects:

[0021] In the gallium nitride power device provided by this invention, by setting nanoparticles on the first buffer layer, the longitudinal extension of defects can be blocked, effectively improving the growth quality, crystal structure and stress distribution of the epitaxial structure.

[0022] Furthermore, this invention employs two nucleation layers: a first nucleation layer located between the substrate and the first buffer layer, and a second nucleation layer composed of the first buffer layer and nanoparticles. The first buffer layer can provide high-quality nanoseed crystals, while the nanoparticles block the longitudinal extension of defects and improve lateral growth. Therefore, the two-stage nucleation growth scheme can obtain a high-quality epitaxial structure, effectively improving the growth quality, crystal structure, and stress distribution of the epitaxial structure, enhancing the crystal quality of the active layer, reducing leakage channels, and improving the reliability of gallium nitride power devices. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a gallium nitride power device according to an embodiment of the present invention;

[0024] Figure 2 This is a flowchart of a method for fabricating a gallium nitride power device according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the structure after the growth of a nanofilm in the preparation method of a gallium nitride power device according to an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure after the H2 post-processing process is performed in the fabrication method of a gallium nitride power device according to an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the structure after the growth of the second buffer layer in the fabrication method of a gallium nitride power device according to an embodiment of the present invention;

[0028] Figures 1-5 middle:

[0029] 101-Substrate, 102-First nucleation layer, 103-First buffer layer, 104a-Nano film, 104-Nano particle, 105-Second buffer layer, 106-Channel layer, 107-Barrier layer, 108-P-type layer, 201-Passivation layer, 202-Gate electrode, 203-Source electrode, 204-Drain electrode, 3-Defect. Detailed Implementation

[0030] The gallium nitride power device proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0031] read Figure 1 This invention provides a gallium nitride power device, preferably a HEMT (high electron mobility transistor). The gallium nitride power device may include an epitaxial structure, which may include, from bottom to top, a substrate 101, a first nucleation layer 102, a first buffer layer 103, a plurality of nanoparticles 104, a second buffer layer 105, an active layer, and a P-type layer 108.

[0032] In this embodiment, the first nucleation layer 102 is located between the substrate 101 and the first buffer layer 103. The material of the first nucleation layer 102 is preferably a nitride, and more preferably aluminum nitride (AlN). That is, the first nucleation layer 102 is preferably an AlN layer.

[0033] The nanoparticles 104 are located between the first buffer layer 103 and the second buffer layer 105, forming a second nucleation layer. The nanoparticles 104 are preferably SiC nanoparticles, SiN nanoparticles, or composite nanoparticles composed of SiC and SiN, and are spaced apart on the first buffer layer 103. Compared to the single nucleation layer between the heterogeneous substrate and the first buffer layer in the prior art, where the heterogeneous substrate lacks high-quality GaN seed crystals, making it difficult to crystallize high-quality GaN epitaxial structures, the nanoparticles 104 in this embodiment utilize materials such as SiC and / or SiN to form a nanoparticle structure, forming a second nucleation layer with the crystallized GaN first buffer layer. The first buffer layer 103 can provide high-quality nanoseed crystals (specifically GaN nanoseed crystals), while the nanoparticles 104 can block the longitudinal extension of defects, improve lateral growth, effectively improve the growth quality, crystal structure, and stress distribution of the epitaxial structure, enhance the crystal quality of the active layer, reduce leakage channels, and improve the reliability of gallium nitride power devices. In other words, this embodiment uses a two-stage nucleation growth method to obtain high-quality gallium nitride power devices.

[0034] The active layer may include a channel layer 106 and a barrier layer 107. The P-type layer 108 covers a portion of the active layer, specifically a portion of the barrier layer 107. In this embodiment, the P-type layer 108 covering a portion of the barrier layer 107 serves as a gate structure layer.

[0035] The gallium nitride power device may further include a passivation layer 201 and electrodes located on the epitaxial structure, specifically including: a passivation layer 201, a gate electrode 202, a source electrode 203, and a drain electrode 204, wherein the passivation layer 201 covers the P-type layer 108, the passivation layer 201 also covers the active layer, the gate electrode 202 penetrates the passivation layer 201 and contacts the P-type layer 108, the source electrode 203 and the drain electrode 204 penetrate the passivation layer 201 and contact the active layer, and the source electrode 203 and the drain electrode 204 are located on both sides of the gate electrode 202.

[0036] Compared to existing technologies (where a single nucleation layer exists between the heterostructure and the first buffer layer, making it difficult to crystallize high-quality GaN epitaxial structures due to the lack of high-quality GaN seed crystals on the heterostructure, and often requiring subsequent thicker AlN / AlGaN / GaN accumulation buffer layers, resulting in lattice distortion, dislocations, and stress accumulating layer by layer due to lattice mismatch, and thermal stress caused by thermal mismatch also increasing film stress), the gallium nitride power device in this embodiment features two nucleation layers: a first nucleation layer located between the substrate and the first buffer layer, and a second nucleation layer composed of the first buffer layer and nanoparticles. The first buffer layer can provide high-quality nanoseed crystals, and the nanoparticles block the longitudinal extension of defects and improve lateral growth. Therefore, the two-stage nucleation growth scheme can obtain a high-quality epitaxial structure, effectively improving the growth quality, crystal structure, and stress distribution of the epitaxial structure, enhancing the crystal quality of the active layer, reducing leakage channels, and improving the reliability of the gallium nitride power device.

[0037] See Figure 2 This utility model also provides a method for fabricating the gallium nitride power device described above, specifically including the following steps:

[0038] Step S1: Provide a substrate 101;

[0039] Step S2: A first nucleation layer 102, a first buffer layer 103, and nanoparticles 104 are sequentially grown on the substrate 101;

[0040] Step S3: A second buffer layer 105, an active layer, and a P-type layer 108 are sequentially grown on the nanoparticles 104.

[0041] The epitaxial structure formation process of the gallium nitride power device in this embodiment may include MOCVD (Metal-organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), or PECVD (Plasma Enhanced Chemical Vapor Deposition), but is not limited to these.

[0042] Step S1 is performed, providing a substrate 101. The substrate 101 is preferably a heterogeneous substrate, such as sapphire (Al2O3), silicon carbide (SiC), or silicon (Si), or it can be a substrate with an AlN or SiC structural layer on its upper surface, for example, a sapphire substrate with AlN on its upper surface. In this embodiment, the thickness of the substrate 101 is preferably 500 mm to 1300 mm.

[0043] Step S2 is performed to grow a first nucleation layer 102 on the substrate 101. The material of the first nucleation layer 102 is preferably a nitride, more preferably aluminum nitride (AlN). The thickness of the first nucleation layer 102 is preferably 100 nm to 300 nm, for example, 200 nm. In this embodiment, the first nucleation layer 102 can adjust the stress and strain caused by the lattice mismatch between the heterogeneous substrate and the GaN material. However, because heterogeneous materials often have limited effectiveness, it also isolates Ga atoms from reacting to form a Ga-Si eutectic alloy on the Si substrate.

[0044] After the step of growing the first nucleation layer 102, a first buffer layer 103 is grown on the first nucleation layer 102. In this embodiment, the material of the first buffer layer 103 is preferably a nitride. Further, the first buffer layer 103 is not limited to a single material, but can be a combination of multiple materials, different dopants, and different doping concentrations. Even further, the material of the first buffer layer 103 can be GaN or a combination of GaN and AlGaN, that is, the first buffer layer 103 is preferably a GaN layer or a composite layer composed of a GaN layer and an AlGaN layer, and the Al component concentration in the first buffer layer 103 can be constant or gradually varied, with an Al component of 0-100%. In this embodiment, the thickness of the first buffer layer 103 is preferably 500nm-2000nm, for example, 1000nm. At a thickness of 500nm-2000nm, the GaN material has grown into a crystalline state rather than an amorphous state, that is, the first buffer layer 103 can provide high-quality GaN nanoseed crystals. Because this embodiment uses two nucleation layers, it has a higher tolerance for edge and screw dislocations in the first buffer layer 103, making growth simpler and providing high-quality GaN nanoseeds. In the prior art, the heterostructure substrate is not GaN, and the first nucleation layer is grown using other heterostructure materials, resulting in stress problems caused by lattice mismatch. The subsequent first buffer layer is also grown on a heterostructure, and similarly, it will have a large number of dislocations due to stress problems. If the second nucleation layer process is not used, there is no three-dimensional growth of the nanostructure, and the GaN growth will continue these dislocations throughout the entire epitaxial structure. However, this embodiment uses materials such as SiC and / or SiN to form a porous honeycomb structure with particle sizes between several and tens of nanometers, prompting the GaN material in the second buffer layer to undergo three-dimensional nucleation growth again. This embodiment has an additional first buffer layer as GaN nanoseeds, eliminating lattice mismatch and annihilating most defects, thus greatly reducing the dislocation density of the subsequently grown GaN epitaxial structure.

[0045] See Figure 3 and Figure 4 After the step of growing the first buffer layer 103, a plurality of nanoparticles 104 are grown on the first buffer layer 103. In this embodiment, the number of nanoparticles 104 is preferably multiple. In this embodiment, the method for preparing the nanoparticles 104 may include:

[0046] A nanofilm 104a is grown on the first buffer layer 103;

[0047] The H2 post-processing process is performed to transform the nanofilm 104a into nanoparticles 104.

[0048] See Figure 3The nanofilm 104a is preferably made of at least one of SiC and SiN, i.e., the nanofilm 104a is preferably a SiC layer, a SiN layer, or a composite layer composed of SiC and SiN layers. Since the nanofilm 104a is nanoscale and relatively thin, SiC and / or SiN may preferentially grow in island or cluster form, forming a particulate film. The nanofilm 104a can be grown using simple processes, such as continuous growth using MOCVD, with SiH4, N2, NH3 (or C2H4) introduced, and the reaction temperature between 600℃ and 800℃.

[0049] See Figure 4 After the step of growing the nanofilm 104a, an H2 post-processing process can be performed. This H2 post-processing process needs to be performed at a high temperature, preferably 800℃ to 1200℃, and the processing time is preferably 0 seconds to 20 seconds. In this embodiment, the high-temperature H2 post-processing of SiC material allows SiC to recrystallize into a honeycomb nanoparticle structure. SiN will also form a nanoparticle structure after the high-temperature H2 post-processing, meaning that the nanofilm 104a will form nanoparticles after the H2 post-processing. After the H2 post-processing, the first buffer layer 103 and the nanoparticles 104 form a second nucleation layer. The thickness of the nanoparticles 104 is preferably 0.5 nm to 5 nm, for example, 3 nm. In this embodiment, if the thickness of the nanoparticles 104 is too thin, it cannot achieve a nanostructure masking effect; if the thickness is too thick, high-temperature recrystallization cannot be completely broken down, and subsequent two-dimensional growth is difficult. The nanoparticles 104 can block the longitudinal extension of defect 3, improve lateral growth, effectively improve the growth quality, crystal structure and stress distribution of epitaxial structure, improve the crystal quality of active layer, reduce leakage channel generation, and improve the reliability of gallium nitride power devices.

[0050] See Figure 5 Step S3 is performed, which involves growing a high-quality second buffer layer 105 on the nanoparticles 104 after the H2 post-processing step. In this embodiment, the material of the second buffer layer 105 is preferably GaN, i.e., the second buffer layer 105 is preferably a GaN layer. The thickness of the second buffer layer 105 is preferably 0.8 μm to 2 μm, for example, 1.3 μm.

[0051] After the step of growing the second buffer layer 105, an active layer is grown on the second buffer layer 105. In this embodiment, the active layer may include a channel layer 106 and a barrier layer 107. Therefore, after the step of growing the second buffer layer 105, a channel layer 106 is grown on the second buffer layer 105. In this embodiment, the material of the channel layer 106 is preferably GaN, that is, the channel layer 106 is preferably a GaN layer. The channel layer 106 is preferably an unintentionally doped layer, and its thickness is preferably 100 nm to 800 nm, for example, 500 nm.

[0052] Following the step of growing the channel layer 106, a barrier layer 107 is grown on the channel layer 106. In this embodiment, the material of the barrier layer 107 is preferably a nitride, such as AlGaN. Further, the Al composition in the barrier layer 107 is gradually varied, and the Al composition is preferably 2% to 30%. The thickness of the barrier layer 107 is preferably 10 nm to 30 nm, for example, 20 nm.

[0053] After growing the barrier layer 107, a p-type layer 108 is grown on the barrier layer 107. In this embodiment, the material of the p-type layer 108 can be AlGaN, and its Al content is preferably less than or equal to 20%. In other embodiments, the p-type layer 108 can also be other materials, such as GaN, InGaN, etc., with different combinations of dopants and different doping concentrations. The thickness of the p-type layer 108 is preferably 30 nm to 120 nm, for example, 80 nm. In this step, the p-type layer 108 completely covers the barrier layer 107.

[0054] In this embodiment, after the step of growing the P-type layer 108, photolithography and etching processes are performed to remove a portion of the P-type layer 108, exposing the upper surface of the barrier layer 107. The remaining P-type layer 108 serves as the gate structure layer. The etching process is preferably a dry etching process, but is not limited thereto.

[0055] After performing the etching process, the method for fabricating the gallium nitride power device may further include:

[0056] Step S4: A passivation layer 201 is formed on the P-type layer 108, and the passivation layer 201 also covers the exposed barrier layer 107;

[0057] Step S5: Etch the passivation layer 201 to form a first via, a second via, and a third via. The first via exposes the P-type layer 108, and the second and third vias expose the barrier layer 107. The first via is located between the second and third vias.

[0058] Step S6: Form a gate electrode 202 in the first via, form a source electrode 203 in the second via, and form a drain electrode 204 in the third via.

[0059] Step S4 is performed to form a passivation layer 201. In this embodiment, the material of the passivation layer 201 is preferably an insulating material, more preferably at least one of SiO2, SiN, and AlN, but not limited thereto. The passivation layer 201 serves as a gate insulating material, used to isolate the gate electrode 202 and the barrier layer 107. The formation process of the passivation layer 201 can be a physical deposition process or a chemical deposition process, which will not be elaborated here.

[0060] Step S5 is executed to etch the passivation layer 201, i.e., to pattern the passivation layer 201. In this embodiment, a photolithography process is required before etching the passivation layer 201 to define the area of ​​the passivation layer 201 to be etched. The etching process is preferably a dry etching process, but is not limited thereto. In this embodiment, three through-holes penetrating the passivation layer 201 are formed by the etching process, namely a first through-hole, a second through-hole, and a third through-hole. The first through-hole can expose the P-type layer 108, and the second and third through-holes can expose the barrier layer 107, with the first through-hole located between the second and third through-holes.

[0061] Step S6 is executed to form the gate electrode 202, source electrode 203, and drain electrode 204, i.e., to fabricate the gate electrode, source electrode 203, and drain electrode 204. In this embodiment, metal material is formed in the through-holes using a deposition process or an electroplating process to prepare each electrode. The metal material filling the first through-hole forms the gate electrode 202, the metal material filling the second through-hole forms the source electrode 203, and the metal material filling the third through-hole forms the drain electrode 204. In this embodiment, the material of the gate electrode 202 is preferably one of Ti, Al, Ni, Au, Ag, Pt, W, Cu, Ta, Mo, Cu, TiW, TiN, or an alloy combination thereof. After forming the gate electrode 202, a high-temperature annealing process is performed, and this high-temperature annealing process can be a conventional electrode high-temperature annealing process, which will not be described in detail here. The gate electrode 202 is in contact with the P-type layer 108, and the gate electrode 202 and the P-type layer 108 form an ohmic contact or a Schottky contact through high-temperature annealing.

[0062] In this embodiment, the materials of the source electrode 203 and the drain electrode 204 are preferably one of Ti, Al, Ni, Au, Ag, Pt, W, Cu, Ta, Mo, Cu, TiW, TiN, or an alloy combination thereof. After forming the source electrode 203 and the drain electrode 204, a high-temperature annealing process is performed, and this high-temperature annealing process can be a conventional electrode high-temperature annealing process, which will not be described in detail here. The source electrode 203 and the drain electrode 204 are in contact with the barrier layer 107, and an ohmic contact is formed between the source electrode 203 and the drain electrode 204 and the barrier layer 107 through high-temperature annealing. In this embodiment, the formation process and the annealing process of the gate electrode 202, the source electrode 203, and the drain electrode 204 can be performed simultaneously.

[0063] In other embodiments, the gate electrode 202 may be formed first, followed by a high-temperature annealing process for the gate electrode 202, then the source electrode 203 and the drain electrode 204 may be formed, and finally a high-temperature annealing process for the source electrode 203 and the drain electrode 204 may be performed.

[0064] In summary, this invention employs a two-stage nucleation process: a first nucleation layer located between the substrate and the first buffer layer, and a second nucleation layer composed of the first buffer layer and nanoparticles. The first buffer layer provides high-quality nanoseed crystals, while the nanoparticles block the longitudinal extension of defects and improve lateral growth. Therefore, this two-stage nucleation growth scheme can yield a high-quality epitaxial structure, effectively improving the growth quality, crystal structure, and stress distribution of the epitaxial structure, enhancing the crystal quality of the active layer, reducing leakage channels, and improving the reliability of gallium nitride power devices.

[0065] Secondly, the first and second buffer layers of this invention can be made of GaN material, resulting in a smaller thermal stress mismatch between the structural layers, a smooth surface, and less susceptibility to cracking.

[0066] Moreover, the preparation method of this utility model is compatible with conventional processes, requires no additional expensive equipment and technology, is simple, easy to implement, and has low cost; and is compatible with commercial 6-inch and 8-inch production lines.

[0067] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention's technical solutions using the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention's technical solutions. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention's technical solutions, shall still fall within the protection scope of the present invention's technical solutions.

[0068] Furthermore, it should be understood that this invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of this invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. The structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way, unless the context clearly indicates otherwise.

Claims

1. A gallium nitride power device, characterized in that, From bottom to top, it includes: a substrate, a first nucleation layer, a first buffer layer, several nanoparticles, a second buffer layer, an active layer, and a P-type layer.

2. The gallium nitride power device as described in claim 1, characterized in that, The first buffer layer and the nanoparticles together form the second nucleation layer.

3. The gallium nitride power device as described in claim 1, characterized in that, The nanoparticles are SiC nanoparticles, SiN nanoparticles, or composite nanoparticles composed of SiC and SiN, and the nanoparticles are spaced apart on the first buffer layer.

4. The gallium nitride power device as described in claim 1, characterized in that, The thickness of the nanoparticles is 0.5 nm to 5 nm.

5. The gallium nitride power device as described in claim 1, characterized in that, The first nucleation layer is an AlN layer.

6. The gallium nitride power device as described in claim 1, characterized in that, The thickness of the first nucleation layer is 100nm to 300nm.

7. The gallium nitride power device as described in claim 1, characterized in that, The substrate is a heterogeneous substrate.

8. The gallium nitride power device as described in claim 1, characterized in that, The first buffer layer is a GaN layer or a composite layer consisting of a GaN layer and an AlGaN layer.

9. The gallium nitride power device as described in claim 1, characterized in that, The thickness of the first buffer layer is 500nm to 2000nm.

10. The gallium nitride power device as described in claim 1, characterized in that, The second buffer layer is a GaN layer.

11. The gallium nitride power device as claimed in claim 1, characterized in that, The thickness of the second buffer layer is 0.8 μm to 2 μm.

12. The gallium nitride power device as described in claim 1, characterized in that, The P-type layer covers a portion of the active layer. The gallium nitride power device further includes a passivation layer, a gate electrode, a source electrode, and a drain electrode. The passivation layer covers both the P-type layer and the active layer. The gate electrode penetrates the passivation layer and contacts the P-type layer. The source electrode and drain electrode penetrate the passivation layer and contact the active layer. The source electrode and drain electrode are located on opposite sides of the gate electrode.

13. The gallium nitride power device as described in claim 1, characterized in that, The gallium nitride power device is a HEMT device.

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