Semiconductor device

Abstract

The utility model discloses a kind of semiconductor devices, the semiconductor device includes substrate and epitaxial layer arranged on the substrate;The epitaxial layer includes barrier layer and passivation layer located at the barrier layer far from the substrate side;Gate recess is opened on the passivation layer, and the gate recess exposes the part surface of the barrier layer;The roughness of the surface of the barrier layer corresponding the gate recess is greater than zero.The utility model can improve the reliability of semiconductor device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Semiconductor devices, such as enhanced high electron mobility transistors (HEMTs), have important applications in modern electronics.

[0003] However, the reliability of semiconductor devices in related technologies needs to be improved. Utility Model Content

[0004] This invention provides a semiconductor device to improve the reliability of semiconductor devices.

[0005] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising a substrate and an epitaxial layer disposed on the substrate;

[0006] The epitaxial layer includes a barrier layer and a passivation layer located on the side of the barrier layer away from the substrate; a gate groove is formed on the passivation layer, and the gate groove exposes a portion of the surface of the barrier layer;

[0007] The surface roughness of the barrier layer corresponding to the gate groove is greater than zero.

[0008] Optionally, the surface of the barrier layer corresponding to the passivation layer is a flat surface.

[0009] Optionally, the thickness of the barrier layer corresponding to the gate recess portion is less than the thickness of the barrier layer corresponding to the passivation layer portion.

[0010] Optionally, the semiconductor device further includes a gate structure disposed within the gate recess.

[0011] Optionally, the gate structure is flush with the surface of the passivation layer, which is away from the substrate.

[0012] Optionally, the gate structure includes a doped nitride semiconductor layer and a gate sequentially stacked on the barrier layer.

[0013] Optionally, the passivation layer is an in-situ grown layer of the barrier layer.

[0014] Optionally, the epitaxial layer further includes a buffer layer and a channel layer, wherein the channel layer is located on the side of the barrier layer closer to the substrate, and the buffer layer is located between the channel layer and the substrate.

[0015] Optionally, the passivation layer is further provided with a source groove and a drain groove, wherein the source groove exposes a portion of the surface of the barrier layer, and the drain groove exposes a portion of the surface of the barrier layer;

[0016] The surface of the barrier layer corresponding to the source groove is a flat surface; the surface of the barrier layer corresponding to the drain groove is a flat surface.

[0017] Optionally, the barrier layer is made of aluminum gallium nitride or indium gallium nitride, and the passivation layer is made of silicon oxide or silicon nitride.

[0018] The technical solution of this utility model embodiment uses a semiconductor device including a substrate and an epitaxial layer disposed on the substrate; the epitaxial layer includes a barrier layer and a passivation layer located on the side of the barrier layer away from the substrate; a gate groove is formed on the passivation layer, and the gate groove exposes a portion of the surface of the barrier layer; the roughness of the surface of the barrier layer corresponding to the gate groove is greater than zero. When a bias voltage controlling the conduction of the semiconductor device is applied, electrons below the gate groove are attracted to move towards the gate groove. When electrons cross the rough surface of the barrier layer, a certain amount of scattering occurs, thereby reducing the energy of electrons reaching the gate, thereby improving the gate withstand voltage and enhancing the reliability of the semiconductor device.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present utility model;

[0023] Figure 3 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present utility model;

[0024] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1 The semiconductor device includes a substrate 1 and an epitaxial layer 2 disposed on the substrate 1. The epitaxial layer 2 includes a barrier layer 23 and a passivation layer 24 located on the side of the barrier layer 23 away from the substrate 1; a gate recess Gap1 is formed on the passivation layer 24, and the gate recess Gap1 exposes a portion of the surface of the barrier layer 23; the surface roughness of the barrier layer 23 corresponding to the gate recess Gap1 is greater than zero.

[0028] Specifically, the semiconductor device is, for example, a HEMT device. Substrate 1 provides support for the entire semiconductor device; substrate 1 is, for example, a silicon substrate. Epitaxial layer 2 is formed by epitaxial growth on substrate 1. Epitaxial layer 2 includes a heterojunction, in which a two-dimensional electron gas is generated, forming a conductive channel. Passivation layer 24 serves as a surface passivation layer. A gate recess Gap1 is formed on passivation layer 24, and a gate structure is disposed in gate recess Gap1. When no bias voltage is applied, the gate structure can deplete the underlying two-dimensional electron gas, thereby closing the conductive channel. When a positive bias voltage is applied to the gate structure, the gate structure attracts electrons, causing the conductive channel to reform, allowing current to flow in the conductive channel.

[0029] However, when the gate structure attracts electrons, some of the electrons' energy is transferred to the gate structure, affecting it and reducing the reliability of the semiconductor device. In this embodiment, the surface roughness of the portion of the barrier layer 23 corresponding to the gate groove Gap1 (hereinafter referred to as the target portion 231) is set to be greater than zero. That is, the surface of the target portion 231 near the passivation layer 24 is not a flat surface, but has a certain degree of roughness. When electrons cross the rough surface, some scattering occurs, thereby reducing the energy of the electrons reaching the gate, thus improving the gate withstand voltage and enhancing the reliability of the semiconductor device. It should be noted that the surface of the barrier layer corresponding to the gate groove is the surface of the barrier layer covered by the orthogonal projection of the gate groove along the thickness direction of the semiconductor device.

[0030] The technical solution of this embodiment employs a semiconductor device including a substrate and an epitaxial layer disposed on the substrate. The epitaxial layer includes a barrier layer and a passivation layer located on the side of the barrier layer away from the substrate. A gate groove is formed on the passivation layer, exposing a portion of the surface of the barrier layer. The surface roughness of the barrier layer corresponding to the gate groove is greater than zero. When a bias voltage controlling the conduction of the semiconductor device is applied, electrons below the gate groove are attracted to move towards the gate groove. When electrons cross the rough surface of the barrier layer, a certain amount of scattering occurs, thereby reducing the energy of the electrons reaching the gate, thus improving the gate withstand voltage and enhancing the reliability of the semiconductor device.

[0031] It should be noted that the specific value of the roughness of the target portion 231 is not limited, as long as the surface is not uneven. For example, the roughness Ra of the target portion 231 may be greater than 0.5 nm, and in some embodiments, it may be greater than 1 nm. Of course, the meaning of "flat" is not absolute flatness, as long as it is flat within the allowable range of process error, for example, a roughness of less than 0.5 nm can be understood as flat.

[0032] Optionally, in some embodiments, the surface roughness of the target portion 231 can be made greater than zero by means of dry etching or wet etching.

[0033] Optionally, continue to refer to Figure 1 The surface of the barrier layer 23 corresponding to the passivation layer 24 is a flat surface.

[0034] Specifically, the surface of the barrier layer 23 corresponding to the passivation layer 24 is the part where the barrier layer 23 and the passivation layer 24 meet. If the surface of the barrier layer 23 corresponding to the passivation layer 24 is rough, electrons in the channel will be trapped in the rough interface, resulting in current collapse and a sharp degradation of the dynamic on-resistance. This also leads to problems such as increased gate leakage current, decreased reliability, and lower carrier mobility. By making the surface of the barrier layer 23 corresponding to the passivation layer 24 a smooth surface, electrons can move more smoothly, improving the current collapse effect and further enhancing the reliability of the semiconductor device.

[0035] Optionally, in some embodiments, the maximum thickness H1 of the barrier layer 23 corresponding to the gate recess Gap1 portion (i.e., the target portion 231) is (i.e., Figure 1 The thickness between the sharpest point of the upper surface of the target portion 231 and the lower surface of the target portion 231 is equal to the thickness H3 of the portion of the barrier layer 23 corresponding to the passivation layer 24; the minimum thickness H2 of the barrier layer 23 corresponding to the gate recess Gap1 portion (i.e., the target portion 231) is equal to the thickness H2 of the passivation layer 24 corresponding to the passivation layer 24. Figure 1 The thickness between the left and right planar regions on the upper surface of the target portion 231 and the lower surface of the target portion 231 is less than the thickness H3 of the passivation layer 24 corresponding to the barrier layer 23; thus, the overall thickness of the gate recess Gap1 portion of the barrier layer 23 is less than the thickness of the passivation layer 24 corresponding to the barrier layer 23.

[0036] Alternatively, in some other embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of another semiconductor device provided by an embodiment of the present invention. In this embodiment, the maximum thickness H1 of the barrier layer 23 corresponding to the gate recess Gap1 portion (i.e., the target portion 231) is less than the thickness H3 of the portion of the barrier layer 23 corresponding to the passivation layer 24. That is, the thickness of any part of the target portion 231 is less than the thickness of the portion of the barrier layer 23 corresponding to the passivation layer 24. By thinning the thickness of the barrier layer corresponding to the gate recess, the threshold voltage of the semiconductor device can be controlled, for example, the absolute value of the threshold voltage can be reduced. However, in related technologies, the thickness of the barrier layer is equal everywhere, which means that the thickness of the barrier layer 23 corresponding to the passivation layer 24 will be reduced simultaneously; a thinner barrier layer 23 corresponding to the passivation layer 24 will result in a larger channel resistance, that is, a larger on-resistance of the semiconductor device. In this embodiment, setting the thickness of the barrier layer 23 corresponding to the gate recess Gap1 portion to be less than the thickness of the corresponding passivation layer 24 portion can both control the threshold voltage of the semiconductor device and reduce the absolute value of the threshold voltage of the semiconductor device; and can also avoid excessive on-resistance of the semiconductor device.

[0037] Optionally, Figure 3This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, with reference to... Figure 3 The semiconductor device also includes a gate structure 3, which is disposed within a gate recess.

[0038] Specifically, the conduction state of the semiconductor device can be controlled by controlling the bias voltage applied to the gate structure 3. For example, when no bias voltage is applied to the gate structure 3, the gate structure 3 depletes the two-dimensional electron gas below it, and the semiconductor device is turned off. When a positive bias voltage is applied to the gate structure 3, the gate structure 3 attracts electrons, causing the conductive channel to regenerate, and the semiconductor device is turned on, allowing current to flow.

[0039] Optionally, such as Figure 3 As shown, the gate structure 3 includes a doped nitride semiconductor layer 31 and a gate 32 sequentially stacked on a barrier layer 23. The doped nitride semiconductor layer 31 is, for example, p-type doped gallium nitride. When no bias voltage is applied to the gate structure 3, the p-type doped gallium nitride depletes the underlying two-dimensional electron gas, thereby turning off the semiconductor device. The gate 32 is, for example, a metal layer, such as titanium nitride. After a positive bias voltage is applied to the gate structure, the gate structure attracts electrons. Some high-energy electrons reach the interface between the doped nitride semiconductor layer 31 and the gate 32, affecting the interface performance and leading to gate reliability failure. In this embodiment, by setting the surface roughness of the gate groove corresponding to the barrier layer to be greater than zero, electrons will be scattered when passing through the surface of the gate groove corresponding to the barrier layer, thereby reducing the energy of electrons reaching the interface between the doped nitride semiconductor layer 31 and the gate 32, improving the impact on the interface, and enhancing the reliability of the semiconductor device.

[0040] Optionally, continue to refer to Figure 3 In some embodiments, the gate structure 3 is flush with the surface of the passivation layer 24, which is also flush with the surface of the passivation layer 24. When subsequently routing the traces corresponding to the gate structure 3, these traces are placed on a flat surface, reducing routing difficulty and further improving the reliability of the semiconductor device. It should be noted that "flat surface" does not mean strictly flat; it can be flat within the allowable range of process tolerances.

[0041] Optionally, the passivation layer 24 is an in-situ growth layer of the barrier layer 23. That is, the passivation layer 24 is formed in-situ based on the barrier layer 23. In this embodiment, after growing the barrier layer into the epitaxial layer on the substrate 1 using an MOCVD (Metal-organic Chemical Vapor Deposition) machine, instead of continuing to grow a doped nitride semiconductor layer, the passivation layer 24 is grown in-situ first. Due to the in-situ growth method, there are fewer interface defects between the passivation layer 24 and the barrier layer 23, and the interface between the passivation layer 24 and the barrier layer 23 is smoother, improving the reliability of the semiconductor device. In addition, compared with the method of first growing the doped nitride semiconductor layer, it is not necessary to etch the doped nitride semiconductor layer other than the gate structure, so as not to damage the surface of the part of the barrier layer corresponding to the passivation layer, ensuring the interface quality of the part of the barrier layer corresponding to the passivation layer, and greatly improving the reliability of the semiconductor device. More specifically, since the interface quality of the part of the barrier layer corresponding to the passivation layer is better, it can improve the dynamic resistance drift problem of semiconductor devices.

[0042] It should be noted that after the passivation layer is grown in situ, a dry etching method can be used to create trenches on the passivation layer to form gate trenches. The interface of the barrier layer can be cleaned by steps such as wet cleaning. Subsequently, a doped nitride semiconductor layer is grown using MOCVD, and then the gate is deposited using PVD (Physical Vapor Deposition).

[0043] Optionally, refer to Figures 1 to 3 The epitaxial layer also includes a buffer layer 21 and a channel layer 22. The channel layer 22 is located on the side of the barrier layer 23 close to the substrate 1, and the buffer layer 21 is located between the channel layer 22 and the substrate 1.

[0044] Specifically, the buffer layer 21 is made of materials such as gallium nitride, which can improve the epitaxial quality of the subsequent channel layer 22. The channel layer 22 is made of materials such as gallium nitride, and the barrier layer 23 is made of materials such as aluminum gallium nitride or indium gallium nitride. Gallium nitride 22 and barrier layer 23 form a heterojunction, forming a two-dimensional electron gas at the interface, which allows the semiconductor device to conduct electricity.

[0045] Optionally, Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, with reference to... Figure 4The passivation layer 24 also has source and drain grooves. The source groove exposes a portion of the barrier layer surface, and the drain groove exposes a portion of the barrier layer surface. A source electrode 4 is disposed within the source groove, and a drain electrode 5 is disposed within the drain groove. The surface of the barrier layer 24 corresponding to the source groove is a flat surface, and the surface of the barrier layer corresponding to the drain groove is a flat surface. Metal electrodes need to be disposed on the surfaces of the barrier layer corresponding to the source and drain grooves. Making these surfaces flat can reduce the difficulty of forming metal electrodes and improve the quality and performance of the formed metal electrodes, further improving the reliability of semiconductor devices. It should be emphasized that the flat surface described in this article is not flat in an absolute sense; as long as the roughness is less than a certain value, it can be considered a flat surface.

[0046] Alternatively, in some embodiments, the material of the passivation layer is, for example, silicon oxide or silicon nitride.

[0047] It should be understood that the various forms of the process shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this utility model can be achieved, and this is not limited herein.

[0048] The specific embodiments described above do not constitute a limitation on the scope of protection of this utility model. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the scope of protection of this utility model.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a substrate and an epitaxial layer disposed on the substrate; The epitaxial layer includes a barrier layer and a passivation layer located on the side of the barrier layer away from the substrate; a gate groove is formed on the passivation layer, and the gate groove exposes a portion of the surface of the barrier layer; The surface roughness of the barrier layer corresponding to the gate groove is greater than zero.

2. The semiconductor device according to claim 1, characterized in that, The surface of the barrier layer corresponding to the passivation layer is a flat surface.

3. The semiconductor device according to claim 1, characterized in that, The thickness of the barrier layer corresponding to the gate recess portion is less than the thickness of the barrier layer corresponding to the passivation layer portion.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate structure disposed within the gate recess.

5. The semiconductor device according to claim 4, characterized in that, The gate structure is flush with the surface of the passivation layer that is also flush with the surface of the substrate.

6. The semiconductor device according to claim 4, characterized in that, The gate structure includes a doped nitride semiconductor layer and a gate sequentially stacked on the barrier layer.

7. The semiconductor device according to claim 1, characterized in that, The passivation layer is an in-situ growth layer of the barrier layer.

8. The semiconductor device according to claim 1, characterized in that, The epitaxial layer further includes a buffer layer and a channel layer, wherein the channel layer is located on the side of the barrier layer closer to the substrate, and the buffer layer is located between the channel layer and the substrate.

9. The semiconductor device according to claim 1, characterized in that, The passivation layer is further provided with a source groove and a drain groove, the source groove exposing a portion of the surface of the barrier layer, and the drain groove exposing a portion of the surface of the barrier layer; The surface of the barrier layer corresponding to the source groove is a flat surface; The surface of the barrier layer corresponding to the drain groove is a flat surface.

10. The semiconductor device according to claim 1, characterized in that, The barrier layer is made of aluminum gallium nitride, and the passivation layer is made of silicon oxide or silicon nitride.

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