Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device can include a first nanowire, a first gate structure surrounding the first nanowire, a first inner spacer on the first nanowire and the first gate structure, a first source / drain region on the first nanowire and the first inner spacer, a second nanowire under the first nanowire, a second gate structure surrounding the second nanowire, a second inner spacer on the second nanowire and the second gate structure, and a second source / drain region on the second nanowire and the second inner spacer. The first inner spacer can have a first outer sidewall having a first width. The second inner spacer can have a second outer sidewall having a second width that is less than the first width.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and using photolithography to pattern the various material layers to form circuit elements and components on them.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards higher device density, higher efficiency, and lower cost, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). However, as the minimum feature size decreases, additional features are introduced. Utility Model Content

[0004] Some embodiments disclosed herein provide a semiconductor device including a first nanostructure, a first gate structure, a first internal spacer, a first source / drain region, a second nanostructure, a second gate structure, a second internal spacer, and a second source / drain region. The first gate structure surrounds the first nanostructure. The first internal spacer is located on the first nanostructure and the first gate structure. The first source / drain region is located on the first nanostructure and the first internal spacer, and the first internal spacer has a first outer sidewall having a first width. The second nanostructure is located below the first nanostructure. The second gate structure surrounds the second nanostructure. The second internal spacer is located on the second nanostructure and the second gate structure. The second source / drain region is located on the second nanostructure and the second internal spacer, and the second internal spacer has a second outer sidewall having a second width smaller than the first width.

[0005] Some embodiments disclosed herein provide a semiconductor device including a first nanostructure, a first gate structure, a first internal spacer, a first source / drain region, a second nanostructure, a second gate structure, a second internal spacer, and a second source / drain region. The first gate structure surrounds the first nanostructure. The first internal spacer is located on the first nanostructure and the first gate structure. The first source / drain region is located on the first nanostructure and the first internal spacer, and the first internal spacer has a first inner sidewall having a first curvature. The second nanostructure is located below the first nanostructure. The second gate structure surrounds the second nanostructure. The second internal spacer is located on the second nanostructure and the second gate structure. The second source / drain region is located on the second nanostructure and the second internal spacer, wherein the second internal spacer has a second inner sidewall having a second curvature smaller than the first curvature.

[0006] Some embodiments disclosed herein provide a semiconductor device comprising a first nanostructure, a first gate structure, a first internal spacer, a first source / drain region, a second nanostructure, a second gate structure, a second internal spacer, and a second source / drain region. The first gate structure surrounds the first nanostructure. The first internal spacer is located on the first nanostructure and the first gate structure. The first source / drain region is located on the first nanostructure and the first internal spacer, wherein the first source / drain region is doped with a first dopant. The second nanostructure is located below the first nanostructure. The second gate structure surrounds the second nanostructure. The second internal spacer is located on the second nanostructure and the second gate structure. The second source / drain region is located on the second nanostructure and the second internal spacer, wherein the second source / drain region is doped with a second dopant, and wherein the first dopant and the second dopant have opposite conductivity types. Attached Figure Description

[0007] When with attachment Figure 1 When reading this document, it is best to understand the specifications as described below. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for ease of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view illustrating an example of stacked transistors according to some embodiments;

[0009] Figures 2 to 13 Various views of intermediate steps in the fabrication of stacked transistors according to some embodiments.

[0010] [Symbol Explanation]

[0011] 10: Stacked transistors

[0012] 10L: Field-Effect Transistor

[0013] 10U: Field-Effect Transistor

[0014] 20:Substrate

[0015] 20': Semiconductor fin

[0016] 22: Multi-layer stacking

[0017] 24: Feigning a nanostructure

[0018] 24A: Feigned Nanostructure

[0019] 24B: Feigned Nanostructure

[0020] 26: Semiconductor Nanostructures

[0021] 26L: Lower semiconductor nanostructure

[0022] 26U: Upper semiconductor nanostructure

[0023] 28: Semiconductor Strip

[0024] 30: Dielectric layer

[0025] 32: Sacrificial Layer

[0026] 34: STI area

[0027] 36: Dummy dielectric layer

[0028] 38: Dummy gate layer

[0029] 40: Masking layer

[0030] 42: Dummy gate stack

[0031] 44: Gate spacer

[0032] 46: Source / Drain Groove

[0033] 54: Internal spacers

[0034] 54L: Lower internal spacer

[0035] 54U: Upper internal spacer

[0036] 56: Dielectric isolation layer

[0037] 62: Source / Drain Region

[0038] 62L: Lower epitaxial source / drain region

[0039] 62U: Upper epitaxial source / drain region

[0040] 66: First contact etch termination layer

[0041] 68: First ILD

[0042] 70: Second CESL

[0043] 72: Second ILD

[0044] 78: Gate Dielectric

[0045] 80: Gate electrode

[0046] 80L: Lower gate electrode

[0047] 80U: Upper gate electrode

[0048] 90: Gate structure

[0049] 90L: Lower gate structure

[0050] 90U: Upper gate structure

[0051] 92: Gate mask

[0052] 94: Metal-Semiconductor Alloy Region

[0053] 96: Source / Drain Contacts

[0054] 104:ESL

[0055] 106: Third ILD

[0056] 108: Gate contact

[0057] 110: Source / Drain via

[0058] 112: Device Layer

[0059] 114: Front-side interconnect structure

[0060] 116: Dielectric layer

[0061] 118: Electrical conductivity characteristics

[0062] A-A': Reference section

[0063] W1: First width

[0064] W2: Second width Detailed Implementation

[0065] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0066] Furthermore, for ease of description, spatial relative terms such as “below,” “lower,” “lower,” “overlapping,” “upper,” and the like are used herein to describe the relationship between one component or feature as illustrated in the accompanying drawings and another component or feature(s). In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly.

[0067] Various embodiments provide semiconductor devices and methods of forming the same. The semiconductor device may include a stacked transistor comprising an upper transistor and a lower transistor. The upper transistor and the lower transistor may have different device types (e.g., n-type and p-type). The upper transistor may include an upper semiconductor nanostructure as a channel region, and the lower transistor may include a lower semiconductor nanostructure as a channel region. By forming different materials on the upper and lower semiconductor nanostructures, different stresses (and corresponding strains) can be induced in the upper and lower semiconductor nanostructures. Therefore, the overall performance of the stacked transistor can be improved.

[0068] Figure 1 Examples of stacked transistors 10 (including field-effect transistors (FETs) 10U and 10L) according to some embodiments are illustrated. Figure 1For perspective purposes and for clarity, some features of the stacked transistor 10 are omitted. The stacked transistor 10 includes a plurality of vertically stacked FETs. For example, the stacked transistor 10 may include a lower nanostructure FET 10L of a first device type (e.g., n-type or p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type or n-type). When the stacked transistor 10 is a complementary field-effect transistor (CFET), the second device type of the upper nanostructure FET 10U is the opposite of the first device type of the lower nanostructure FET 10L. The upper nanostructure FET 10U and the lower nanostructure FET 10L include semiconductor nanostructures 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 acts as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor 10 may be applied to other types of transistors, nanofield-effect transistors (nanoFETs), finFETs, or the like.

[0069] A gate dielectric 78 surrounds individual semiconductor nanostructures 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the individual gate electrodes 80. Depending on the context, each of the source / drain regions 62 may individually or collectively refer to a source or a drain. Isolation features (not shown) may be formed to isolate selected source / drain regions in the source / drain regions 62 and / or selected gate electrodes in the gate electrodes 80.

[0070] Figure 1 Further illustrated is reference section A-A', a vertical section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor 10 and along, for example, the current direction between the source / drain regions 62 of the stacked transistor 10. For clarity, reference section A-A' is shown in subsequent figures.

[0071] Figures 2 to 13 Various views of intermediate steps in the fabrication of a stacked transistor according to some embodiments, the stacked transistor being similar to Figure 1 The stacked transistor 10 shown. Figure 2 This is a perspective view. Figures 3 to 13 for Figure 2 The structure shown is along with Figure 1 A cross-sectional view of a reference section similar to the reference section A-A' shown in the figure.

[0072] exist Figure 2 The invention provides a wafer including a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, silicon-doped carbon, III-V compound semiconductors, or similar materials, or combinations thereof.

[0073] Semiconductor strips 28 are formed extending upward from substrate 20. Each of the semiconductor strips 28 includes semiconductor fins 20' (patterned portions of substrate 20) and a multilayer stack 22. The stacked elements of the multilayer stack 22 are hereinafter referred to as nanostructures. Specifically, the multilayer stack 22 includes dummy nanostructures 24A and dummy nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Dummy nanostructures 24A and dummy nanostructures 24B can be further collectively referred to as dummy nanostructure 24, and the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0074] The dummy nanostructure 24A is formed of a first semiconductor material, and the dummy nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the dummy nanostructure 24B can be removed at a faster rate than the dummy nanostructure 24A.

[0075] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The one or more third semiconductor materials can be selected from candidate semiconductor materials of substrate 20. Lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the dummy nanostructure 24 have high etch selectivity towards the one or more third semiconductor materials of semiconductor nanostructure 26. Therefore, the dummy nanostructure 24 can be selectively removed in subsequent process steps without significantly removing semiconductor nanostructure 26. In some embodiments, dummy nanostructure 24A is formed of or contains silicon-germanium, semiconductor nanostructure 26 is formed of silicon, and dummy nanostructure 24B can be formed of germanium or silicon-germanium, wherein the percentage of germanium atoms is higher than that of dummy nanostructure 24A.

[0076] The lower semiconductor nanostructure 26L will serve as the channel region for the lower nanostructure FET of the stacked transistor. The upper semiconductor nanostructure 26U will serve as the channel region for the upper nanostructure FET of the stacked transistor. The semiconductor nanostructure 26 immediately above / below (e.g., in contact with) the dummy nanostructure 24B can be used for isolation and may or may not serve as the channel region for the stacked transistor. Subsequently, the dummy nanostructure 24B will be replaced by an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0077] To form the semiconductor strip 28, first, second, and third semiconductor material layers (as illustrated and described above) can be deposited over the substrate 20. The first, second, and third semiconductor material layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or similar methods. Then, patterning processes can be applied to the first, second, and third semiconductor material layers and the substrate 20 to define the semiconductor strip 28, which includes semiconductor fins 20', dummy nanostructures 24, and semiconductor nanostructures 26.

[0078] For example, the patterning process may include one or more photolithography processes, including dual or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to allow the creation of patterns with, for example, smaller pitches than could be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch the first, second, and third semiconductor material layers and the substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or similar combinations thereof. Etching may be anisotropic.

[0079] Just like Figure 2As shown, a shallow trench isolation (STI) region 34 is formed above the substrate 20 and between adjacent semiconductor strips 28. The STI region 34 may include a dielectric liner and a dielectric material located above the dielectric liner. The dielectric liner and dielectric material may include oxides (such as silicon oxide), nitrides (such as silicon nitride), similar materials, or combinations thereof. Forming the STI region 34 may include depositing one or more dielectric layers and performing a planarization process, such as chemical mechanical polishing (CMP), mechanical polishing, or similar processes, to remove excess dielectric material. Deposition processes may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), similar materials, or combinations thereof. In some embodiments, the STI region 34 includes silicon oxide formed by an FCVD process followed by an annealing process. One or more dielectric layers are then recessed to define the STI region 34. One or more dielectric layers may be recessed so that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes higher than the remaining STI region 34.

[0080] After forming the STI region 34, a dummy gate stack 42 may be formed above and along the sidewalls of the upper portion of the semiconductor strip 28 (the portion that protrudes higher than the STI region 34). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or comprised of, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed above the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, via physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium (polycrystalline SiGe), or the like. A mask layer 40 is formed over the planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, or the like. Next, the mask layer 40 may be patterned via photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38 and, possibly, the dummy dielectric layer 36. The remainder of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 forms a dummy gate stack 42.

[0081] exist Figure 3 In this process, gate spacers 44 and source / drain trenches 46 are formed. First, gate spacers 44 are formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. Gate spacers 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, which can be formed by deposition processes such as CVD, ALD, or the like.

[0082] Subsequently, source / drain recesses 46 are formed in the semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into the semiconductor fin 20'. The bottom surface of the source / drain recesses 46 may be above, below, or flush with the top surface of the STI region 34. During the etching process, gate spacers 44 and dummy gate stacks 42 shield portions of the semiconductor strip 28. Etching may include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain recesses 46 when a selected depth is reached.

[0083] exist Figure 4 In this process, a dielectric layer 30 is formed in a source / drain recess 46. The dielectric layer 30 may fill the lower portion of the source / drain recess 46 and may cover the sidewalls of the lower semiconductor nanostructure 26L and the sidewalls of the dummy nanostructure 24A (e.g., the dummy nanostructure 24A located between the dummy nanostructure 24B and the semiconductor fin 20') that contacts the lower semiconductor nanostructure 26L. After forming the dielectric layer 30, the sidewalls of the dummy nanostructure 24A (e.g., the dummy nanostructure 24A located between the dummy nanostructure 24B and the dummy gate stack 42) that contacts the upper semiconductor nanostructure 26U may be exposed. The dielectric layer 30 may be used to protect the dummy nanostructure 24A during subsequent etching processes. In some embodiments, the sidewalls of the upper semiconductor nanostructure 26U that contacts the dummy nanostructure 24B are in contact with the dielectric layer 30. The dielectric layer 30 may be removed in subsequent processes and may be referred to as a sacrificial layer. Although in Figure 4 The dielectric layer 30 is illustrated as having a flat top surface, but in other embodiments, the dielectric layer 30 may have a curved surface, such as a recessed top surface or a protruding top surface.

[0084] The dielectric layer 30 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or the like. The formation of the dielectric layer 30 may include a suitable deposition process such as CVD, FCVD, or the like. In embodiments using FCVD, the formation of the dielectric layer 30 includes a deposition step, a curing step, and an annealing step. In the deposition step, precursors such as trisilaneamine, ammonia, and oxygen may be used. The deposited film may comprise elements such as silicon, oxygen, carbon, hydrogen, nitrogen, or the like. The weight percentage of oxygen in the deposited film may range from about 0% to about 90%. The weight percentage of carbon in the deposited film may range from about 0% to about 90%. The weight percentage of hydrogen in the deposited film may range from about 0% to about 90%. The weight percentage of nitrogen in the deposited film may range from about 0% to about 90%. The deposited film may then be densified by a curing step under ozone or ultraviolet radiation for less than or equal to about 180 seconds.

[0085] The annealing step can be performed after the curing step and can be a single annealing process or a double annealing process. A single annealing process can be a dry annealing treatment. During the dry annealing treatment of a single annealing process, the deposited film can be annealed in an inert gas environment (e.g., nitrogen, helium, argon) for about 1 minute to about 28 hours. The annealing temperature can be in the range of 25°C to about 800°C, and the annealing pressure can be in the range of about 0.01 atm to about 25 atm. In embodiments performing a single annealing process, the dielectric layer 30 may comprise a nitrogen-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide nitride, silicon carbonitride, or the like.

[0086] The dual annealing process may include a wet annealing treatment followed by a dry annealing treatment. During the wet annealing treatment of the dual annealing process, the deposited film may be annealed in an environment of water vapor, hydrogen peroxide vapor, oxygen, free radicals generated by water, hydrogen peroxide, and oxygen, or combinations thereof. Nitrogen may also be used as a carrier gas. The weight percentage of water vapor in the wet annealing environment may range from about 5% to about 100%. The annealing temperature may range from about 25°C to about 800°C, and the annealing pressure may range from about 0.01 atm to about 25 atm. During the dry annealing treatment of the dual annealing process, the deposited film may be annealed in an environment of oxygen, nitrogen, or the like for about 1 minute to about 48 hours. The annealing temperature may range from about 25°C to about 800°C, and the annealing pressure may range from about 0.01 atm to about 25 atm. In embodiments performing the dual annealing process, the dielectric layer 30 may comprise an oxygen-containing dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like.

[0087] In some embodiments, during the deposition step, the dielectric material of the dielectric layer 30 may also be formed on other surfaces in the source / drain recess 46, such as the sidewalls of the upper semiconductor nanostructure 26U, the dummy nanostructure 24A in contact with the upper semiconductor nanostructure 26U, and the gate spacer 44. In such embodiments, an etching step may be performed after an annealing step to remove the dielectric material of the dielectric layer 30 from these surfaces. The etching step may include an isotropic etching process or the like.

[0088] exist Figure 5 In this process, the dummy nanostructure 24A in contact with the upper semiconductor nanostructure 26U is removed, while the dummy nanostructure 24A in contact with the lower semiconductor nanostructure 26L remains intact, which can be attributed to the protection provided by the dielectric layer 30. The dummy nanostructure 24A in contact with the upper semiconductor nanostructure 26U can be removed by a suitable etching process, such as an isotropic etching process. The etching process can selectively remove the material of the dummy nanostructure 24A without significantly removing the material of the upper semiconductor nanostructure 26U or the dielectric layer 30. In some embodiments, the upper semiconductor nanostructure 26U may be lightly etched such that the spacing between the upper semiconductor nanostructures 26U is greater than the spacing between the lower semiconductor nanostructures 26L. In embodiments where the dummy nanostructure 24A comprises silicon germanium and the upper semiconductor nanostructure 26U comprises silicon, the etching process may be a dry etching process, and an etchant such as tetramethylammonium hydroxide, ammonium hydroxide, or the like may be used.

[0089] exist Figure 6 In this process, dielectric layer 30 is removed to expose the sidewalls of the lower semiconductor nanostructure 26L and the sidewalls of the dummy nanostructure 24A in contact with the lower semiconductor nanostructure 26L. Dielectric layer 30 can be removed by a suitable etching process. The etching process can selectively remove material from dielectric layer 30 without significantly removing material from the upper semiconductor nanostructure 26L, lower semiconductor nanostructure 26L, dummy nanostructure 24A, dummy nanostructure 24B, or semiconductor fin 20'. In some embodiments, the etching process is a wet etching process using one or more etchants (such as hydrofluoric acid and / or the like). In some embodiments, the etching process is a dry etching process using one or more etchants (such as hydrofluoric acid, ammonia, and / or the like).

[0090] exist Figure 7In this process, a sacrificial layer 32 may be formed in the source / drain recess 46 to occupy the space previously occupied by the dummy nanostructure 24A before it is removed. The sacrificial layer 32 may be in contact with the upper semiconductor nanostructure 26U and may also cover the sidewalls of other features in the source / drain recess 46. The sacrificial layer 32 may be deposited using a suitable deposition process, such as CVD, ALD, or similar. The sacrificial layer 32 may contain an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or similar. The sacrificial layer 32 may contain a different material than the dummy nanostructure 24A, which is in contact with the lower semiconductor nanostructure 26L. Therefore, the stress (and corresponding strain) induced by the sacrificial layer 32 in the upper semiconductor nanostructure 26U may differ from the stress (and corresponding strain) induced by the dummy nanostructure 24A in the lower semiconductor nanostructure 26L. Since the upper semiconductor nanostructure 26U can serve as the channel region of the upper nanostructure FET of the stacked transistor, and the lower semiconductor nanostructure 26L can serve as the channel region of the lower nanostructure FET of the stacked transistor, different stresses (and corresponding strains) in the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L can improve the overall performance of the stacked transistor.

[0091] In an embodiment where the stacked transistor is a CFET, it includes an upper nanostructure FET as a p-type device and a lower nanostructure FET as an n-type device. The sacrificial layer 32 can induce compressive stress and strain in the upper semiconductor nanostructure 26U, and the dummy nanostructure 24A can induce tensile stress and strain in the lower semiconductor nanostructure 26L. In another embodiment where the stacked transistor is a CFET, it includes an upper nanostructure FET as an n-type device and a lower nanostructure FET as a p-type device. The sacrificial layer 32 can induce tensile stress and strain in the upper semiconductor nanostructure 26U, and the dummy nanostructure 24A can induce compressive stress and strain in the lower semiconductor nanostructure 26L.

[0092] exist Figure 8 In this process, the sacrificial layer 32 is partially removed, after which the sidewalls of the sacrificial layer 32 are recessed from the sidewalls of the upper semiconductor nanostructure 26U. Alternatively, portions of the sidewalls of the sacrificial layer 32 covering other features in the source / drain recess 46 may be removed. After partial removal of the sacrificial layer 32, the sidewalls of the sacrificial layer 32 may be recessed. The sacrificial layer 32 can be partially removed by a suitable etching process. The etching process can selectively remove material from the sacrificial layer 32 without significantly removing material from the upper semiconductor nanostructure 26U, the lower semiconductor nanostructure 26L, the dummy nanostructure 24A, the dummy nanostructure 24B, or the semiconductor fin 20'. The etching process can be a dry etching process using one or more etchants (such as hydrofluoric acid, ammonia, and / or the like).

[0093] exist Figure 9In this process, dummy nanostructure 24A, which is in contact with the lower semiconductor nanostructure 26L, is partially removed and dummy nanostructure 24B is completely removed, after which the sidewall of dummy nanostructure 24A is recessed from the sidewall of the lower semiconductor nanostructure 26L. In some embodiments, after the partial removal of dummy nanostructure 24A, the sidewall of dummy nanostructure 24A is substantially straight. In some embodiments, after the partial removal of dummy nanostructure 24A, the sidewall of dummy nanostructure 24A is curved. Dummy nanostructures 24A and dummy nanostructure 24B can be removed by a suitable etching process. The etching process can selectively remove material from dummy nanostructures 24A and dummy nanostructure 24B without significantly removing material from the upper semiconductor nanostructure 26L, the lower semiconductor nanostructure 26L, or the semiconductor fin 20'. The etching process can remove dummy nanostructure 24A at a slower rate than dummy nanostructure 24B. In embodiments where dummy nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, dummy nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process may be a dry etching process using one or more etchants (such as chlorine and / or the like). Because the dummy gate stack 42 surrounds the sidewalls of semiconductor nanostructure 26 (see...), Figure 2 Therefore, the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, so that the upper semiconductor nanostructure 26U will not collapse when the dummy nanostructure 24B is completely removed.

[0094] exist Figure 10 In this process, internal spacers 54 and dielectric isolation layer 56 are formed. The internal spacers 54 may include an upper internal spacer 54U formed on the sidewall of the sacrificial layer 32 and a lower internal spacer 54L formed on the sidewall of the dummy nanostructure 24A. The upper internal spacer 54U may have a protruding inner sidewall that contacts the recessed sidewall of the sacrificial layer 32. The inner sidewall of the upper internal spacer 54U may have a first curvature. The upper internal spacer 54U may have an outer sidewall having a first width W1. In subsequent processes, the outer sidewall of the upper internal spacer 54U may be covered by epitaxial source / drain regions. The lower internal spacer 54L may have a substantially straight inner sidewall that contacts a substantially straight sidewall of the dummy nanostructure 24A, or a curved inner sidewall that contacts a curved sidewall of the dummy nanostructure 24A. The inner wall of the lower internal spacer 54L may have a second curvature smaller than the first curvature of the inner wall of the upper internal spacer 54U. The lower internal spacer 54L may have an outer wall with a second width W2 smaller than the first width W1. In subsequent processes, the outer wall of the lower internal spacer 54L may be covered by epitaxial source / drain regions.

[0095] A dielectric isolation layer 56 may be formed in the space occupied by the dummy nanostructure 24B before it is removed. As described in more detail later, source / drain regions may subsequently be formed in the source / drain recess 46, and the dummy nanostructure 24A may be replaced with a corresponding gate structure. Internal spacers 54 may be used to isolate the subsequently formed source / drain regions from the subsequently formed gate structure. The dielectric isolation layer 56 may be used to isolate the upper semiconductor nanostructure 26U from the lower semiconductor nanostructure 26L.

[0096] The internal spacers 54 and dielectric isolation layer 56 can be formed by conformally depositing a suitable dielectric material in the source / drain recess 46, on the sidewalls of the sacrificial layer 32 and the dummy nanostructure 24A, and between the bottom upper semiconductor nanostructure 26U and the top lower semiconductor nanostructure 26L. The dielectric material can then be etched to remove excess portions. The dielectric material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbide, silicon carbide, silicon carbide, or the like. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can be used. The dielectric material can be formed by a suitable deposition process, such as ALD, CVD, or the like. The etching of the dielectric material can be anisotropic or isotropic etching.

[0097] exist Figure 11 In the process, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain groove 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. The upper epitaxial source / drain region 62U is in contact with the upper semiconductor nanostructure 26U, but not with the lower semiconductor nanostructure 26L. The lower epitaxial source / drain region 62L is in contact with the lower internal spacers 54L, which electrically insulate the lower epitaxial source / drain region 62L from the dummy nanostructure 24A. The upper epitaxial source / drain region 62U is in contact with the upper internal spacer 54U, which electrically insulates the upper epitaxial source / drain region 62U from the sacrificial layer 32. In subsequent processes, the dummy nanostructure 24A will be replaced by the gate.

[0098] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the individual materials may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, or the like. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the individual materials may include silicon or silicon-germanium doped with p-type dopants such as boron, indium, or the like. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not have the corresponding p-type or n-type dopants implanted. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be shielded to prevent undesired epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0099] As a result of the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has facets that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0100] A first contact etch stop layer (CESL) 66 and a first inter-layer dielectric (ILD) 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 may be formed from a dielectric material with high etch selectivity for etching the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. The first CESL 66 may be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 may be formed from a dielectric material that may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Applicable dielectric materials for the first ILD 68 may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

[0101] The formation process may include depositing a conformal CESL layer, depositing material for the first ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the unetched first CESL 66. An anisotropic etching process is then performed to remove the portion of the first CESL 66 that is higher than the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0102] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. Depending on the selected conductivity type of the upper epitaxial source / drain region 62U, the material of the upper epitaxial source / drain region 62U may be selected from the same candidate group of materials used to form the lower epitaxial source / drain region 62L. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U may be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U may be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the conductivity types of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L may be the same. The upper epitaxial source / drain region 62U can be doped in situ and / or implanted with n-type or p-type dopants. Adjacent upper epitaxial source / drain regions 62U can remain separate after the epitaxial process or can be merged.

[0103] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods may be similar to those of the first CESL 66 and the first ILD 68, and are not discussed in detail herein. The formation process may include depositing layers for the second CESL 70 and the second ILD 72, and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask layer 40 (if present) or the dummy gate layer 38 are substantially coplanar (within process variations). Therefore, the top surface of the mask layer 40 (if present) or the dummy gate layer 38 is exposed via the second ILD 72. In the illustrated embodiment, the mask layer 40 is retained after the removal process. In other embodiments, the mask layer 40 is removed such that the top surface of the dummy gate layer 38 is exposed via the second ILD 72.

[0104] Figure 12The diagram illustrates a gate replacement process in which a dummy gate stack 42 and a dummy nanostructure 24A are replaced with a gate structure 90. The gate replacement process includes first removing the dummy gate stack 42, the sacrificial layer 32, and the remaining portions of the dummy nanostructure 24A. The dummy gate stack 42 is removed using one or more suitable etching processes. Then, the remaining portions of the sacrificial layer 32 and the dummy nanostructure 24A are removed using an additional suitable etching process. The remaining portions of the sacrificial layer 32 are removed using a dry etching process with one or more etchants (such as hydrofluoric acid, ammonia, and / or the like). The remaining portions of the dummy nanostructure 24A can be removed using a wet etching process with one or more etchants (such as tetramethylammonium hydroxide, ammonium hydroxide, and / or the like). The semiconductor nanostructure 26 remains intact during the etching process. After removing the sacrificial layer 32 and the dummy nanostructure 24A, the stress-induced strain of the sacrificial layer 32 in the upper semiconductor nanostructure 26U and the stress-induced strain of the dummy nanostructure 24A in the lower semiconductor nanostructure 26L, as described above, are retained in the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L. Therefore, the overall performance of the stacked transistor can be improved.

[0105] Then, gate dielectric 78 is deposited in the trenches between gate spacers 44 and on the exposed semiconductor nanostructure 26. Gate dielectric 78 is conformally formed on the exposed surface of the trenches (removed dummy gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructure 26 and gate spacers 44. In some embodiments, gate dielectric 78 surrounds all (e.g., four) sides of semiconductor nanostructure 26. Specifically, gate dielectric 78 may be formed on the top surface of semiconductor fin 20'; the top surface, sidewalls, and bottom surface of semiconductor nanostructure 26; and the sidewalls of internal spacers 54. Gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicides such as metal silicides, combinations thereof, multilayers thereof, or the like. Gate dielectric 78 may include high dielectric constant (high k) materials having a k value greater than about 7.0, such as metal oxides or silicides of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular-beam deposition (MBD), ALD, PECVD, and the like, followed by a planarization process (e.g., CMP) to remove a portion of the gate dielectric 78 above the second ILD 72. Although a single-layer gate dielectric 78 is illustrated, the gate dielectric 78 may include multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0106] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L surrounds the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multiple layers thereof, or the like. Although a single-layer lower gate electrode 80L is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0107] The lower gate electrode 80L is formed of one or more materials suitable for a device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of one or more materials suitable for a device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of aluminum titanium, aluminum titanium carbide, aluminum tantalum, tantalum carbide, combinations thereof, or the like. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, or the like. Alternatively or additionally, the lower gate electrode 80L may include a dipole-inducing element suitable for a device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0108] The lower gate electrode 80L can be formed by conformally depositing one or more gate electrode layers to create a recess. An acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be performed to create the recess. The etching can be isotropic. Etching the lower gate electrode 80L exposes the upper semiconductor nanostructure 26U.

[0109] In some embodiments, an isolation layer (not explicitly shown) may be formed on the lower gate electrode 80L. The isolation layer serves as an isolation feature between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0110] Then, an upper gate electrode 80U is formed on the isolation layer (if present) described above or on the lower gate electrode 80L. The upper gate electrode 80U is deposited between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U surrounds the upper semiconductor nanostructure 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from one or more materials suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed from one or more materials suitable for the device type of the upper nanostructure FET. Although a single-layer upper gate electrode 80U is illustrated, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler layers.

[0111] Additionally, a removal process is performed to planarize the top surfaces of the upper gate electrode 80U and the second ILD 72. The removal process for forming the gate dielectric 78 may be the same etching process used to form the upper gate electrode 80U. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, or similar methods may be used. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each individual pair of gate dielectric 78 and gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) may be collectively referred to as the “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L). The upper gate structure 90U may have recessed sidewalls that contact the protruding inner sidewalls of the upper internal spacer 54U. The sidewalls of the upper gate structure 90U may have a third curvature. The lower gate structure 90L may have a substantially straight sidewall that contacts the substantially straight inner sidewall of the lower internal spacer 54L, or a curved sidewall that contacts the curved inner sidewall of the lower internal spacer 54L. The sidewall of the lower gate structure 90L may have a fourth curvature smaller than the third curvature of the sidewall of the upper gate structure 90U. Each gate structure 90 extends along three sides (e.g., top surface, sidewall, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see [reference]). Figure 1 The lower gate structure 90L may also extend along the sidewalls and / or top surface of the semiconductor fin 20'.

[0112] like Figure 12As shown, a gate mask 92 is formed over the gate structure 90. The formation process may include recessing the gate structure 90, filling the resulting groove with a dielectric material such as silicon nitride, silicon carbide nitride, silicon oxynitride, silicon carbide nitride, or the like, and performing a planarization process to remove excess dielectric material over the second ILD 72.

[0113] exist Figure 13 In the second ILD 72, a metal-semiconductor alloy region 94 and source / drain contacts 96 are formed through the second ILD 72 to be electrically coupled to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. As an example of forming the source / drain contacts 96, an opening through the second ILD 72 and the second CESL 70 is formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, or the like. A removal process may be performed to remove excess material from the gate spacer 44 and the top surface of the second ILD 72. The remaining liner and conductive material form the source / drain contacts 96 in the opening. In some embodiments, a planarization process such as CMP, etch-back process, a combination thereof, or the like is utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within process variations).

[0114] Depending on the application, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 may be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanium region formed from both metal silicides and metal germanides, or similar. The metal-semiconductor alloy region 94 can be formed before one or more materials of the source / drain contact 96 by depositing metal in the opening of the source / drain contact 96 and then performing a thermal annealing process. The metal may be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, PVD, or similar methods. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from openings in the source / drain contacts 96 (such as from the surface of the metal-semiconductor alloy region 94). One or more materials can then be formed on the metal-semiconductor alloy region 94 to create the source / drain contacts 96.

[0115] Then, ESL 104 and third ILD 106 are formed. In some embodiments, ESL 104 may include a dielectric material with high etch selectivity for etching the third ILD 106, such as alumina, aluminum nitride, silicon carbide, or the like. The third ILD 106 may be formed using flowable CVD, ALD, or the like, and the material may include PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like.

[0116] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 108 and the source / drain via 110, openings for the gate contact 108 and the source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, or the like. A planarization process such as CMP can be performed to remove excess material from the top surface of the third ILD 106. The remaining lining and conductive material form the gate contact 108 and the source / drain via 110 in the opening. The gate contact 108 and the source / drain via 110 may be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 108 and the source / drain via 110 may be formed in different cross-sections to avoid short circuits in the contacts.

[0117] A front interconnect structure 114 is formed on device layer 112. The front interconnect structure 114 includes a dielectric layer 116 and a layer of conductive features 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may further include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicon glass (USG), silicon oxide, silicon nitride, or similar materials, or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0118] Conductive feature 118 may include conductive lines and vias formed using an damascene process. Conductive feature 118 may include metal lines and metal vias, which include a diffusion barrier layer and a copper-containing material located above the diffusion barrier layer. An aluminum pad may also be present above and electrically connected to the metal lines and vias. In some embodiments, the lower gate structure 90L and the lower epitaxial source / drain region 62L may be contacted via the back side of device layer 112 (e.g., the side opposite to the front interconnect structure 114).

[0119] The embodiments disclosed herein have several advantageous features. By forming a sacrificial layer 32 on the upper semiconductor nanostructure 26U and a dummy nanostructure 24A on the lower semiconductor nanostructure 26L, different stresses (and corresponding strains) can be induced in the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L. Therefore, the overall performance of the stacked transistor including the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L can be improved.

[0120] In one embodiment, a semiconductor device includes: a first nanostructure; a first gate structure surrounding the first nanostructure; a first internal spacer located on the first nanostructure and the first gate structure; a first source / drain region located on the first nanostructure and the first internal spacer, wherein the first internal spacer has a first outer sidewall having a first width; a second nanostructure located below the first nanostructure; a second gate structure surrounding the second nanostructure; a second internal spacer located on the second nanostructure and the second gate structure; and a second source / drain region located on the second nanostructure and the second internal spacer, wherein the second internal spacer has a second outer sidewall having a second width less than the first width. In one embodiment, the first source / drain region includes a first dopant of a first conductivity type, and the second source / drain region includes a second dopant of a second conductivity type different from the first conductivity type. In one embodiment, the first source / drain region is separated from the second source / drain region by a dielectric layer. In one embodiment, the semiconductor further includes an isolation layer located between the first nanostructure and the second nanostructure. In one embodiment, the first internal spacer, the second internal spacer, and the isolation layer include the same dielectric material. In one embodiment, the first nanostructure and the second nanostructure comprise the same semiconductor material. In one embodiment, the first internal spacer has a first inner sidewall having a first curvature, wherein the second internal spacer has a second inner sidewall having a second curvature less than the first curvature.

[0121] In one embodiment, a method of forming a semiconductor device includes: forming a first semiconductor nanostructure and a first dummy nanostructure located on the first semiconductor nanostructure; forming a second semiconductor nanostructure below the first semiconductor nanostructure and forming a second dummy nanostructure on the second semiconductor nanostructure; forming a first dielectric layer, wherein the sidewalls of the second dummy nanostructure are covered by the first dielectric layer, and the sidewalls of the first dummy nanostructure remain exposed after forming the first dielectric layer; removing the first dummy nanostructure to form a first opening, wherein the second dummy nanostructure remains intact after removing the first dummy nanostructure; removing the first dielectric layer to expose the sidewalls of the second dummy nanostructure; and forming a first sacrificial layer in the first opening. In one embodiment, the method includes: recessing the second dummy nanostructure by an etching process; and forming a first internal spacer on the first sacrificial layer and a second internal spacer on the second dummy nanostructure by a deposition process. In one embodiment, a first internal spacer has a first sidewall in contact with a first sacrificial layer, wherein the first sidewall has a first curvature, and a second internal spacer has a second sidewall in contact with a second dummy nanostructure, wherein the second sidewall has a second curvature less than the first curvature. In one embodiment, the method includes replacing the first sacrificial layer with a first gate structure and replacing the second dummy nanostructure with a second gate structure. In one embodiment, the first sacrificial layer and the second dummy nanostructure comprise different materials. In one embodiment, the method includes forming a first source / drain region on a first semiconductor nanostructure, wherein the first source / drain region comprises a first dopant of a first conductivity type; and forming a second source / drain region on a second semiconductor nanostructure, wherein the second source / drain region comprises a second dopant of a second conductivity type different from the first conductivity type. In one embodiment, forming a first dielectric layer includes performing a flowable chemical vapor deposition (FCVD) process, wherein the FCVD process includes a deposition step, a curing step, and an annealing step.

[0122] In one embodiment, a method of forming a semiconductor device includes: forming a nanostructure stack over a substrate, wherein the nanostructure stack includes a first semiconductor nanostructure, a first dummy nanostructure above the first semiconductor nanostructure, a second semiconductor nanostructure above the first dummy nanostructure, and a second dummy nanostructure above the second semiconductor nanostructure; replacing the second dummy nanostructure with a sacrificial layer, wherein the first dummy nanostructure remains intact after the replacement of the second dummy nanostructure; partially removing the first dummy nanostructure; forming a first internal spacer on the first dummy nanostructure and forming a second internal spacer on the sacrificial layer; and replacing the first dummy nanostructure with a first gate structure and replacing the sacrificial layer with a second gate structure. In one embodiment, the method includes: forming a first dielectric layer, wherein the sidewalls of the first dummy nanostructure are covered by the first dielectric layer, and the sidewalls of the second dummy nanostructure do not contain the first dielectric layer; and removing the first dielectric layer before replacing the second dummy nanostructure with the sacrificial layer. In one embodiment, the first dummy nanostructure induces tensile stress and strain in the first semiconductor nanostructure, and wherein the sacrificial layer induces compressive stress and strain in the second semiconductor nanostructure. In one embodiment, a first dummy nanostructure induces compressive stress and strain in a first semiconductor nanostructure, and a sacrificial layer induces tensile stress and strain in a second semiconductor nanostructure. In one embodiment, the method includes: forming a first source / drain region on a first semiconductor nanostructure and a first internal spacer, wherein the first source / drain region is doped with a first dopant; forming a second dielectric layer over the first source / drain region; and forming a second source / drain region on a second semiconductor nanostructure and a second internal spacer, wherein the second source / drain region is located over the second dielectric layer, wherein the second source / drain region is doped with a second dopant, and wherein the first and second dopants have opposite conductivity types. In one embodiment, the first internal spacer includes a first sidewall contacting the first source / drain region, wherein the first sidewall has a first width, and the second internal spacer includes a second sidewall contacting the second source / drain region, wherein the second sidewall has a second width greater than the first width.

[0123] In one embodiment, a semiconductor device includes: a first nanostructure; a first gate structure surrounding the first nanostructure; a first internal spacer located on the first nanostructure and the first gate structure; a first source / drain region located on the first nanostructure and the first internal spacer, wherein the first internal spacer has a first inner sidewall having a first curvature; a second nanostructure located below the first nanostructure; a second gate structure surrounding the second nanostructure; a second internal spacer located on the second nanostructure and the second gate structure; and a second source / drain region located on the second nanostructure and the second internal spacer, wherein the second internal spacer has a second inner sidewall having a second curvature less than the first curvature. In one embodiment, the semiconductor device further includes an isolation layer located between the first nanostructure and the second nanostructure. In one embodiment, the first internal spacer, the second internal spacer, and the isolation layer include the same dielectric layer. In one embodiment, the first nanostructure and the second nanostructure include the same semiconductor layer.

[0124] In one embodiment, a semiconductor device includes: a first nanostructure; a first gate structure surrounding the first nanostructure; a first internal spacer located on the first nanostructure and the first gate structure; a first source / drain region located on the first nanostructure and the first internal spacer, wherein the first source / drain region is doped with a first dopant; a second nanostructure located below the first nanostructure; a second gate structure surrounding the second nanostructure; a second internal spacer located on the second nanostructure and the second gate structure; and a second source / drain region located on the second nanostructure and the second internal spacer, wherein the second source / drain region is doped with a second dopant, and wherein the first dopant and the second dopant have opposite conductivity types. In one embodiment, the first internal spacer includes a first sidewall contacting the first source / drain region, wherein the first sidewall has a first width, and the second internal spacer includes a second sidewall contacting the second source / drain region, wherein the second sidewall has a second width greater than the first width.

[0125] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: The first nanostructure; A first gate structure, surrounding the first nanostructure; A first internal spacer is located on the first nanostructure and the first gate structure; A first source / drain region is located on the first nanostructure and the first internal spacer, wherein the first internal spacer has a first outer wall having a first width; A second nanostructure is located below the first nanostructure; A second gate structure surrounds the second nanostructure; A second internal spacer is located on the second nanostructure and the second gate structure; and A second source / drain region is located on the second nanostructure and the second internal spacer, wherein the second internal spacer has a second outer wall having a second width smaller than the first width.

2. The semiconductor device as claimed in claim 1, characterized in that, The first source / drain region contains a first dopant of a first conductivity type, and the second source / drain region contains a second dopant of a second conductivity type different from the first conductivity type.

3. The semiconductor device as claimed in claim 2, characterized in that, The first source / drain region is separated from the second source / drain region by a dielectric layer.

4. The semiconductor device as claimed in claim 1, characterized in that, The first internal spacer has a first inner sidewall with a first curvature, and the second internal spacer has a second inner sidewall with a second curvature that is less than the first curvature.

5. A semiconductor device, characterized in that, Include: The first nanostructure; A first gate structure, surrounding the first nanostructure; A first internal spacer is located on the first nanostructure and the first gate structure; A first source / drain region is located on the first nanostructure and the first internal spacer, wherein the first internal spacer has a first inner sidewall having a first curvature; A second nanostructure is located below the first nanostructure; A second gate structure surrounds the second nanostructure; A second internal spacer is located on the second nanostructure and the second gate structure; and A second source / drain region is located on the second nanostructure and the second internal spacer, wherein the second internal spacer has a second inner sidewall having a second curvature that is smaller than the first curvature.

6. The semiconductor device of claim 5, further comprising an isolation layer located between the first nanostructure and the second nanostructure.

7. The semiconductor device of claim 6, wherein the first internal spacer, the second internal spacer, and the isolation layer comprise the same dielectric layer.

8. The semiconductor device of claim 5, wherein the first nanostructure and the second nanostructure comprise the same semiconductor layer.

9. A semiconductor device, characterized in that, Include: The first nanostructure; A first gate structure, surrounding the first nanostructure; A first internal spacer is located on the first nanostructure and the first gate structure; A first source / drain region is located on the first nanostructure and the first internal spacer, wherein the first source / drain region is doped with a first dopant; A second nanostructure is located below the first nanostructure; A second gate structure surrounds the second nanostructure; A second internal spacer is located on the second nanostructure and the second gate structure; as well as A second source / drain region is located on the second nanostructure and the second internal spacer, wherein the second source / drain region is doped with a second dopant, and wherein the first dopant and the second dopant have opposite conductivity types.

10. The semiconductor device of claim 9, wherein the first internal spacer includes a first sidewall in contact with the first source / drain region, wherein the first sidewall has a first width, and wherein the second internal spacer includes a second sidewall in contact with the second source / drain region, wherein the second sidewall has a second width greater than the first width.

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