Semiconductor device

Abstract

Embodiments of the present disclosure provide semiconductor devices. One exemplary semiconductor device of the present disclosure includes a first channel region disposed above a semiconductor substrate, a gate structure disposed above the first channel region, a first source / drain region disposed at a first side of the first channel region, a second source / drain region disposed at a second side of the first channel region, an interlayer dielectric layer disposed above the first channel region, the first source / drain region, and the second source / drain region, a first contact disposed in the interlayer dielectric layer and electrically coupled to the first source / drain region, and a second contact disposed in the semiconductor substrate and electrically coupled to the second source / drain region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) has typically increased, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) has decreased. This scaling down process provides benefits by increasing production efficiency and reducing associated costs. Such scaling down has also increased the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in the processing and manufacturing of ICs. Utility Model Content

[0004] Some embodiments disclosed herein provide a semiconductor device including a first channel region, a gate structure, a first source / drain region, a second source / drain region, an interlayer dielectric layer, a first contact, and a second contact. The first channel region is disposed above a semiconductor substrate, and the gate structure is disposed above the first channel region. The first source / drain region is disposed on a first side of the first channel region, and the second source / drain region is disposed on a second side of the first channel region. The interlayer dielectric layer is disposed above the first channel region, the first source / drain region, and the second source / drain region. The first contact is disposed in the interlayer dielectric layer and electrically coupled to the first source / drain region, and the second contact is disposed in the semiconductor substrate and electrically coupled to the second source / drain region.

[0005] Some embodiments disclosed herein provide a semiconductor device including a semiconductor substrate, a first channel region, a second channel region, a first contact, a first interconnect structure, a second contact, and a second interconnect structure. The semiconductor substrate has a front side and a back side opposite to the front side. The first channel region and the second channel region are disposed above the front side of the semiconductor substrate, wherein the first channel region and the second channel region have the same length and are disposed between a first epitaxial region and a second epitaxial region. The first contact is disposed above the front side of the semiconductor substrate and laterally aligned with the first epitaxial region. The first interconnect structure is disposed above the front side of the semiconductor substrate and electrically coupled to the first epitaxial region via the first contact. The second contact is disposed in the semiconductor substrate and laterally aligned with the second epitaxial region. The second interconnect structure is disposed above the back side of the semiconductor substrate and electrically coupled to the second epitaxial region via the second contact.

[0006] Some embodiments disclosed herein provide a semiconductor forming apparatus, comprising a semiconductor substrate, a first channel region, a second channel region, a first dielectric filler, a first contact, a first interconnect structure, a second contact, and a second interconnect structure. The semiconductor substrate has a front side and a back side opposite to the front side. The first channel region and the second channel region are disposed above the front side of the semiconductor substrate, wherein the first channel region and the second channel region have the same length and are disposed between a first epitaxial region and a second epitaxial region. The first dielectric filler separates the first epitaxial region from the semiconductor substrate. The first contact is disposed above the front side of the semiconductor substrate and laterally aligned with the first epitaxial region. The first interconnect structure is disposed above the front side of the semiconductor substrate and electrically coupled to the first epitaxial region via the first contact. The second contact is disposed in the semiconductor substrate and laterally aligned with the second epitaxial region. The second interconnect structure is disposed above the back side of the semiconductor substrate and electrically coupled to the second epitaxial region via the second contact. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the detailed description below. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1 to 6 This is a perspective view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments;

[0009] Figures 7A to 23B This is a cross-sectional side view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments;

[0010] Figure 24 The diagram illustrates the device on / off switching system of the semiconductor device and general semiconductor device disclosed herein;

[0011] Figures 25A to 25B This is a cross-sectional side view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments;

[0012] Figure 26A and Figure 26B This is a cross-sectional view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments;

[0013] Figure 27A and Figure 27B This is a cross-sectional view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments;

[0014] Figure 28A and Figure 28B This is a cross-sectional view of an intermediate stage in the manufacture of a semiconductor device according to some embodiments.

[0015] [Symbol Explanation]

[0016] 10: Transistor Structure

[0017] 100A: Transistor Structure

[0018] 100: Semiconductor devices

[0019] 101B: Dorsal side

[0020] 101F: Front

[0021] 101:Substrate

[0022] 102: Multi-layer stacking

[0023] 104: First semiconductor layer / First semiconductor

[0024] 106: Second semiconductor layer

[0025] 108: Semiconductor Strip

[0026] 110A: First Nanostructure

[0027] 110: First Nanostructure

[0028] 112: Second Nanostructure

[0029] 114: Fins

[0030] 116: Trench

[0031] 118: Insulating materials

[0032] 120: Isolation Zone

[0033] 130: Dummy gate structure

[0034] 132: Dummy gate dielectric

[0035] 134: Dummy Gate Electrode

[0036] 136: Hard Mask

[0037] 138: Gate spacer

[0038] 140A: Upper part

[0039] 140B: Lower part

[0040] 140: First Opening

[0041] 142: Second opening

[0042] 144: Insulation layer

[0043] 150: Internal spacer / bottom spacer

[0044] 154: Dielectric layer / dielectric filler

[0045] 158: Source / Drain Region

[0046] 158A, 158B, 158C, 158D: Source / Drain Regions

[0047] 160: Contact Etching Termination Layer (CESL)

[0048] 162: First dielectric (ILD) layer

[0049] 164: Third opening

[0050] 168: Gate dielectric layer

[0051] 170: Gate electrode / electrode

[0052] 172: Gate Structure

[0053] 174: Second dielectric (ILD) layer

[0054] 176: Contact Etching Termination Layer (CESL)

[0055] 178: Contacts

[0056] 180: Contact

[0057] 182: Silicide Region

[0058] 183: Front-side interconnect structure

[0059] 184: Electrical conductivity characteristics

[0060] 186: Dielectric layer

[0061] 188: Carrier substrate

[0062] 190: Bonding layer

[0063] 191: Opening

[0064] 192: Back side contact / contact

[0065] 194: Silicide Region

[0066] 195: Backside interconnect structure

[0067] 196: Electrical conductivity characteristics

[0068] 198: Dielectric layer

[0069] 200: Semiconductor devices

[0070] 279: Dummy Contact / Contact

[0071] 281: Silicide Region

[0072] 300: Semiconductor Devices

[0073] 378: Contact

[0074] 392: Back side contact / contact

[0075] 394: Silicide Region

[0076] 400: Semiconductor Device

[0077] 455: Semiconductor filler

[0078] AA: Cross section

[0079] BB: Cross-section

[0080] I DS Drain-to-source current

[0081] L: Fixed length

[0082] P1: Current path

[0083] P2: Current path Detailed Implementation

[0084] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0085] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “top,” “upper,” and the like are used herein for ease of description to describe the relationship between one or more elements or features as depicted in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are similarly interpreted accordingly.

[0086] Embodiments of this disclosure provide a transistor structure including a plurality of nanostructure channels disposed between source and drain regions, and these nanostructure channels having the same length. In some embodiments, the transistor structure also includes a front-side contact electrically coupled to the front side of one of the source / drain regions and a back-side contact electrically coupled to the back side of the other source / drain regions. Therefore, the transmission distance between the contacts will be the same regardless of which nanostructure channel the current is transmitted through. The transistor structure of this disclosure can therefore have rapid turn-on and turn-off transitions.

[0087] While the embodiments disclosed herein relate to nanostructured channel FETs, such as horizontal gate all around (HGAA) FETs or vertical gate all around (VGAA) FETs, implementations of some of the forms disclosed herein can be used in other processes and / or other devices, such as planar FETs, FinFETs, and other suitable devices. Those skilled in the art will readily understand that other modifications are contemplated within the scope of this disclosure. In cases where a gate all around (GAA) transistor structure is employed, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes, thereby allowing patterns to be generated with a spacing, for example, smaller than that obtained using a single direct optical lithography process in other ways. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. The spacers are formed along a patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0088] Figures 1 to 23B and Figures 25A to 25B An exemplary process for manufacturing a semiconductor device 100 according to an embodiment of the present disclosure is illustrated. It should be understood that for additional embodiments of the method, additional operations may be performed by… Figures 1 to 23B and Figures 25A to 25B The illustrations provide information before, during, and after the processes, and some of the operations described below may be substituted or eliminated. The order of operations / processes is not restrictive and may be interchangeable.

[0089] Figures 1 to 6 This is a perspective view of an intermediate stage in the manufacture of a semiconductor device 100 according to some embodiments. Figure 1As illustrated, the semiconductor device 100 includes a substrate 101 having a front side 101F and a back side 101B opposite to the front side 101F. The semiconductor device 100 also includes a multilayer stack 102 formed over the front side 101F of the substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one embodiment, the insulating layer is an oxygen-containing layer.

[0090] The substrate 101 may include various regions in its front side 101F that are doped with impurities (e.g., dopants with p-type or n-type conductivity). Depending on the circuit design, the substrate 101 may include p-type doped wells for n-type field-effect transistors (NFETs) and n-type doped wells for p-type field-effect transistors (PFETs).

[0091] The multilayer stack 102 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured FETs. In some embodiments, the multilayer stack 102 includes a first semiconductor layer 104 and a second semiconductor layer 106 alternately stacked over the front side 101F of the substrate 101. For example, the multilayer stack 102 is illustrated for illustrative purposes as including three layers of first semiconductor layer 104 and three layers of second semiconductor layer 106. It should be understood that any number of first semiconductor layers 104 and second semiconductor layers 106 may be included in the multilayer stack 102. In some embodiments, the first semiconductor layer 104 is formed of a first semiconductor material, and the second semiconductor layer 106 is formed of a second semiconductor material different from the first semiconductor material. The second semiconductor material may have different etch selectivity and / or oxidation rate compared to the first semiconductor material. In some embodiments, the first semiconductor material or the second semiconductor material is or includes materials such as SiGe, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, combinations thereof, or similar. In some embodiments, the first semiconductor material is formed of Si and the second semiconductor material is formed of SiGe, or vice versa.

[0092] Each first semiconductor layer 104 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 106 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 104. In some embodiments, each second semiconductor layer 106 has a thickness ranging from about 2 nm to about 50 nm. The first semiconductor layer 104 and the second semiconductor layer 106 are formed by any suitable deposition process, such as epitaxial deposition. By way of example, the epitaxial deposition of the multilayer stack 102 may be performed by: vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and similar and / or other suitable epitaxial growth processes.

[0093] exist Figure 2In some embodiments, the multilayer stack 102 and the substrate 101 are patterned by one or more etching processes. Each semiconductor strip 108 may include a first nanostructure 110 patterned from a first semiconductor layer 104 and a second nanostructure 112 patterned from a second semiconductor layer 106. The substrate 101 may include a plurality of fins 114 after the etching process. The semiconductor strips 108 are respectively disposed above the fins 114. The term nanostructure is used herein to refer to any portion of material having a nanoscale or even micrometer scale size and having an elongated shape without regard to the cross-sectional shape of such portion. Thus, this term refers to both elongated material portions with circular and substantially circular cross-sections and rod or bar-shaped material portions, for example, having a cylindrical or substantially rectangular cross-section.

[0094] Semiconductor strip 108 can be formed by patterning a hard mask layer (not shown) formed on a multilayer stack 102 using multiple patterning operations, including lithography and etching processes. The etching process may include wet etching, such as reactive ion etching (RIE) or neutral beam etching (NBE), wet etching, and / or other suitable processes. The lithography process may include: forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element may be performed using an electron beam (e-beam) lithography process. The etching process passes through the hard mask layer, through the multilayer stack 102, and into the substrate 101 to form a trench 116 in an unprotected area, thereby leaving the semiconductor strip 108 and fins 114. The trench 116 extends along the X direction. In some embodiments, the semiconductor strip 108 and fin 114 have a longitudinal axis along the X direction.

[0095] Semiconductor device 100 may include multiple transistor structures. A first nanostructure 110 or a portion thereof may form a nanostructure channel of the transistor structure in a later manufacturing stage, while a second nanostructure 112 may act as a sacrificial layer in a later manufacturing stage, thereby allowing the nanostructure channel to be surrounded by a gate structure. The transistor structure having the nanostructure channel may be referred to as a nanostructure transistor, nanosheet transistor, nanowire transistor, gate-all-around (GAA) transistor, multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel.

[0096] exist Figure 3In this process, after the semiconductor strips 108 are formed, an insulating material 118 is formed above the substrate 101. The insulating material 118 fills the trenches 116 between adjacent semiconductor strips 108 until the semiconductor strips 108 are embedded in the insulating material 118. Subsequently, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching-back methods, is performed to expose the top of the semiconductor strips 108. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluoride-doped silicate glass (FSG), a low-k dielectric material (k value less than about 3.5), or any suitable dielectric material. The insulating material 118 may be formed by any suitable method such as flowable CVD (FCVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced CVD (PECVD).

[0097] exist Figure 4 In this configuration, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of semiconductor strip 108 and substrate 101. The recess in insulating material 118 exposes trenches 116 between adjacent semiconductor strips 108. Isolation region 120 can be formed using suitable processes such as dry etching, wet etching, or combinations thereof. The top surface of isolation region 120 may be flush with or below the top surface of fin 114 and in contact with fin 114.

[0098] exist Figure 5 In this embodiment, one or more dummy gate structures 130 (only one is shown) are formed over the semiconductor device 100. The dummy gate structure 130 is formed over a portion of the semiconductor strip 108. Each dummy gate structure 130 may include a dummy gate dielectric 132, a dummy gate electrode 134, and a hard mask 136. The dummy gate dielectric 132, the dummy gate electrode 134, and the hard mask 136 can be formed by sequentially depositing blanket layers of the dummy gate dielectric 132, the dummy gate electrode 134, and the hard mask 136, and then patterning those layers into the dummy gate structure 130. The dummy gate structure 130 may have a direction substantially perpendicular to the longitudinal direction of the semiconductor strip 108 (e.g., Figure 5 The longitudinal direction of the X direction (e.g., the X direction in the equation). Figure 5 (in the Y direction). The dummy gate structure 130 can be landed on the isolation region 120 and cross one or more semiconductor strips 108.

[0099] The dummy gate dielectric 132 may include one or more layers of dielectric material, such as a deposited oxide material (e.g., silicon oxide) or a material oxidized from the substrate 101. The dummy gate electrode 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The hard mask 136 may include one or more dielectric layers. For example, the hard mask 136 may be a combination of oxide layers and nitride layers.

[0100] Gate spacers 138 are then formed on the sidewalls of the dummy gate structure 130. Gate spacers 138 can be formed by conformally depositing one or more layers of gate spacers 138 and anisotropically etching (e.g., RIE) one or more layers. Dielectric materials such as silicon nitride, silicon oxide, silicon carbide, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like can be used for gate spacers 138.

[0101] exist Figure 6 In some embodiments, a first opening 140 is formed in the semiconductor strip 108, fin 114, and substrate 101. The first opening 140 can be formed by removing at least a plurality of portions of the semiconductor strip 108 and substrate 101 that are not protected by the gate spacer 138 and the dummy gate structure 130. Therefore, the first opening 140 is as follows: Figure 6 The diagram shown is in the X direction (or in the diagram shown in the diagram). Figure 7A A cross-sectional view (as shown in the diagram) may be formed between adjacent dummy gate structures 130. A first opening 140 may be recessed below the top surface of the isolation region 120, although the first opening may also be recessed to be flush with or above the top surface of the isolation region 120. The first opening 140 may be formed by an etching process using isotropic or anisotropic etching processes, and the etching process may be selective relative to one or more crystal planes of the substrate 101. The etching process may be dry etching, such as RIE, NBE, or the like, or wet etching. The etchant from the etching process may include CH2F2, C2F6, and / or CF4 with or without HBr, Cl2, and / or O2 or the like.

[0102] Figure 7A and Figure 7B To respectively along Figure 6 Cross-sectional views of the semiconductor device 100 taken in multiple directions, with cross-sections AA and BB. According to some embodiments, multiple dummy gate structures 130, multiple semiconductor strips 108, and more detailed elements are illustrated in the cross-sectional views. Throughout the description, figures including the numeral "A" are obtained from [source missing]. Figure 6 The reference cross-section AA in the figure, including the figure number "B", is obtained from the figure. Figure 6 The reference cross section BB in the diagram.

[0103] exist Figure 7A and Figure 7B In this embodiment, a first opening 140 extends through the stack of first nanostructures 110 and second nanostructures 112 and into the substrate 101. In some embodiments, the first opening 140 has an extension depth, such as being at least about twice the height of the stack of first nanostructures 110 and second nanostructures 112. In some embodiments, the first opening 140 includes an upper portion 140A that extends at least through all first nanostructures 110 to expose all first nanostructures 110. In some embodiments, the upper portion 140A also extends below the bottom of the lowest second nanostructure 112. It should be understood that although dry etching is anisotropic etching and can produce substantially vertical sidewalls for the upper portion of the opening, the opening produced by dry etching can have a width that gradually narrows toward the bottom of the opening. In forming the extension depth for the first opening 140, the upper portion 140A of the first opening 140 can have a substantially vertical sidewall profile and allow each of the first nanostructures 110 between the first openings 140 to have a fixed length L. As will be discussed in detail below, because each of the first nanostructures 110 has substantially the same length, all current paths through each of the first nanostructures 110 will be substantially the same, and thus can provide a rapid turn-on and turn-off transition for the transistor structure. In some embodiments, each of the first openings 140 also includes a lower portion 140B below and connected to the upper portion 140A. The lower portion 140B of the first opening 140 may have a width that gradually narrows toward the bottom of the first opening 140, such as having a parabolic or triangular shape in a cross-sectional view. In some embodiments, the ratio of the height of the upper portion 140A to the height of the lower portion 140B is about 5 to about 15. The depth of extension of the first opening 140 can be achieved by increasing the etching time and / or increasing the plasma bias.

[0104] exist Figure 8A and Figure 8B In some embodiments, the second nanostructure 112 exposed by the first opening 140 is etched to form the second opening 142. That is, the second opening 142 may be the space occupied by the second nanostructure 112, including the space between adjacent first nanostructures 110 and between the bottommost first nanostructure 110 and the substrate 101. Although an etchant selective for etching the second semiconductor material 112 is used, the first nanostructures 110 and the substrate 101 remain relatively unetched. In embodiments where the second semiconductor material includes, for example, SiGe, an etching process is used that employs a hydroxide etchant such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or similar.

[0105] exist Figure 9A and Figure 9B In some embodiments, an insulating layer 144 is deposited in a first opening 140 and a second opening 142. In some embodiments, given the size difference between the first opening 140 and the second opening 142, the insulating layer 144 may substantially or completely fill the second opening 142 and form a conformal layer in the first opening 140. The insulating layer 144 may include an oxygen-containing material, such as silicon oxide, silicon oxynitride, silicon carbonitride, fluorosilicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. In some embodiments, the insulating layer 144 includes a material similar to those materials of the isolation region 120. The insulating layer 144 may be formed by any suitable deposition method, such as FCVD, ALD, PECVD, LPCVD, combinations thereof, or the like.

[0106] exist Figure 10A and Figure 10B In some embodiments, an etching process is performed to remove the insulating layer 144 in the first opening 140 and to partially recess the insulating layer 144 into the second opening 142. Figure 8A The etching process may use an etchant selective for etching the insulating layer 144, and the first nanostructure 110 and the substrate 101 may remain relatively unetched. The etching process may be an isotropic etching process. In some embodiments, the isotropic etching process is performed for a sufficient time to remove the insulating layer 144 in the first opening 140 and to laterally recess the insulating layer 144 in the second opening 142. Thus, the insulating layer 144 is substantially or completely removed in the first opening 140. In embodiments where the insulating layer 144 remains in the first opening 140 after the isotropic etching process, other anisotropic processes may be performed to substantially or completely remove the insulating layer 144 in the first opening 140.

[0107] exist Figure 11A and Figure 11B In some embodiments, an internal spacer 150 is formed in a lateral recess and on the sidewall of the insulating layer 144. The internal spacer 150 can serve as an isolation feature between the subsequently formed source / drain regions and the gate structure. As discussed in more detail below, the source / drain regions will be formed in the first opening 140, and the insulating layer 144 will be replaced by the gate structure.

[0108] In some embodiments, the internal spacer layer is deposited by a conformal deposition process such as CVD, ALD, or the like. The internal spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material such as a low-k dielectric material may be used. The internal spacer layer may then be anisotropically etched to form internal spacer 150 using gate spacer 138 as a mask, such as from RIE, NBE, or the like. Although the outer sidewalls of internal spacer 150 are illustrated in... Figure 11A The inner spacer 150 is flush with the sidewall of the first nanostructure 110, but the outer sidewall of the inner spacer 150 may extend beyond the first nanostructure 110 or be recessed from the sidewall of the first nanostructure 110. Furthermore, although the outer sidewall of the inner spacer 150 is flush with the sidewall of the first nanostructure 110, the outer sidewall of the inner spacer 150 may extend beyond the first nanostructure 110 or be recessed from the sidewall of the first nanostructure 110. Figure 11A The diagram shows a straight line, but the outer sidewall of the internal spacer 150 may be recessed or convex.

[0109] exist Figure 12A and Figure 12B In some embodiments, a dielectric filler 154 is formed in the first opening 140. The dielectric filler 154 may be formed, for example, by depositing a relatively thick dielectric layer on the bottom of the first opening 140 and a relatively thin dielectric layer on the sidewalls of the first opening 140, and a trimming etch process may then be performed to remove the dielectric layer on the sidewalls of the first opening 140. The deposition of the dielectric layer may include FCVD, PECVD, LPCVD, combinations thereof, or the like. The trimming etch process may be wet etching, dry etching with a suitable tilt angle, or a combination thereof. In some embodiments, the dielectric layer deposition process and the trimming etch process may be repeated to allow the dielectric filler 154 to have sufficient thickness at the bottom of the first opening 140. The dielectric filler 154 may at least cover the exposed surface of the first opening 140 below the bottom insulating layer 144 to isolate the subsequently formed source / drain regions 158. Figure 13A ) and substrate 101. Since the first opening 140 extends deeply into the substrate 101, the dielectric filler 154 can effectively reduce or prevent leakage or crosstalk between adjacent epitaxial source / drain regions. Figure 13A ).

[0110] The upper surface of the dielectric filler 154 may be a planar surface, a raised surface, or a recessed surface. In some embodiments, as illustrated in Figure 12C, the upper surface of the dielectric filler 154 may be a recessed surface to allow a larger volume of source / drain regions 158 to be formed in the first opening 140, which can provide improved electrical performance. The upper surface of the dielectric filler 154 may vertically overlap with the bottom spacer 150 (e.g., between the bottom of the bottom first nanostructure 110 and the top of the fin 114 / substrate 101). The dielectric filler 154 may not be in physical contact with the first nanostructure 110.

[0111] exist Figure 13A and Figure 13BIn some embodiments, a source / drain region 158 is formed in a first opening 140 and over a dielectric filler 154. In this disclosure, the source and drain regions are used interchangeably and have substantially the same structure. Furthermore, the source / drain regions may be referred to individually or collectively as source or drain depending on the context. The source / drain regions can apply stress to the first nanostructure 110, thereby improving device performance. For an n-type channel FET, the source / drain region 158 may be formed of one or more Si, SiP, SiC, and SiCP layers, or for a p-type channel FET, it may be formed of one or more Si, SiGe, and Ge layers. For a p-type field-effect transistor (PFET), p-type impurities such as boron, boron fluoride, indium, or the like may be included in the source / drain region 158. For an n-type field-effect transistor (NFET), n-type impurities such as phosphorus, arsenic, antimony, or the like may be included in the source / drain region 158. The source / drain region 158 may be formed using epitaxial growth methods such as CVD, ALD, MBE, combinations thereof, or the like, and may also be referred to as epitaxial source / drain region 158. In some embodiments, the impurities may be in-situ doped during epitaxial deposition of the source / drain region 158. The source / drain region 158 may have a density between approximately 1 × 10⁻⁶. 19 atoms / cm 3 With 1×10 21 atoms / cm 3 The impurity concentration between. In some embodiments, the source / drain regions 158 are grown to form facets that may correspond to crystal planes of the material used for the substrate 101.

[0112] exist Figure 14A and Figure 14BIn some embodiments, a contact etch stop layer (CESL) 160 is conformally formed on the exposed surface of the semiconductor device 100. The CESL 160 covers the sidewalls of the isolation region 120, the source / drain region 158, and the gate spacer 138. The CESL 160 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon nitride, silicon oxide, silicon carbide, or similar combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 162 is formed on the CESL 160 over the semiconductor device 100. The material of the first ILD layer 162 may include compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, SiOC, PSG, BSG, BPSG, combinations thereof, or similar materials. Organic materials such as polymers may also be used in the first ILD layer 162. The first ILD layer 162 may be deposited using FCVD, PECVD, or other suitable deposition techniques. In some embodiments, after the first ILD layer 162 is deposited, a thermal process is performed to cure the first ILD layer 162. After the first ILD layer 162 is formed, a planarization operation, such as CMP, is performed to align the top surface of the first ILD layer 162 with the top surface of the dummy gate electrode 134 or the hard mask 136. In some remaining embodiments of the hard mask 136, the planarization process aligns the top surface of the first ILD layer 162 with the top surfaces of the hard mask 136 and the gate spacer 138. In some embodiments, the top surfaces of the dummy gate electrode 134, the gate spacer 138, and the first ILD layer 162 are aligned within a variation of the process after the planarization process. In such embodiments, the top surface of the dummy gate electrode 134 is exposed via the first ILD layer 162.

[0113] In some embodiments, an optional first capping layer (not shown) is formed over the first ILD layer 162. Forming the first capping layer may include recessing the first ILD layer 162 between the dummy gate electrodes 134 and filling the recess with the first capping layer formed by the recessing process. Filling the recess with the first capping layer can be achieved by any suitable deposition process, such as CVD, PECVD, ALD, or other suitable methods. In some embodiments, a planarization process is then performed to remove excess portions of the first capping layer over the dummy gate electrodes 134, such that the upper surface of the first capping layer is flush with the upper surface of the dummy gate electrodes 134 or the hard mask 136 (if present). In some embodiments, the first capping layer includes silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or the like. The first capping layer protects the first ILD layer 162 from... Figure 16A and Figure 16B The process of removing the insulating layer 144, as illustrated in the figure, is damaged.

[0114] exist Figure 15A and Figure 15B In this process, the dummy gate electrode 134 and the hard mask 136 (if present) are removed. In some embodiments, the dummy gate dielectric 132 is also removed after the dummy gate electrode 134 is removed. The hard mask 136, the dummy gate electrode 134, and the dummy gate dielectric 132 may be removed by one or more etching processes. For example, the etching process may be performed by etching the hard mask 136 using the dummy gate electrode 134 as an etch stop layer, etching the dummy gate electrode 134 using the dummy gate dielectric 132 as an etch stop layer, and then removing the dummy gate dielectric 132 by another etching process. In some embodiments, the etching process for etching the dummy gate electrode 134 and the dummy gate dielectric 132 may include using a reactive gas that selectively etches the dummy gate electrode 134 and the dummy gate dielectric 132 at a faster rate than the first ILD layer 162 or the gate spacer 138. Figure 15B As illustrated, after the dummy gate dielectric 132 and dummy gate electrode 134 are removed, the insulating layer 144 is exposed.

[0115] exist Figure 16A and Figure 16B In some embodiments, insulating layer 144 is removed. Insulating layer 144 may be removed by an isotropic etching process, such as wet etching containing an etchant containing diluted HF or other suitable etchant. Removal of hard mask 136, dummy gate electrode 134, dummy gate dielectric 132 and insulating layer 144 forms a third opening 164 between gate spacers 138 and between first nanostructures 110. In some embodiments, such as those illustrated in Figures 8A to 11B The process involving insulating layer 144 can be omitted, leaving the second nanostructure 112 intact and unreplaced by insulating layer 144. In such embodiments, the third opening 164 is formed by removing the second nanostructure 112, and as... Figures 12A to 15B Features such as the internal spacer 150 and dielectric filler 154 shown in the diagram are still formed and positioned as follows: Figure 16A The location shown in the drawing.

[0116] In some embodiments, an optional second capping layer (not shown) is formed over the isolation region 120 before the insulating layer 144 is removed. Forming the second capping layer may include depositing a dielectric material over the upper surface of the isolation region 120 and over the exposed surfaces of the first nanostructure 110 and the insulating layer 144. In some embodiments, the thickness of the dielectric material over the upper surface of the isolation region 120 may be greater than the thickness of the dielectric material over the exposed surfaces of the first nanostructure 110 and the insulating layer 144 by adjusting appropriate deposition parameters or according to a deposition method (e.g., FCVD). An etching process may then be performed to remove the dielectric material over the exposed surfaces of the first nanostructure 110 and the insulating layer 144, while some of the dielectric material on the upper surface of the isolation region 120 may remain to form the second capping layer. The etching process may include a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the second capping layer includes silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, combinations thereof, or the like. The second top cover layer protects the isolation zone 120 from damage during the process of removing the insulation layer 144.

[0117] exist Figure 17A and Figure 17B In this configuration, a gate dielectric layer 168 and a gate electrode 170 are formed to replace the gate. The gate dielectric layer 168 is conformally deposited in a third opening 164. The gate dielectric layer 168 may be formed on the top surface and sidewalls of the substrate 101 and on the exposed surface of the first nanostructure 110. In some embodiments, the gate dielectric layer 168 is also deposited on the top surface of the first ILD layer 162 (or the second capping layer, if present), CESL 160, gate spacer 138, and isolation region 120. In some embodiments, the gate dielectric layer 168 comprises one or more layers such as dielectric materials such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-alumina (HfO-AlO) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 168 can be formed by CVD, ALD, or any suitable deposition technique.

[0118] Gate electrodes 170 are deposited over gate dielectric layer 168 and fill the remaining portion of third opening 164. Gate electrode 170 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers. Although a single-layer electrode 170 is illustrated... Figure 17A and Figure 17BIn this process, the gate electrode 170 may comprise any number of liner layers, any number of work function tuning layers, and filler material. The gate electrode 170 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. After filling the third opening 164, excess material on the gate dielectric layer 168 and the gate electrode 170 above the top surface of the first ILD layer 162 is then removed by a planarization process such as CMP until the top surface of the first ILD layer 162 is exposed. The remaining portion of the gate electrode 170 and the gate dielectric layer 168 thus forms an alternative gate structure for the semiconductor device 100. The gate electrode 170 and the gate dielectric layer 168 may be collectively referred to as gate structure 172. Gate structure 172 may surround a channel (i.e., the first nanostructure 110) of the semiconductor device 100.

[0119] As by Figure 18A and Figure 18B Further illustration shows that a second ILD layer 174 is deposited over a first ILD layer 162. In some embodiments, the second ILD layer 174 is formed of a dielectric material similar to those materials of the first ILD layer 162, and is formed by a method similar to that used for the first ILD layer 162. In some embodiments, a CESL 176 is also formed prior to the formation of the second ILD layer 174. The CESL 176 may comprise a material similar to those materials of the CESL 160, and may be formed using a method similar to that used for the CESL 160.

[0120] exist Figure 19A and Figure 19B In some embodiments, contacts 178 and 180 are formed in the first ILD layer 162 and the second ILD layer 174. Contact 178 is electrically coupled to the source / drain region 158 and may be referred to as a source / drain contact. Because contact 178 is formed above the front side 101F of the substrate 101, contact 178 may also be referred to as a front contact or a front source / drain contact. Contact 180 is electrically coupled to the gate structure 172 and may be referred to as a gate contact.

[0121] In some embodiments, contact 178 is electrically coupled to only one of two adjacent source / drain regions 158. For example, contact 178 may extend to physically connect to the front side of a target source / drain region 158. Figure 19AAn example of four source / drain regions 158, including a first source / drain region 158A, a second source / drain region 158B, a third source / drain region 158C, and a fourth source / drain region 158D, is illustrated. A contact 178 is electrically coupled to the first source / drain region 158A and the third source / drain region 158C, while the second source / drain region 158B and the fourth source / drain region 158D are covered by a first ILD layer 162 and are not connected to the contact 178. In other words, there are no conductive features disposed in the first ILD layer 162 and extending to connect to the second source / drain region 158B or the fourth source / drain region 158D. As will be described in more detail below, the back contact 192 ( Figure 23A The source / drain region 158 is formed and connected to the back side (i.e., the side adjacent to the substrate 101), which is not connected to the contact 178, such as to the back side of the second source / drain region 158B and the fourth source / drain region 158D. The first source / drain region 158A, the second source / drain region 158B, the first nanostructure 110 between the first source / drain region 158A and the second source / drain region 158B, the front source / drain contact 178, and the back source / drain contact 192 can form a transistor structure 100A. In such embodiments, the first nanostructure 110A can act as a channel for the transistor structure 100A, and the first source / drain region 158A and the second source / drain region 158B can together form the source / drain region for the first nanostructure 110A. Current / signal can flow in and out through the front contact 178 and the back contact 192.

[0122] In some embodiments, forming contacts 178 and 180 includes etching a second ILD layer 174, a first ILD layer 162, a CESL 176, and / or a CESL 160 to form recesses that expose the surfaces of the source / drain regions 158 and / or the gate structure 172, and materials for contacts 178 and 180 are then deposited in the recesses. The recesses can be formed by etching using one or more anisotropic etching processes such as RIE, NBE, or the like.

[0123] Contacts 178 and 180 may each comprise one or more layers, such as a barrier layer, an adhesive layer, and a filler material above the barrier layer and / or adhesive layer. In some embodiments, the barrier layer of contacts 178 and 180 comprises titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material of contacts 178 and 180 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, contact 178 also includes a silicide region 182 in contact with the source / drain region 158 to reduce resistance. The silicide region 182 may be formed between the barrier layer (or filler material) and the source / drain region 158 by reacting the material of the barrier layer (or filler material) of contact 178 with the semiconductor material of the source / drain region 158. Although the silicide region 182 is referred to as a silicide region, the silicide region 182 may also be a germanide region or a Germanium silicide region. Planarization processes such as CMP can be performed to remove excess material above the top surface of the second ILD layer 174 at contacts 178 and 180.

[0124] Figures 20A to 23B and Figures 25A to 25B The illustration shows the following intermediate steps according to some embodiments: forming a front-side interconnect structure 183 (illustrated in) above the front side 101F of the substrate 101. Figure 20A and Figure 20B (middle), forming a back contact 192 in the substrate 101 (illustrated in the middle), Figure 23A and Figure 23B (in the middle), and a back-side interconnect structure 195 (illustrated in the middle) is formed above the back side 101B of the substrate 101. Figure 25A and Figure 25B (Middle). The front interconnect structure 183 and the back interconnect structure 195 may each include conductive features that are electrically coupled to the transistor structure 100A or other transistor structures. As mentioned above, the back contact 192 may be connected to a source / drain region 158 that is not connected to the front source / drain contact 178, such as as shown in the figure. Figure 19A The second source / drain region 158B and the fourth source / drain region 158D are in the middle.

[0125] exist Figure 20A and Figure 20B In some embodiments, a front interconnect structure 183 is formed over the front side 101F of the substrate 101, such as over the second ILD layer 174. The front interconnect structure 183 may include one or more layers of conductive features 184 formed in one or more stacked dielectric layers 186. Each of the stacked dielectric layers 186 may contain a dielectric material such as silicon oxide, PSG, BSG, BPSG, low-k dielectric materials, combinations thereof, or the like. The dielectric layers 186 may be deposited using suitable processes such as CVD, PECVD, PVD, or the like.

[0126] Conductive feature 184 may include conductive wiring and conductive vias interconnecting conductive wiring layers. Conductive vias may extend through individual layers in dielectric layer 186 to provide vertical connections between conductive wiring layers. Conductive feature 184 may be formed via any acceptable process such as a single damascene process, a dual damascene process, a combination thereof, or the like. For example, conductive feature 184 may be formed using a damascene process, in which individual dielectric layers 186 are patterned using a combination of optical lithography and etching techniques to form trenches corresponding to the desired pattern of conductive feature 184. Optional diffusion barrier layers and / or optional adhesive layers may be deposited, and the trenches may then be filled with a conductive material. Suitable materials for barrier layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, and combinations thereof, or the like, and suitable conductive materials include copper, silver, gold, tungsten, aluminum, and combinations thereof, or the like. In an embodiment, conductive feature 184 may be formed by depositing a copper or copper seed layer and filling the trenches by electroplating. Chemical mechanical planarization (CMP) processes or similar methods can be used to remove excess conductive material from the surface of individual dielectric layers 186 and planarize the surfaces of dielectric layers 186 and conductive features 184 for subsequent processing.

[0127] Figure 20A and Figure 20B The diagram illustrates the five layers of conductive features 184 and dielectric layers 186 in the front interconnect structure 183. However, it should be understood that the front interconnect structure 183 may include any number of conductive features 184 disposed on any number of dielectric layers 186. The front interconnect structure 183 may be electrically connected to source / drain contacts 178 and gate contacts 180. In some embodiments, the front interconnect structure 183 may also include bump pads at the top layer of the front interconnect structure 183 for external connections. External connections may be electrically coupled to the source / drain region 158 via the front interconnect structure 183 and contacts 178.

[0128] exist Figure 21A and Figure 21B In this process, the carrier substrate 188 is bonded to the top surface of the front interconnect structure 183 via a bonding layer 190. The carrier substrate 188 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. The carrier substrate 188 provides structural support during subsequent processing steps and in the finishing apparatus.

[0129] In some embodiments, the bonding layer 190 may be a heat-releasing material that loses its adhesive properties upon heating, such as a light-to-heat-conversion (LTHC) release coating; an ultraviolet (UV) adhesive that loses its adhesive properties upon exposure to UV light; or the like. The bonding layer 190 may be applied as a liquid and cured. After the carrier substrate 188 is bonded to the front interconnect structure 183, the semiconductor device 100 may be flipped so that the back side 101B of the substrate 101 faces upward. According to some embodiments, a thinning process is then applied to the back side 101B of the substrate 101. The thinning process may include planarization processes (e.g., mechanical polishing, CMP, or the like), etch-back processes, combinations thereof, or the like.

[0130] exist Figure 22A and Figure 22B In some embodiments, an opening 191 of the back contact 192 is formed in the substrate 101. The opening 191 may extend from the back side 101B of the substrate 101 and through the dielectric filler 154 to expose the back side of the source / drain region 158. As previously discussed, the opening 191 may extend only to expose the source / drain region 158 not connected to the front source / drain contact 178 or extend into the source / drain region 158. For example, the opening 191 may extend only to expose the second source / drain region 158B and the fourth source / drain region 158D or extend into the second source / drain region 158B and the fourth source / drain region 158D. The process for forming the opening 191 may include one or more etching processes, such as one or more anisotropic etching processes, such as RIE, NBE, or the like. For example, the process for forming the opening 191 may include a first etching process for etching through the substrate 101 from the back side 101B of the substrate, and a second etching process for etching through the dielectric filler 154 to expose the source / drain region 158 or extending into the source / drain region 158.

[0131] exist Figure 23A and Figure 23BIn some embodiments, back-side contacts 192 are formed in openings 191. In some embodiments, each back-side contact 192 may include one or more layers, such as a barrier layer and a filler material above the barrier layer. In some embodiments, the barrier layer of the back-side contact 192 includes titanium, titanium nitride, tantalum, tantalum nitride, or the like. The filler material of the back-side contact 192 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, the back-side contact 192 also includes a silicide region 194 (not shown in the illustrated transistor structure 100A for clarity) that contacts the source / drain region 158 to reduce resistance. The silicide region 194 may be formed between the barrier layer (or filler material) and the source / drain region 158 by reacting the material of the barrier layer (or filler material) of the back-side contact 192 with the semiconductor material of the source / drain region 158. A planarization process, such as CMP, can be performed to remove excess material from the back contact 192 above the back side 101B of the substrate 101.

[0132] After forming the back-side contact 192, each transistor structure 100A may include a front-side contact 178 and a back-side contact 192 disposed vertically on opposite sides of the channel (i.e., the first nanostructure 110). Therefore, the current path between the front-side contact 178 and the back-side contact 192 may be substantially the same, regardless of which first nanostructure 110 the current is transmitted through. Figure 19A In the diagram, the current path P1 (illustrated wirelessly) passing through the topmost first nanostructure 110 (maximally adjacent to the first ILD layer 162) and the current path P2 (illustrated by dashed lines) passing through the bottommost first nanostructure 110 (closest to the substrate 101) are illustrated for illustrative purposes. In some embodiments, the current path from one contact 178 / 192 to another contact 192 / 178 is the same regardless of which of the first nanostructures 110 the current passes through, because the total vertical transmission distance from one contact 178 / 192 to another contact 192 / 178 is fixed by setting contacts 178 and 192 on opposite sides of the source / drain region 158, and the lateral transmission distance is also fixed by forming a deeply extending first opening 140. Figure 7A Therefore, all channels of the 100A transistor structure can respond to input current or signals simultaneously. Figure 24 To illustrate a scheme for the on / off switching system of the input current relative to the transistor structure 100A disclosed herein and a general transistor structure 10, wherein the general transistor structure 10 includes both source / drain contacts disposed on the same side of the nanostructure channel and / or nanostructure channels of different lengths. Transistor structure 100A may have a relationship with respect to the input current (e.g., drain-to-source current I). DSThe rapid turn-on / turn-off switching system of the transistor structure 10, caused by the change in the distance of the current path between the two source / drain contacts, can be substantially eliminated.

[0133] exist Figure 25A and Figure 25B In some embodiments, a back-side interconnect structure 195 is formed above the exposed surfaces of the back side 101B and back-side contacts 192 of the substrate 101. The back-side interconnect structure 195 includes conductive features and a dielectric layer similar to those of the front-side interconnect structure 183. The back-side interconnect structure 195 may include conductive features 196 stacked in the dielectric layer 198. The back-side interconnect structure 195 is formed by methods similar to those used for the front-side interconnect structure 183. For example, forming the conductive features 196 may include patterning recesses in the dielectric layer 198, for example, using a combination of optical lithography and etching processes. The pattern of the recesses in the dielectric layer 198 may correspond to the pattern of the conductive features 196. The conductive features 196 are then formed by depositing a conductive material in the recesses. In some embodiments, the conductive features 196 include a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the conductive features 196 include copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like. Optional diffusion barrier layers and / or optional adhesive layers may be deposited prior to filling the recess with a conductive material. Suitable materials for the barrier / adhesive layers include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or the like. Conductive feature 196 may be formed using, for example, CVD, ALD, PVD, electroplating, or the like. Conductive feature 196 is electrically coupled to the source / drain region 158 via a back-side contact 192.

[0134] In some embodiments, conductive feature 196 includes power rails that are conductive connections electrically connecting source / drain regions 158 to a reference voltage, supply voltage, or the like. Advantages are achieved by placing the power rails on the back side of the semiconductor device rather than the front side of the semiconductor die. For example, the gate density of semiconductor device 100 and the interconnect density of front-side interconnect structure 183 can be increased. Additionally, the back side of semiconductor device 100 can accommodate wider power rails, thereby reducing resistance and increasing the efficiency of power delivery to semiconductor device 100. For example, the width of conductive feature 196 can be at least twice the width of the first standard of the conductive connection of front-side interconnect structure 183.

[0135] In some embodiments, the back-side interconnect structure 195 further includes bump pads at the top layer for external connections. These external connection bump pads, also referred to as back-side input / output pads, can provide signal, power supply voltage, and / or ground connections to the nanostructure transistors. The back-side interconnect structure 195 may include one or more embedded passive devices (not shown), such as resistors, capacitors, inductors, or the like. These embedded passive devices may be integrated with conductive features 196 (e.g., power rails) to provide circuitry (e.g., power circuitry) on the back side of the transistor structure 100A.

[0136] Figure 26A and Figure 26B The figure shows a cross-sectional view of a semiconductor device 200 according to some embodiments. Semiconductor device 200 is similar to semiconductor device 100 and can be seen in figures 1A to 1900. Figure 23B and Figures 25A to 25B The process is formed in the process, where similar reference figures refer to similar components. In Figure 26A and Figure 26B In the semiconductor device 200, a dummy contact 279 is also formed above the front side of the substrate 101. For example, the dummy contact 279 may be formed above and connected to the front side of the source / drain region 158, which is also connected to the back contact 192. For example, the dummy contact 279 is formed and connected to the front side of the second source / drain region 158B and the fourth source / drain region 158D. The top surface of the dummy contact 279 may be completely sealed or covered by the dielectric layer 186 of the front interconnect structure 183. Therefore, the dummy contact 279 is not electrically and physically coupled to the conductive feature 184 of the front interconnect structure 183, and the presence of the dummy contact 279 will not substantially affect the current path between the front contact 178 and the back contact 192. The dummy contact 279 may be formed in the same process, such as in the figure shown. Figure 19A and Figure 19B The dummy contact 279 is formed together with the back-side contact 178 in the process. The dummy contact 279 may have the same structure and material as contact 178. For example, the dummy contact 279 may have the same height as contact 178. In some embodiments, the dummy contact 279 also includes a silicide region 281 in contact with the source / drain region 158. The formation of the dummy contact 279 can facilitate the manufacturing process. For example, the semiconductor device 200 may have a uniform pattern density of contacts 279, 178, and 180, which can help reduce dishing caused by planarization processes, reduce lithography, and reduce isodensity loading in etching or deposition processes.

[0137] Figure 27A and Figure 27BThe figures illustrate a cross-sectional view of a semiconductor device 300 according to some embodiments. Semiconductor device 300 is similar to semiconductor device 100 or 200 and may include any suitable features of semiconductor device 100 or 200, wherein similar reference numerals refer to similar elements. According to some embodiments, semiconductor device 300 may be as illustrated in Figures 1A to 1980. Figure 23B and Figures 25A to 25B It is formed using the processes described in the text. Figure 27A and Figure 27B In some embodiments, contacts 392 / 378 may extend into the source / drain region 158. In some embodiments, the back-side contact 392 (including the silicide region 394) vertically overlaps with the bottom first nanostructure 110 (most adjacent to the substrate 101). In some embodiments, for example, the front-side contact 378 also extends to vertically overlap the top first nanostructure 110 (most adjacent to the first ILD layer 162) to reduce the distance variation of the current path. In some embodiments, the semiconductor device 400 provides greater process tolerance for etching processes to form contacts 378 and 392.

[0138] Figure 28A and Figure 28B The figures illustrate a cross-sectional view of a semiconductor device 400 according to some embodiments. Semiconductor device 400 is similar to semiconductor devices 100, 200, or 300 and may include any suitable features of semiconductor devices 100, 200, or 300, wherein similar reference numerals refer to similar elements. According to some embodiments, semiconductor device 400 may be as illustrated in Figures 1A to 1900. Figure 23B and Figures 25A to 25B It is formed using the processes described in the text. Figure 28A and Figure 28B In this embodiment, semiconductor device 400 includes a semiconductor filler 455 disposed between dielectric filler 154 and substrate 101. Semiconductor filler 455 may be a material similar to those used in substrate 101. For example, semiconductor filler 455 may be monocrystalline silicon. Semiconductor filler 455 may be formed by any suitable method, such as epitaxial deposition, and may be in-situ doped. In some embodiments, semiconductor filler 455 may have the same type of dopant as adjacent wells, such as a p-type dopant for a p-type well in NMOS, or an n-type dopant for an n-type well in PMOS. Semiconductor filler 455 may be formed in the first opening 140 prior to the formation of dielectric filler 154. In some embodiments, semiconductor filler 455 may act as a buffer between substrate 101 and dielectric filler 145, such as thereby reducing stress or minimizing the impact on wells in the substrate (if doped).

[0139] The embodiments disclosed herein provide a transistor structure including a plurality of nanostructure channels disposed between source and drain regions, wherein the plurality of nanostructure channels have the same length. In some embodiments, the transistor structure also includes a front contact electrically coupled to the front side of one of the source / drain regions and a back contact electrically coupled to the back side of the other source / drain regions. Therefore, regardless of which nanostructure channel current is transmitted through, the lateral and vertical transmission distances of the current between the contacts will be fixed and substantially the same. The transistor structure disclosed herein can therefore have rapid turn-on and turn-off transitions.

[0140] One embodiment is a semiconductor device comprising: a first channel region disposed above a semiconductor substrate; a gate structure disposed above the first channel region; a first source / drain region disposed on a first side of the first channel region; a second source / drain region disposed on a second side of the first channel region; an interlayer dielectric layer disposed above the first channel region, the first source / drain region, and the second source / drain region; a first contact disposed in the interlayer dielectric layer and electrically coupled to the first source / drain region; and a second contact disposed in the semiconductor substrate and electrically coupled to the second source / drain region. In one embodiment, the semiconductor device further comprises a first dielectric filler disposed between the first source / drain region and the semiconductor substrate. In another embodiment, the semiconductor device further comprises a semiconductor filler disposed between the first dielectric filler and the semiconductor substrate. In one embodiment, the semiconductor further includes a second dielectric filler disposed between the first source / drain region and the semiconductor substrate, and the second contact extends through the semiconductor substrate and the second dielectric filler. In one embodiment, a non-conductive feature is disposed in the interlayer dielectric layer and electrically coupled to the second source / drain region. In one embodiment, the semiconductor device further includes a dummy contact disposed in the interlayer dielectric layer and connected to the second source / drain region; and a dielectric layer that contacts the dummy contact and completely covers a top surface of the dummy contact. In one embodiment, the semiconductor device further includes a second channel region disposed above the first channel region, wherein the first channel region and the second channel region have the same length, and the gate structure surrounds the first channel region and the second channel region.

[0141] Another embodiment is a semiconductor device comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first channel region and a second channel region disposed above the front side of the semiconductor substrate, wherein the first channel region and the second channel region have the same length and are disposed between a first epitaxial region and a second epitaxial region; a first contact disposed above the front side of the semiconductor substrate and laterally aligned with the first epitaxial region; a first interconnect structure disposed above the front side of the semiconductor substrate and electrically coupled to the first epitaxial region via the first contact; a second contact disposed in the semiconductor substrate and laterally aligned with the second epitaxial region; and a second interconnect structure disposed above the back side of the semiconductor substrate and electrically coupled to the second epitaxial region via the second contact. In one embodiment, the second interconnect structure includes a power rail. In one embodiment, the semiconductor device further includes a third contact disposed above the front side of the semiconductor substrate and laterally aligned to the second epitaxial region, wherein the third contact is a dummy contact. In one embodiment, the first contact and the third contact have the same height. In one embodiment, the semiconductor device further includes a first dielectric filler separating the first epitaxial region from the semiconductor substrate. In one embodiment, the semiconductor device further includes a second dielectric filler separating the first epitaxial region from the semiconductor substrate, and the second contact extends through the second dielectric filler. In one embodiment, the first contact and the second contact each include a silicide region. In one embodiment, the first interconnect structure and the second interconnect structure each include bonding pads for multiple external connections.

[0142] Another embodiment is a semiconductor device comprising: a semiconductor substrate having a front side and a back side opposite to the front side; a first channel region and a second channel region disposed above the front side of the semiconductor substrate, wherein the first channel region and the second channel region have the same length and are disposed between a first epitaxial region and a second epitaxial region; a first dielectric filler separating the first epitaxial region from the semiconductor substrate; a first contact disposed above the front side of the semiconductor substrate and laterally aligned with the first epitaxial region; a first interconnect structure disposed above the front side of the semiconductor substrate and electrically coupled to the first epitaxial region via the first contact; a second contact disposed in the semiconductor substrate and laterally aligned with the second epitaxial region; and a second interconnect structure disposed above the back side of the semiconductor substrate and electrically coupled to the second epitaxial region via the second contact.

[0143] Another embodiment is a method for forming a semiconductor device, the method comprising: forming a first channel region disposed above a semiconductor substrate; forming a first source / drain region and a second source / drain region on a first side and a second side of the first channel region, respectively; forming an interlayer dielectric layer disposed above the first channel region, the first source / drain region, and the second source / drain region; forming a gate structure above the first channel region; forming a first contact in the interlayer dielectric layer, wherein the first contact is electrically coupled to the first source / drain region; and forming a second contact in the semiconductor substrate, wherein the second contact is electrically coupled to the second source / drain region. In one embodiment, the step of forming the first source / drain region includes: forming an opening to expose the first side of the first channel region; and depositing an epitaxial structure in the opening, wherein the method further includes a step of depositing a dielectric filler in the opening prior to the step of depositing the epitaxial structure. In one embodiment, the method further includes forming a second channel region and a third channel region below the first channel region when forming the first channel region, wherein the opening includes a first portion exposing the second channel region and the third channel region and a second portion below the first portion, wherein the first portion of the opening has a fixed width and the second portion of the opening has a gradually narrowing width. In one embodiment, the method further includes forming a first interconnect structure above the first contact before forming the second contact. In one embodiment, the method further includes forming a second interconnect structure on the side of the semiconductor substrate away from the first interconnect structure, wherein the second interconnect structure includes a power rail.

[0144] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A first channel region is disposed above a semiconductor substrate; A gate structure is disposed above the first channel region; A first source / drain region is disposed on a first side of the first channel region; A second source / drain region is disposed on a second side of the first channel region; An interlayer dielectric layer is disposed above the first channel region, the first source / drain region, and the second source / drain region; A first contact is disposed in the interlayer dielectric layer and electrically coupled to the first source / drain region; and A second contact is disposed in the semiconductor substrate and electrically coupled to the second source / drain region.

2. The semiconductor device as claimed in claim 1, characterized in that, It further includes a first dielectric filler between the first source / drain region and the semiconductor substrate.

3. The semiconductor device as claimed in claim 2, characterized in that, It further includes a semiconductor filler disposed between the first dielectric filler and the semiconductor substrate.

4. The semiconductor device as claimed in claim 1, characterized in that, It further includes a second dielectric filler disposed between the first source / drain region and the semiconductor substrate, and the second contact extends through the semiconductor substrate and the second dielectric filler.

5. The semiconductor device as claimed in claim 1, characterized in that, The non-conductive structure is disposed in the middle of the interlayer dielectric layer and electrically coupled to the second source / drain region.

6. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A dummy contact is disposed in the interlayer dielectric layer and connected to the second source / drain region; and A dielectric layer that contacts and completely covers the top surface of the dummy contact.

7. A semiconductor device, characterized in that, Include: A semiconductor substrate having a front side and a back side opposite to the front side; A first channel region and a second channel region are disposed above the front side of the semiconductor substrate, wherein the first channel region and the second channel region have the same length and are disposed between a first epitaxial region and a second epitaxial region. A first contact point is disposed above the front side of the semiconductor substrate and laterally aligned with the first epitaxial region; A first interconnect structure is disposed above the front side of the semiconductor substrate and electrically coupled to the first epitaxial region via the first contact; A second contact, disposed in the semiconductor substrate and laterally aligned with the second epitaxial region; and A second interconnect structure is disposed above the back side of the semiconductor substrate and electrically coupled to the second epitaxial region via the second contact.

8. The semiconductor device as claimed in claim 7, characterized in that, The second interconnection structure includes a power rail.

9. The semiconductor device as claimed in claim 7, characterized in that, It further includes a third contact disposed above the front side of the semiconductor substrate and laterally aligned with the second epitaxial region, wherein the third contact is a dummy contact.

10. A semiconductor device, characterized in that, Include: A semiconductor substrate having a front side and a back side opposite to the front side; A first channel region and a second channel region are disposed above the front side of the semiconductor substrate, wherein the first channel region and the second channel region have the same length and are disposed between a first epitaxial region and a second epitaxial region. A first dielectric filler that separates the first epitaxial region from the semiconductor substrate; A first contact point is disposed above the front side of the semiconductor substrate and laterally aligned with the first epitaxial region; A first interconnect structure is disposed above the front side of the semiconductor substrate and electrically coupled to the first epitaxial region via the first contact; A second contact, disposed in the semiconductor substrate and laterally aligned with the second epitaxial region; and A second interconnect structure is disposed above the back side of the semiconductor substrate and electrically coupled to the second epitaxial region via the second contact.

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