Semiconductor die package

Abstract

The utility model provides a kind of capacitor structure in the multiple semiconductor dies including image sensor device of semiconductor die package piece.In other examples, capacitor structure can be located on the front side of sensor die, directly bonded to the front side of application-specific integrated circuit die of sensor die and the back side of application-specific integrated circuit die.Including capacitor structure on the front side and back side of application-specific integrated circuit die can more effectively use the die area of application-specific integrated circuit die to integrate capacitor structure, which can increase the density of capacitor structure of image sensor device without sacrificing the area of sensor die of photodiode of pixel sensor.

Description

Technical Field

[0001] This utility model relates to an integrated circuit, and more particularly to a semiconductor die package. Background Technology

[0002] Various semiconductor device packaging technologies can be used to incorporate one or more semiconductor dies into a semiconductor die package. In some cases, semiconductor dies can be horizontally connected through interposers. Alternatively and / or vertically arranged within the semiconductor die package, this achieves a smaller horizontal or lateral footprint and / or increases the density of the semiconductor die package. Semiconductor dies can be directly connected via die-to-die (or wafer-to-wafer) bonding and / or via interconnects and one or more interposers. Utility Model Content

[0003] This invention provides a container structure and a second capacitor structure in a second interconnect layer. The semiconductor die package includes a second semiconductor die. The second semiconductor die includes a second substrate layer, a third interconnect layer perpendicularly adjacent to a first side of the second substrate layer, and a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors on a second side of the second substrate layer opposite to the first side. A first interconnect layer of a first semiconductor die is bonded to a third interconnect layer of the second semiconductor die.

[0004] This invention provides a semiconductor die package. The semiconductor die package includes a first semiconductor die. The first semiconductor die includes a first substrate layer, a first interconnect layer perpendicularly adjacent to a first side of the first substrate layer, a second interconnect layer perpendicularly adjacent to a second side of the first substrate layer opposite to the first side, a first capacitor structure in the first interconnect layer, and a second capacitor structure on a second side of the first substrate layer. The second capacitor structure extends from the second side of the first substrate layer into the first substrate layer. The semiconductor die package also includes a second semiconductor die. The second semiconductor die includes a second substrate layer, a third interconnect layer perpendicularly adjacent to a first side of the second substrate layer, and a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors on the second side of the second substrate layer opposite to the first side. The first interconnect layer of the first semiconductor die is bonded to the third interconnect layer of the second semiconductor die.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the figures and this disclosure. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic diagram of the example semiconductor die package described in this article.

[0008] Figure 2A and 2B This is a schematic diagram of the example capacitor structure described in this article.

[0009] Figures 3A-3E This is a schematic diagram illustrating an example embodiment of the semiconductor die (or a portion thereof) described herein.

[0010] Figures 4A-4D This is a schematic diagram illustrating an example embodiment of the semiconductor die (or a portion thereof) described herein.

[0011] Figures 5A-5D This is a schematic diagram illustrating an example embodiment of the semiconductor die package (or a portion thereof) described herein.

[0012] Figure 6A and 6B This is a schematic diagram illustrating an example embodiment of the semiconductor die package (or a portion thereof) described herein.

[0013] Figure 7A-7K This is a schematic diagram of an example implementation of the semiconductor die package described herein.

[0014] Figure 8 This is a flowchart of an example process related to forming the semiconductor die package described in this article.

[0015] Figure 9 This is a flowchart of an example process related to forming the semiconductor die package described herein. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description may include embodiments where a first feature is formed on or above a second feature, wherein the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or architectures discussed.

[0017] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “above,” and “upper” to describe the relationship between one component or feature and another component, as shown in the figure. In addition to the orientations shown in the figure, spatially related terms are also intended to cover different orientations of the device or operation in use. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein can be interpreted accordingly.

[0018] Complementary metal-oxide-semiconductor (CMOS) image sensor devices may include multiple semiconductor dies bonded together in a vertical stack. The image sensor dies in the vertical stack may include multiple pixel sensors arranged in a pixel sensor array. The pixel sensors in the pixel sensor array may include photodiodes configured to convert photons of incident light into a photocurrent. The magnitude of the photocurrent is at least partially based on the intensity of the incident light. Therefore, if the pixel sensors in the pixel sensor array are capable of sensing incident light over a wide intensity range, a high range of brightness and contrast can be achieved in the image and / or video generated by the CMOS image sensor assembly.

[0019] In some cases, a pixel sensor may limit the number of incident photons it can absorb before it reaches saturation. "Saturation" refers to the level of photon absorption beyond which the pixel sensor can no longer absorb additional photons. Pixel sensor saturation results in a limited dynamic range because it cannot obtain additional brightness and color information through further photon absorption.

[0020] The amount of photocurrent charge that can be stored in a pixel sensor before saturation is called the full well capacity (FWC) of the pixel sensor. In other examples, the full well capacity of a pixel sensor may be based at least in part on the size (e.g., depth, width, volume) and / or shape of the photodiode in the pixel sensor. However, while increasing the size of the photodiode can increase the full well capacity of the pixel sensor, this may come at the cost of reducing the pixel density in the pixel sensor array, which could reduce the resolution of the pixel sensor array.

[0021] In some embodiments described herein, an image sensor device (e.g., a complementary metal-oxide-semiconductor (CMOS) image sensor device) includes capacitor structures within multiple semiconductor dies of the image sensor device. The capacitor structures may be configured to store charge associated with photocurrents generated by pixel sensors in the pixel sensor array of the sensor die of the image sensor assembly. In other examples, the capacitor structures may be located on the front side of the sensor die, on the front side of an application-specific integrated circuit (ASIC) die directly bonded to the sensor die, and on the back side of the ASIC die. Capacitor structures included on the back side of the ASIC die may be included in the back side of the semiconductor substrate of the ASIC die, and / or may be included in an interconnect layer (e.g., a back-of-line (BEOL) region or a back-end region) perpendicularly adjacent to the semiconductor substrate. Including capacitor structures on the front and back sides of the ASIC die allows for more efficient utilization of the ASIC die area to integrate the capacitor structures, which can increase the density of capacitor structures in the image sensor device without sacrificing the sensor die area of ​​the photodiodes of the pixel sensors.

[0022] The photocurrent generated by the pixel sensors in a pixel sensor array can be transferred to a capacitor structure located throughout the semiconductor die of the image sensor device. This allows the pixel sensor to generate more charge photocurrent than if all the photocurrent were stored in photodiodes and / or floating diffusion nodes. Therefore, the capacitor structure increases the overall well capacity of the pixel sensor. This increased overall well capacity of the pixel sensor enables a wider range of brightness and / or contrast in images and / or videos produced by the pixel sensor array.

[0023] Additionally and / or alternatively, the increased full-well capacity of the pixel sensor enables global shutter functionality in image sensor devices. Global shutter is an image sensor exposure technique where all pixels in the pixel sensor array are simultaneously exposed to incident light, rather than sequentially exposing rows of pixels (called a rolling shutter). When using this progressive exposure to capture fast-moving objects, rolling shutters can produce incomplete images and / or distortions, potentially due to image deformation caused by differences in output time. The increased full-well capacity provided by the capacitor structure of the image sensor device allows the pixels in the pixel sensor array to simultaneously accumulate charge of the incident light during global shutter exposure. This can improve image quality for fast-moving objects, reduce image blur, and enhance overall image quality.

[0024] Figure 1 This is a schematic diagram of the example semiconductor die package 100 described in this article. Figure 1 A cross-sectional view of a semiconductor die package 100 is shown. (As shown) Figure 1 As shown, in other examples, the semiconductor die package 100 includes a plurality of semiconductor dies, including semiconductor die 102, semiconductor die 104, and semiconductor die 106. Other numbers of semiconductor dies in the semiconductor die package 100 are within the scope of this disclosure.

[0025] Semiconductor dies 102-106 can be vertically arranged in a stack or in a semiconductor die package 100. For example, semiconductor dies 102 and 104 can be bonded at a bonding interface 108a, such that semiconductor dies 102 and 104 are stacked and vertically arranged in the semiconductor die package 100. As another example, semiconductor dies 104 and 106 can be bonded at a bonding interface 108b, such that semiconductor dies 104 and 106 are stacked and vertically arranged in the semiconductor die package 100. In other example bonding architectures, the bonding between semiconductor dies 102 and 104 and the bonding between semiconductor dies 104 and 106 can be formed by bonding semiconductor wafers together (e.g., wafer-to-wafer bonding), by bonding dies together (die-to-die bonding), and / or by bonding dies to wafers (e.g., die-to-wafer bonding). A bonding machine can be used to bond semiconductor dies 102 and 104 by forming a metal-to-metal bond and / or a dielectric-to-dielectric bond at a bonding interface 108a between semiconductor dies 102 and 104. A bonding machine can also be used to bond semiconductor dies 104 and 106 by forming a metal-to-metal bond and / or a dielectric-to-dielectric bond at a bonding interface 108b between semiconductor dies 104 and 106.

[0026] Semiconductor die 102 may be an image sensor die of semiconductor die package 100. Semiconductor die package 100 may be configured to generate images and / or video based on sensing performed by semiconductor die 102. Therefore, semiconductor die package 100 may be an image sensor device, such as a CMOS image sensor (CIS). In particular, due to the vertical arrangement of semiconductor dies 102-106, semiconductor die package 100 may be a three-dimensional (3D) CIS.

[0027] like Figure 1 As shown, in other examples, semiconductor die 102 may include a pixel sensor array 110, a black level correction (BLC) region 112 adjacent to (e.g., horizontally adjacent to) the pixel sensor array 110, and a bonding pad region 114 adjacent to (e.g., horizontally adjacent to) the BLC region 112. The pixel sensor array 110 includes a plurality of pixel sensors 116. The pixel sensors 116 may be arranged in a grid or another type of arrangement and may be configured to generate a photocurrent based on photons of incident light. The BLC region 112 may include region 118 in device layer 120, which shields incident light through a metal shielding layer. The metal shielding layer may include a photoresist barrier to prevent incident light from entering region 118. Therefore, region 118 is a sensing region that remains “dark” so that dark current measurements can be performed in the BLC region 112. Dark current measurements can be performed to measure the amount of charge (dark current) in device layer 120 generated from sources other than incident light (e.g., heat from device layer 120), so that the dark current measurements can be used for black level correction (or black level calibration) of pixel sensor array 110. Bonding pad region 114 may include bonding pad structures capable of forming external electrical connections to semiconductor die package 100.

[0028] Device layer 120 includes substrate layer 122. Substrate layer 122 may include silicon (Si) (e.g., a silicon substrate), a silicon layer or another type of semiconductor layer, a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor material.

[0029] The photodiode 124 of the pixel sensor 116 is contained within a substrate layer 122 of the semiconductor die 102. Each photodiode 124 may include one or more doped regions of the substrate layer 122. Corresponding to a photodiode 124, the substrate layer 122 may be doped with various types of ions to form a PN junction or PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) portion, and an n-type portion). For example, the substrate layer 122 may be doped with n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 124 and doped with p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 124. The photodiode 124 may be configured to absorb photons of incident light. The absorption of photons causes the photodiode 124 to accumulate charge (photocurrent) due to the photoelectric effect. Here, photons bombard the photodiode 124, causing the photodiode 124 to emit electrons. The emission of electrons leads to the formation of electron-hole pairs, where electrons migrate towards the cathode of the photodiode 124 and holes migrate towards the anode, generating a photocurrent.

[0030] Photodiodes 124 may be electrically and / or optically isolated from each other through one or more isolation structures in substrate 122. For example, a deep trench isolation (DTI) structure 126 may extend from the back side of substrate 122. DTI structure 126 may include an elongated structure comprising one or more dielectric layers, one or more metal layers, and / or another arrangement of layers and / or materials. DTI structure 126 may laterally surround the photodiodes 124 of pixel sensor 116 in substrate 122.

[0031] A grid structure 128 may be contained on the back side of the substrate layer 122. A portion of the grid structure 128 may be located above the DTI structure 126 and may be formed around the periphery of the photodiode 124 of the pixel sensor 116. Openings in the grid structure 128 are located above the photodiode 124 to allow incident light to pass through the grid structure 128 and reach the photodiode 124. In some embodiments, the grid structure 128 may be formed of a metallic material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof. In some embodiments, the grid structure 128 may be formed of a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y The grid structure 128 may include a plurality of layers, comprising a dielectric layer and a metal layer on a dielectric layer, or another combination of dielectric and metal layers.

[0032] A color filter region 130 of the pixel sensor 116 is contained within an opening in the grid structure 128. The color filter region 130 may be contained above a photodiode 124 of the pixel sensor 116. Each color filter region 130 may be configured to filter incident light to allow a specific wavelength of the incident light to reach the photodiode 124. For example, the color filter region 130 may filter incident light to allow red light to pass through the color filter region 130 to reach the associated photodiode 124. As another example, the color filter region 130 may filter incident light to allow green light to pass through the color filter region 130 to reach the associated photodiode 124. As another example, the color filter region 130 may filter incident light to allow blue light to pass through the color filter region 130 to reach the associated photodiode 124. In some embodiments, the color filter region 130 may be non-discriminatory or non-filtering, which may define a white pixel sensor. The non-discriminating or non-filtering color filter region 130 may include a material that allows all wavelengths of light to enter the associated photodiode 124 (e.g., for the purpose of determining overall brightness to increase the photosensitivity of the image sensor). In some embodiments, the color filter region 130 may be a near-infrared (NIR) bandpass color filter region 130, which may define an NIR pixel sensor. The NIR bandpass color filter region 130 may include a material that allows a portion of incident light in the NIR wavelength range to pass to the associated photodiode 124 while blocking visible light from passing through.

[0033] Microlens 132 may be contained above and / or on the color filter area 130. Microlens 132 may include a corresponding microlens for each pixel sensor 116. Microlenses may be configured to focus incident light onto the photodiode 124 of the associated pixel sensor 116.

[0034] A transfer gate 134 of the pixel sensor 116 is contained on the front side of the substrate layer 122. The transfer gate 134 is configured to selectively allow photocurrent to flow from the photodiode 124 to the floating diffusion node 136 of the pixel sensor 116. The floating diffusion node 136 is contained in the substrate layer 122 and is configured to temporarily store the photocurrent generated by the photodiode 124. The transfer gate 134 can selectively control the flow of photocurrent from the photodiode 124 of the pixel sensor 116 to the floating diffusion node 136 of the pixel sensor 116 by selectively controlling a leakage path (e.g., a buried channel) between the photodiode 124 and the floating diffusion node 136 in the substrate layer 122. When a gate voltage is applied to the transfer gate 134, a leakage path can be formed in the substrate layer 122, allowing photocurrent to flow from the photodiode 124 to the floating diffusion node 136. When the gate voltage is removed, the leakage path is closed, thereby preventing photocurrent from drifting from the photodiode 124 to the floating diffusion node 136.

[0035] Semiconductor die 102 may include an interconnect layer 138 perpendicularly adjacent to device layer 120. Interconnect layer 138 may include dielectric regions 140, each comprising one or more dielectric layers. The dielectric layers may include a rear dielectric layer (e.g., an intermediate layer dielectric (ILD) layer, an intermetallic dielectric (IMD) layer) and an etch stop layer (ESL) disposed in a direction approximately orthogonal to substrate layer 122. Dielectric regions 140 may each comprise various dielectric materials, such as oxides (e.g., silicon oxide (SiOx) and / or another oxide material), undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), extremely low dielectric constant (ELK) dielectric materials having a dielectric constant less than about 2.5, silicon nitride (SiOx), etc. x N y ), silicon carbide (SiC), silicon oxynitride (SiON) and / or another suitable dielectric material.

[0036] The interconnect layer 138 may also include a plurality of conductive structures 142 (e.g., electrically conductive structures) in the dielectric region 140. The conductive structures 142 are electrically coupled and / or physically coupled to the transfer gate 134, the floating diffusion node 136, and / or other structures in the device layer 120. Furthermore, the conductive structures 142 may be electrically connected together in the interconnect layer 138. The conductive structures 142 correspond to circuit wiring capable of providing signals and / or power to the pixel sensor 116 and / or other integrated circuit devices in the device layer 120 and / or from the pixel sensor 116 and / or other integrated circuit devices. The conductive structures 142 may include combinations of conductive structures (e.g., trenches, wires) extending primarily horizontally in the interconnect layer 138 and conductive structures connected via interconnect structures (e.g., vias) extending primarily vertically in the interconnect layer 138. The conductive structure 142 may each include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au) and / or combinations thereof, as well as other examples of electrically conductive materials.

[0037] The conductive interconnects of interconnect layer 138 can be arranged vertically to facilitate the transfer of electrical signals and / or power between device layer 120 and semiconductor die 104, between integrated circuit devices in device layer 120 via interconnect layer 138, and / or between integrated circuit devices in device layer 120 and integrated circuit devices in semiconductor die 104 and / or 106. Conductive structures 142 can be arranged as alternating layers of metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer may include one or more conductive structures arranged laterally in interconnect layer 138, and each via layer may include one or more interconnect structures that interconnect the metallization layers in interconnect layer 138. As an example, a metal O (M0) layer may be located at the bottom of interconnect layer 138 and may be coupled to integrated circuit devices in device layer 120 (e.g., transfer gate 134, floating diffusion node 136). A via 0 (V0) layer may be located above and coupled to the M0 layer in interconnect layer 138, and a metal 1 (M1) layer may be located above and coupled to the V0 layer in interconnect layer 138. A via 1 (V1) layer may be located above and coupled to the M1 layer in interconnect layer 138. A metal 2 (M2) layer may be located above and electrically coupled to the V1 layer in interconnect layer 138, and so on. In some embodiments, interconnect layer 138 includes nine (9) stacked metallization layers (e.g., M0-M8). In other embodiments, a contact layer (referred to as a "CO" layer) may be located at the bottom of interconnect layer 138 and may be directly coupled to an integrated circuit device in device layer 120 (e.g., with transfer gate 134, with floating diffusion node 136), and a metal 1 (M1) layer may be located above and coupled to the CO layer in interconnect layer 138, and so on. In some implementations, interconnect layer 138 includes another number of stacked metallization layers.

[0038] At the bonding interface 108a between semiconductor dies 102 and 104, the interconnect layer 138 may include a plurality of bonding pads 144. The bonding pads 144 may be electrically coupled to the conductive structure 142 in the interconnect layer 138 through bonding vias 146 and / or other types of conductive structures. In other examples of other electrically conductive metals, the bonding pads 144 and bonding vias 146 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof.

[0039] like Figure 1As further shown, one or more capacitor structures 148 may be included in the interconnect layer 138 and electrically coupled to one or more conductive structures 142 in the interconnect layer 138. The one or more capacitor structures 148 may be electrically coupled to one or more pixel sensors 116 through the conductive structures 142 and may be configured to store photocurrent overflowing from the floating diffusion node 136 of the pixel sensor 116 to facilitate increased full-well capacity. This may enable the pixel sensor 116 to achieve a higher dynamic range and / or may enable global shutter functionality within the semiconductor die package 100. Figure 2A and Figure 2B An embodiment of an example structure of capacitor structure 148 is shown and described.

[0040] Semiconductor die 104 may be an ASIC die or a system-on-a-chip (SoC) die of semiconductor die package 100. Semiconductor die 104 may include control circuitry associated with pixel sensor 116 of semiconductor die 102. Semiconductor die 104 may include a device layer 150 and an interconnect layer 152 perpendicular to device layer 150. Device layer 150 may include a substrate layer 154 and one or more integrated circuit devices 156 within substrate layer 154. Substrate layer 154 may include a silicon (Si) substrate and / or other types of semiconductor substrate. Integrated circuit device 156 may correspond to the control circuitry associated with pixel sensor 116 of semiconductor die 102. For example, integrated circuit device 156 may include source follower gates for pixel sensor 116, may include row select gates for pixel sensor 116, may include overflow gates for pixel sensor 116, and / or may include other control circuitry devices for pixel sensor 116. Integrated circuit device 156 may be contained in a first side (e.g., front side) of substrate 154 and may each include planar transistors, fin field-effect transistors (finFETs), nanostructures (e.g., nanosheet transistors, gate-all-around (GAA) transistors) and / or other types of integrated circuit devices.

[0041] Interconnect layer 152 may be perpendicularly adjacent to a first side (e.g., the front side) of substrate layer 154. Interconnect layer 152 may include a combination and / or arrangement of structures and / or layers similar to interconnect layer 138 of semiconductor die 102. For example, interconnect layer 152 may include a combination of dielectric region 158 (similar to dielectric region 140) and conductive structure 160 (similar to conductive structure 142) within dielectric region 158. Furthermore, interconnect layer 152 may include bonding pads 162 electrically coupled to one or more of conductive structures 160 through bonding via 164. These layers and / or structures may have a perpendicular arrangement opposite to semiconductor die 102, allowing semiconductor die 102 and semiconductor die 104 to be bonded at bonding interface 108a, such that interconnect layer 138 and interconnect layer 152 face each other and are bonded together.

[0042] At the bonding interface 108a, the bonding pad 144 of the semiconductor die 102 and the bonding pad 162 of the semiconductor die 104 are directly bonded via metal-to-metal bonding. Furthermore, the dielectric region 140 of the semiconductor die 102 and the dielectric region 158 of the semiconductor die 104 are directly bonded via dielectric-to-dielectric bonding. One or more of the bonding pad 162 and the semiconductor die 104 can be electrically coupled to the conductive structure 160 through the bonding via 164.

[0043] like Figure 1 As further shown, one or more capacitor structures 166 may be included in an interconnect layer 152 above the front side of the substrate layer 154 of the semiconductor die 104. One or more capacitor structures 166 may be electrically coupled to one or more conductive structures 160 in the interconnect layer 152. One or more of the capacitor structures 166 may be electrically coupled to one or more pixel sensors 116 through conductive structures 142, bonding vias 146, bonding pads 144, bonding pads 162, bonding vias 164, and / or conductive structures 160. The capacitor structures 166 may be configured to store photocurrent overflowing from the floating diffusion node 136 or the pixel sensor 116 to facilitate increased full-well capacity. This may enable the pixel sensor 116 to achieve a higher dynamic range and / or may enable global shutter functionality within the semiconductor die package 100. Figure 2A and 2B An example structural implementation of capacitor structure 166 is shown and described.

[0044] like Figure 1As further shown, semiconductor die 104 may include another interconnect layer 168. Interconnect layer 168 may be located on a second side (e.g., the back side) of substrate layer 154, such that interconnect layers 152 and 168 are located on vertically opposite sides of substrate layer 154 of semiconductor die 104. Interconnect layer 168 may be configured to transfer signals and / or power between semiconductor dies 104 and 106. Interconnect layer 168 may include a combination and / or arrangement of structures and / or layers similar to interconnect layer 152 of semiconductor die 104. For example, interconnect layer 168 may include a combination of dielectric region 170 (similar to dielectric region 158) and conductive structure 172 (similar to conductive structure 160) within dielectric region 170.

[0045] The semiconductor die 104 may include one or more elongated conductive structures 174. The elongated conductive structures 174 may extend through the substrate layer 154 of the device layer 150 between interconnect layers 152 and 168. The elongated conductive structures 174 may include another type of vertically elongated conductive structure physically and electrically connected to a first end of a conductive structure 160 (e.g., a metal pad) in the interconnect layer 152, such as a through-substrate via (TSV), metal pillar, metal row, and / or interconnected with the conductive structure 172 (e.g., a metal pad) in the interconnect layer 168. The elongated conductive structure 174 may be referred to as a TSV structure because it extends completely through the substrate layer 154 of the device layer 150 (e.g., a semiconductor substrate, such as a silicon substrate), as opposed to extending completely through a dielectric or insulating layer. The elongated conductive structure 174 may also extend through a shallow trench isolation (STI) region 176 included in the substrate layer 154 of the device layer 150. The elongated conductive structure 174 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material. The STI region 176 may contain one or more dielectric materials, such as silicon oxide (SiO2). x For example, SiO2), silicon nitride materials (Si x N y (e.g., Si3N4) and / or another suitable dielectric material.

[0046] One or more substrates 178 may be included between the sidewalls of the elongated conductive structure 174 and the substrate layer 154. The one or more substrates 178 may include an adhesive substrate, a barrier substrate, a diffusion substrate, and / or another type of substrate. In some embodiments, the substrate 178 includes a high-dielectric-constant dielectric substrate comprising a high-dielectric-constant dielectric material having a dielectric constant greater than about 3.9. Examples of this material include silicon nitride (Si3N4, e.g., Si...). x N y ), aluminum oxide (Al) x O y For example, Al2O3), tantalum oxide (Ta x O y For example, Ta2O5), titanium dioxide (TiO2) x For example, TiO2), zirconium oxide (ZrO2) x For example, ZrO2), hafnium oxide (HfO) x For example, HfO2), strontium titanium oxide (SrTiO2), etc. x For example, SrTiO3), hafnium oxide (HfSiO3), etc. x For example, HfSiO4), lanthanum oxide (La x O y For example, La2O3), yttrium oxide (Y) x O y (e.g., Y₂O₃) and / or amorphous lanthanum alumina (a-LaAlO₂) x Examples include α-La₂O₃. In some embodiments, the liner 178 comprises a low-dielectric-constant dielectric liner, which includes a low-dielectric-constant dielectric material. Examples of such materials include silicon oxide (SiO₂). x Undoped silicate glass (USG), borosilicate glass (BSG), and / or fluorinated silicate glass (FSG), etc.

[0047] like Figure 1As further shown, one or more capacitor structures 180 may be included in an interconnect layer 168 above (or below, depending on the orientation of) the back side of the substrate layer 154 of the semiconductor die 104. One or more capacitor structures 180 may be electrically coupled to one or more conductive structures 172 in the interconnect layer 168. One or more of the capacitor structures 180 may be electrically coupled to one or more pixel sensors 116 through conductive structures 142, bonding vias 146, bonding pads 144, bonding pads 162, bonding vias 164, conductive structures 160, elongated conductive structures 174, and / or conductive structures 172. The capacitor structures 180 may be configured to store photocurrent overflowing from the floating diffusion node 136 or the pixel sensor 116 to facilitate increased full-well capacity. This may enable the pixel sensor 116 to achieve a higher dynamic range and / or may enable global shutter functionality within the semiconductor die package 100. Figure 2A and 2B An example structural implementation of capacitor structure 180 is shown and described.

[0048] In this manner, capacitor structures are incorporated within multiple dies of the semiconductor die package 100 and multiple sides of the substrate layer 154 of the semiconductor die 104. Incorporating capacitor structures on both sides of the substrate layer 154 of the semiconductor die 104 allows for the inclusion of more capacitor structures on the semiconductor die 104, enabling capacitor structures to be moved from the semiconductor die 102 to the semiconductor die 104, thus reducing the number of capacitor structures on the semiconductor die 102. This allows a larger portion of the die area of ​​the semiconductor die 102 to be used alternatively for the related structures of the photodiode 124 and the pixel sensor 116, which can increase the density of pixel sensors 116 in the pixel sensor array 110, while simultaneously allowing a larger number of capacitor structures to be incorporated into the pixel sensors 116.

[0049] The interconnect layer 168 may also include bonding pads 182 and bonding vias 184. The bonding pads 182 enable the semiconductor die 104 to be bonded to the semiconductor die 106 at the bonding interface 108b, and the bonding vias 184 electrically connect one or more of the bonding pads 182 to the conductive structure 172 in the interconnect layer 168.

[0050] Semiconductor die 106 may be an image sensor processing (ISP) die of semiconductor die package 100. Semiconductor die 106 may include processing circuitry associated with pixel sensor array 110, configured to perform image processing operations to generate images and / or video based on photocurrents generated by pixel sensors 116 in pixel sensor array 110. Additionally and / or alternatively, the processing circuitry in semiconductor die 106 may be configured to perform functions such as compression, storage, file management, and / or other functions associated with images and / or video.

[0051] Semiconductor die 106 may include a device layer 186 and an interconnect layer 188 perpendicular to the device layer 186. Device layer 186 may include a substrate layer 190 and one or more integrated circuit devices 192 in the substrate layer 190. Substrate layer 190 may include a silicon (Si) substrate and / or other types of semiconductor substrates. Integrated circuit devices 192 may correspond to image processing circuitry of semiconductor die 106 and may include transistors, capacitors, resistors and / or other integrated circuit devices.

[0052] Interconnect layer 188 may be perpendicularly adjacent to the front side of substrate layer 190. Interconnect layer 188 may include a combination and / or arrangement of structures and / or layers similar to interconnect layer 168 of semiconductor die 104. For example, interconnect layer 188 may include a combination of dielectric region 194 (similar to dielectric region 170) and conductive structure 196 (similar to conductive structure 172) in dielectric region 194. In addition, interconnect layer 168 may include bonding pads 198 electrically coupled to one or more of conductive structures 196. These layers and / or structures may have a perpendicular arrangement opposite to interconnect layer 168, which allows semiconductor die 104 and semiconductor die 106 to be bonded at bonding interface 108b, such that interconnect layer 168 and interconnect layer 188 face each other and are bonded together.

[0053] At the bonding interface 108b, the bonding pad 182 of the semiconductor die 104 and the bonding pad 198 of the semiconductor die 106 are directly bonded via metal-to-metal bonding. Furthermore, the dielectric region 170 of the semiconductor die 104 and the dielectric region 194 of the semiconductor die 106 are directly bonded via dielectric-to-dielectric bonding.

[0054] As mentioned above, Figure 1 This is provided as an example. Other examples may be similar. Figure 1 The differences described in [the text].

[0055] Figure 2A and 2B This is a schematic diagram of the example capacitor structure described in this article. (Combined with...) Figure 1 One or more of the described capacitor structures 148, 166 and / or 180 can be implemented as Figure 2A and / or Figure 2B One or more of the example capacitor structures shown. Additionally and / or alternatively, one or more other capacitor structures described herein, such as capacitor structure 710 and / or combinations thereof, are also described. Figure 7A-7K The capacitor structure 710 shown and described can be implemented as follows: Figure 2A and / or Figure 2A One or more of the example capacitor structures shown are illustrated.

[0056] like Figure 2A As shown, the example capacitor structure 200 extends into a trench 202 formed in layer 204. Therefore, the capacitor structure 200 can be referred to as a trench capacitor structure. In some embodiments, layer 204 is a dielectric layer and may correspond to dielectric regions 140, 158, and / or 170, etc. In some embodiments, layer 204 is a semiconductor layer and may correspond to the substrate layer 154 of a semiconductor die 104.

[0057] In some embodiments, the trench 202 may have a high aspect ratio, which is the ratio of the vertical depth to the lateral width of the trench 202. In these embodiments, the capacitor structure 200 may be referred to as a deep trench capacitor (DTC) structure. In some embodiments, the aspect ratio of the trench 202 may be approximately 10:1 or greater. In some embodiments, the trench 202 may have an aspect ratio ranging from approximately 20:1 to approximately 50:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0058] As further shown in FIG2, the capacitor structure 200 may include one or more first electrode layers 206 (e.g., the bottom electrode layer or capacitor bottom metal (CBM) layer of the capacitor structure 200), one or more second electrode layers 208 (e.g., the top electrode layer or capacitor top metal (CTM) layer of the capacitor structure 200), and one or more insulating layers 210. The first electrode layer 206, the second electrode layer 208, and the insulating layer 210 are arranged in a metal-insulator-metal (MIM) stack in the capacitor structure 200. In some embodiments, the MIM stack includes a repeated arrangement of the first electrode layer 206, the insulating layer 210 on the first electrode layer 206, and the second electrode layer 208 on the insulating layer 210. For example, the first electrode layer 206a can be located on the sidewall and bottom of the ditch 202, the insulating layer 210a can be on the first electrode layer 206a, the second electrode layer 208a can be located on the insulating layer 210a, another insulating layer 210b can be located on the second electrode layer 208a, another first electrode layer 206c can be located on the insulating layer 210b, another insulating layer 210c can be located on the first electrode layer 206b, and another second electrode layer 208b can be located on the insulating layer 210c. Figure 2A The number of first electrode layers 206, second electrode layers 208, and insulating layers 210 shown is just an example; other numbers are within the scope of this invention.

[0059] The first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may each include a conformal layer that conforms to the contour or trench 202. In other words, the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may each extend along the sidewall of the trench 202 and along the bottom surface of the trench 202. The remaining area in the trench 202 may be filled with the dielectric layer 212.

[0060] The first electrode layer 206 and the second electrode layer 208 may include one or more electrically conductive materials, such as molybdenum (Mo), chromium (Cr), titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), aluminum (Al), gold (Au), silver (Ag), cobalt (Co), copper (Cu), ruthenium (Ru), platinum (Pt), and / or other suitable electrically conductive materials. The insulating layer 210 may include one or more low-dielectric-constant dielectric materials, one or more high-dielectric-constant dielectric materials, and / or another type of electrically insulating material. Examples include zirconium oxide (ZrO). x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), silicon nitride (Si) x N y For example, Si3N4), yttrium oxide (Y)x O y For example, Y2O3), lanthanum oxide (La x O y (e.g., La2O3) and / or europium oxide (HfO) x For example, HfO2), etc. In some embodiments, each of the insulating layers 210 comprises a multilayer stack, which includes multiple dielectric layers. For example, the insulating layer 210 may include a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0061] like Figure 2A As further shown, the first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may extend over the trench 202 and laterally outward from the trench. A portion of the first electrode layer 206 extending laterally outward from the trench 202 along the surface of layer 204 may be electrically connected and / or physically connected to one or more first contact structures 214 (e.g., CBM contacts). A portion of the second electrode layer 208 extending laterally outward from the trench 202 along the surface of layer 204 may be electrically connected and / or physically connected to one or more second contact structures 216 (e.g., CTM contacts). The first contact structures 214 and / or the second contact structures 216 may correspond to conductive structures 142, 160, 172, and / or other conductive structures in the semiconductor die package 100.

[0062] Figure 2B Another example capacitor structure 218 is shown. (e.g.) Figure 2B As shown, capacitor structure 218 includes a first electrode layer 206, a second electrode layer 208, and an insulating layer 210 between the first electrode layer 206 and the second electrode layer 208. The first electrode layer 206, the second electrode layer 208, and the insulating layer 210 may be configured as a planar thin film stack in layer 204. Therefore, in other examples, capacitor structure 218 may be referred to as a planar capacitor, a parallel-plate capacitor, and / or a thin-film capacitor.

[0063] The capacitor structure 218 may also include one or more capping layers that facilitate the etching of the first electrode layer 206, the second electrode layer 208, and / or the insulating layer 210, and / or provide electrical isolation for the capacitor structure 218. For example, the capacitor structure 218 may include a capping layer 220 on the second electrode layer 208. In some embodiments, the capping layer 220 serves as a hard mask to pattern and define the second electrode layer 208. As another example, the capacitor structure 218 may include capping layers 222 and 224. Parts of capping layers 222 and 224 may be included over the insulating layer 210, and parts of capping layers 222 and 224 may be included over capping layer 220.

[0064] The first contact structure 214 can land on the first electrode layer 206 and can extend through the insulating layer 210, the top cover layers 222 and 224. The second contact structure 216 can land on the second electrode layer 208 and can extend through the top cover layers 222 and 224.

[0065] As mentioned above, providing Figure 2A and 2B As an example. Other examples can be found related to... Figure 2A and 2B The descriptions are different.

[0066] Figures 3A-3E This is a schematic diagram of an exemplary embodiment 300 forming the semiconductor die 102 (or a portion thereof) described herein. In some embodiments, combined with Figures 3A-3E One or more of the described semiconductor processing operations can be performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, electroplating equipment, ion implantation equipment and / or wafer / die transport equipment.

[0067] Turn Figure 3A The substrate layer 122 of the device layer 120 of the semiconductor die 102 is provided. The substrate layer 122 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, which may be provided as an SOI wafer and / or another type of semiconductor workpiece.

[0068] like Figure 3B As shown, the photodiode 124 of the pixel sensor 116 of the pixel sensor array 110 of the semiconductor die 102 can be formed in the substrate 122 from the front side of the substrate 122. In some embodiments, ions can be implanted into the substrate 122 using an ion implantation apparatus to form a PN junction between the p-doped region and the n-doped region of the substrate 122, or a PIN junction between the p-doped region of the substrate 122, the n-doped region of the substrate 122, and the intrinsic (e.g., undoped) semiconductor region of the photodiode 124.

[0069] like Figure 3B As further shown, additional regions of the substrate 122 may be doped to form floating diffusion nodes 136. The transfer gate 134 of the pixel sensor 116 may be formed above and / or on the front surface of the substrate 122. Forming the transfer gate 134 may include depositing a gate dielectric layer on the front surface of the substrate 122, depositing a gate electrode on the gate dielectric layer, and / or forming sidewall spacers on the sidewalls of the gate electrode, etc.

[0070] like Figure 3CIn this semiconductor die 102, a portion of the dielectric region 140 of the interconnect layer 138 may be formed above the front side of the substrate layer 122. A deposition apparatus may be used to deposit said portion of the dielectric region 140 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or another suitable deposition technique. The said portion of the dielectric region 140 may be deposited in one or more deposition operations. In some embodiments, a planarization apparatus is used to perform a planarization operation (e.g., chemical mechanical planarization (CMP)) to planarize said portion of the dielectric region 140 after deposition.

[0071] Gate contact 302 and source / drain contact 304 can be formed in dielectric region 140. For example, gate contact 302 can be formed on transfer gate 134 of pixel sensor 116, while source / drain contact 304 can be formed on floating diffusion node 136 of pixel sensor 116. To form gate contact 302 and source / drain contact 304, a groove can be formed in dielectric region 140, and gate contact 302 and source / drain contact 304 can be formed in the groove in dielectric region 140. Deposition equipment can be used to deposit gate contact 302 and source / drain contact 304 using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. Gate contact 302 and source / drain contact 304 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and gate contact 302 and source / drain contact 304 are deposited on the seed layer. In some embodiments, one or more substrates (e.g., adhesion substrates, barrier substrates, diffusion substrates) are deposited, and then gate contacts 302 and source / drain contacts 304 are deposited on the substrates. In some embodiments, after depositing gate contacts 302 and source / drain contacts 304, a planarization operation (e.g., CMP operation) is performed using a planarization apparatus to planarize the gate contacts 302 and source / drain contacts 304.

[0072] like Figure 3DAs shown, an additional portion of the interconnect layer 138 of the semiconductor die 102 can be formed above the front side of the substrate layer 122. The interconnect layer 138 can be formed using one or more semiconductor processing equipment by forming one or more dielectric layers of the dielectric region 140 and forming a plurality of conductive structures 142 in the dielectric layer of the dielectric region 140. For example, a deposition equipment can be used to deposit a first dielectric layer of the dielectric region 140 (e.g., using CVD, ALD, PVD, oxidation, and / or another type of deposition technique), an etching equipment can be used to remove a portion of the first dielectric layer to form a trench in the first dielectric layer, and a deposition equipment can be used to form a first layer (e.g., via layer, metallization layer) of one or more conductive structures 142 in the trench (e.g., using CVD, ALD, PVD, electroplating, and / or other types of deposition techniques). At least a portion of the first layer of conductive structure 142 may be electrically and / or physically connected (e.g., directly connected or connected through contacts 302 and / or 304) to transfer gate 134 and / or floating diffusion node 136. Similar processing operations may be performed to form additional layers of interconnect layer 138 until a sufficient or desired arrangement of conductive structure 142 is achieved.

[0073] Further as Figure 3D As shown, one or more capacitor structures 148 may be formed above the front side of the substrate layer 122 in the interconnect layer 138. For example, according to Figure 2A The capacitor structure 148 is formed by arranging the capacitor structure 200 (e.g., a trench capacitor structure) as shown. In these examples, a trench 202 may be formed in the dielectric region 140. One or more first electrode layers 206, one or more second electrode layers 208, and one or more insulating layers 210 may be alternately formed in the trench 202. A first contact structure 214 may be formed on the first electrode layer 206, and a second contact structure 216 may be formed on the second electrode layer 208. In another example, the capacitor structure 148 may be configured according to... Figure 2B The capacitor structure 218 shown is formed according to the structural arrangement of a thin-film capacitor structure. In these examples, a first electrode layer 206 is formed, an insulating layer 210 is formed on the first electrode layer 206, and a second electrode layer 208 is formed on the insulating layer 210. Top cap layers 220-224 may be formed, and a first contact structure 214 and a second contact structure 216 may be formed on the first electrode layer 206 and the second electrode layer 208, respectively.

[0074] like Figure 3E As shown, the bonding via 146 may be formed on one or more conductive structures 142 in the interconnect layer 138, and the bonding pad 144 may be formed on or on the bonding via 146.

[0075] As mentioned above, providing Figures 3A-3E As an example. Other examples can be found related to... Figures 3A-3E The descriptions are different.

[0076] Figures 4A-4D This is a schematic diagram of an exemplary embodiment 400 forming the semiconductor die 104 (or a portion thereof) described herein. In some embodiments, exemplary embodiment 400 includes an exemplary front-side process for the semiconductor die 104. In some embodiments, one or more semiconductor processing equipment may be used to perform one or more of the operations described in conjunction with exemplary embodiment 400, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, electroplating equipment, and / or other types of semiconductor processing equipment.

[0077] Turn Figure 4A One or more of the operations in Example Implementation 400 may be performed in conjunction with substrate layer 154, device layer 150, or semiconductor die 104. Substrate layer 154 may be provided in the form of a semiconductor wafer (e.g., a silicon wafer), an SOI wafer, or another type of semiconductor substrate.

[0078] like Figure 4B As shown, an integrated circuit device 156 may be formed in and / or on the front side of a substrate layer 154 of a device layer 150. One or more semiconductor processing stations may be used to form one or more portions of the integrated circuit device 156. For example, a deposition station may be used to perform various deposition operations to deposit the layers of the integrated circuit device 156 and / or deposit a photoresist layer for etching the substrate layer 154 and / or portions of the deposited layers. As another example, an exposure station may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a developing station may be used to develop the pattern in the photoresist layer. As another example, an etching station may be used to etch the substrate layer 154 and / or portions of the deposited layers to form the integrated circuit device 156. As another example, a planarization station may be used to planarize portions of the integrated circuit device 156. As another example, an ion implantation station may be used to dope the substrate layer 154 with implanted ions, doping portions of the substrate layer 154 with one or more types of dopants (e.g., p-type dopants, n-type dopants).

[0079] like Figure 4BAs further shown, STI region 176 can be formed on the front side of substrate layer 154. STI region 176 can be formed in a groove in substrate layer 154. In some embodiments, a pattern in the photoresist layer can be used to etch substrate layer 154 to form grooves in substrate layer 154. In these embodiments, a deposition equipment can be used to form a photoresist layer on substrate layer 154. An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development equipment can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching equipment can be used to etch substrate layer 154 on a pattern-based basis to form grooves. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal equipment can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative etching technique to etch substrate layer 154 on a pattern-based basis.

[0080] The deposition equipment can be used to deposit dielectric material of the STI region 176 in the trench using CVD, ALD, PVD, oxidation, and / or another suitable deposition technique. The dielectric material of the STI region 176 can be deposited through one or more deposition operations. In some embodiments, after depositing the dielectric material of the STI region 176, a planarization operation (e.g., CMP operation) can be performed on the STI region 176 to planarize it.

[0081] like Figure 4C As shown, the interconnect layer 152 of the semiconductor die 104 can be formed above the front side of the substrate layer 154 of the semiconductor die 104. One or more semiconductor processing equipment can be used to form the interconnect layer 152 by passing through one or more dielectric layers in the dielectric regions 158 forming the dielectric region 158 and forming a plurality of conductive structures 160 in the dielectric layer of the dielectric region 158. For example, a deposition equipment can be used to deposit a first dielectric layer or dielectric region 158 (e.g., using CVD, ALD, PVD, oxidation, and / or another type of deposition technique), an etching equipment can be used to remove portions of the first dielectric layer to form trenches in the first dielectric layer, and a deposition equipment can be used to form a first layer (e.g., via layer, metallization layer) of one or more conductive structures 160 in the trenches (e.g., using CVD, ALD, PVD, electroplating, and / or other types of deposition techniques). At least a portion of the first layer of conductive structure 160 may be electrically and / or physically connected (e.g., directly connected or connected through contacts) to integrated circuit device 156 in substrate layer 154. Similar processing operations may be performed to form additional layers of interconnect layer 152 until a sufficient or desired arrangement of conductive structure 160 is achieved.

[0082] like Figure 4C As further shown, one or more capacitor structures 166 may be formed above the front side of the substrate layer 154 of the interconnect layer 152. For example, it can be based on... Figure 2A The capacitor structure 166 is formed by the structural arrangement of the capacitor structure 200 shown (e.g., a trench capacitor structure). In these examples, a trench 202 may be formed in the dielectric region 158. One or more first electrode layers 206, one or more second electrode layers 208, and one or more insulating layers 210 may be alternately formed in the trench 202. A first contact structure 214 may be formed on the first electrode layer 206, and a second contact structure 216 may be formed on the second electrode layer 208. In another example, the capacitor structure 166 may be configured according to... Figure 2B The capacitor structure 218 shown is formed according to the structural arrangement of a thin-film capacitor structure. In these examples, a first electrode layer 206 is formed, an insulating layer 210 is formed on the first electrode layer 206, and a second electrode layer 208 is formed on the insulating layer 210. Top cap layers 220-224 may be formed, and a first contact structure 214 and a second contact structure 216 may be formed on the first electrode layer 206 and the second electrode layer 208, respectively.

[0083] like Figure 4D As shown, a bonding via 164 may be formed on one or more conductive structures 160 in the interconnect layer 152, and a bonding pad 162 may be formed above and / or on the bonding via 164.

[0084] As mentioned above, providing Figures 4A-4D As an example. Other examples can be found related to... Figures 4A-4D The descriptions are different.

[0085] Figures 5A-5D This is a schematic diagram of an exemplary embodiment 500 forming the semiconductor die package 100 (or a portion thereof) described herein. For example, exemplary embodiment 500 may include bonding semiconductor dies 102 and 104 of the semiconductor die package 100, and performing a back-side processing on semiconductor die 104 after bonding. In some embodiments, one or more semiconductor processing equipment may be used to perform one or more of the operations described in exemplary embodiment 500, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, bonding equipment, and / or other types of semiconductor processing equipment.

[0086] like Figure 5AAs shown, a bonding operation is performed to bond semiconductor dies 102 and 104 at bonding interface 108a, such that semiconductor dies 102 and 104 are vertically aligned or stacked within semiconductor die package 100. Semiconductor dies 102 and 104 can be vertically aligned or stacked in a wafer-on-wafer (WoW) architecture, die-on-wafer architecture, die-on-die architecture, and / or another direct bonding architecture. A bonding machine can be used to perform the bonding operation to bond semiconductor dies 102 and 104 at bonding interface 108a. The bonding operation may include a direct physical connection between semiconductor dies 102 and 104 through bonding pads 144 of semiconductor die 102 and bonding pads 162 of semiconductor die 104, and a direct physical connection between dielectric regions 140 of semiconductor die 102 and dielectric regions 158 of semiconductor die 104, forming a direct bond between semiconductor dies 102 and 104. Thus, the interconnect layer 138 on the front side of semiconductor die 102 and the interconnect layer 152 on the front side of semiconductor die 104 are opposite to each other in the semiconductor die package 100.

[0087] like Figure 5B As shown, after semiconductor dies 102 and 104 are bonded at bonding interface 108a, a back-side processing can be performed on the back side of semiconductor die 104. The back-side processing may include forming one or more elongated conductive structures 174 (e.g., one or more TSVs) through the substrate layer 154 of semiconductor die 104, such that the one or more elongated conductive structures 174 land on one or more conductive structures 160 in the interconnect layer 152 on the front side of semiconductor die 104.

[0088] To form an elongated conductive structure 174, a groove can be formed from the back side or through the substrate 154. The groove can extend through the STI region 176 in the substrate 154 and into the dielectric region 158 in the interconnect layer 152. The conductive structure 160 in the interconnect layer 152 can be exposed through the groove.

[0089] In some embodiments, the pattern in the photoresist layer is used to etch the substrate layer 154, STI region 176, and / or dielectric region 158 to form a trench. In these embodiments, a deposition equipment can be used to form the photoresist layer (e.g., using spin coating and / or another suitable deposition technique). An exposure equipment can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing equipment can be used to develop and remove a portion of the photoresist layer to expose the pattern. An etching equipment can be used to etch the substrate layer 154, STI region 176, and / or dielectric region 158 based on the pattern to form a trench. In some embodiments, the etching operation includes dry etching operations (e.g., plasma etching operations, gas etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal equipment can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based trench formation.

[0090] Deposition equipment can be used to deposit material for elongated conductive structures 174 in a trench using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The elongated conductive structures 174 can be deposited through one or more deposition operations. In some embodiments, a seed layer is deposited first, and then the elongated conductive structures 174 are deposited on the seed layer. In some embodiments, one or more substrates 178 (e.g., adhesive substrates, barrier substrates, diffusion substrates) are deposited on the trench, and then the elongated conductive structures 174 are deposited on the substrates 178. In some embodiments, after depositing the elongated conductive structures 174, a planarization equipment is used to perform a planarization operation (e.g., a CMP operation) to planarize the elongated conductive structures 174.

[0091] like Figure 5CAs shown, the interconnect layer 168 of the semiconductor die 104 can be formed on the back side of the substrate layer 154 of the semiconductor die 104. The interconnect layer 168 can be formed using one or more semiconductor processing equipment through one or more dielectric layers in the dielectric region 170 forming the interconnect layer 168 and forming a plurality of conductive structures 172 in the dielectric layer of the dielectric region 170. For example, a deposition equipment can be used to deposit a first dielectric layer or dielectric region 170 (e.g., using CVD, ALD, PVD, oxidation, and / or another type of deposition technique), an etching equipment can be used to remove portions of the first dielectric layer to form trenches in the first dielectric layer, and a deposition equipment can be used to form a first layer (e.g., via layer, metallization layer) of one or more conductive structures 172 in the trenches (e.g., using CVD, ALD, PVD, electroplating, and / or other types of deposition techniques). At least a portion of the first layer or conductive structure 172 can be electrically and / or physically connected to an elongated conductive structure 174. Similar processing operations can be performed to form additional layers of interconnect 168 until a sufficient or desired arrangement of conductive structure 172 is achieved.

[0092] like Figure 5C As further shown, one or more capacitor structures 180 may be formed on the back side of the substrate layer 154 in the interconnect layer 168. For example, it can be based on... Figure 2A The capacitor structure 180 is formed by arranging the capacitor structure 200 (e.g., a trench capacitor structure) as shown. In these examples, a trench 202 may be formed in the dielectric region 170. One or more first electrode layers 206, one or more second electrode layers 208, and one or more insulating layers 210 may be alternately formed in the trench 202. A first contact structure 214 may be formed on the first electrode layer 206, and a second contact structure 216 may be formed on the second electrode layer 208. In another example, the capacitor structure 180 may be configured according to... Figure 2B The capacitor structure 218 shown is formed according to the structural arrangement of a thin-film capacitor structure. In these examples, a first electrode layer 206 is formed, an insulating layer 210 is formed on the first electrode layer 206, and a second electrode layer 208 is formed on the insulating layer 210. Top cap layers 220-224 may be formed, and a first contact structure 214 and a second contact structure 216 may be formed on the first electrode layer 206 and the second electrode layer 208, respectively.

[0093] like Figure 5D As shown, the bonding via 184 may be formed on one or more conductive structures 172 in the interconnect layer 168, and the bonding pad 182 may be formed on or on the bonding via 184.

[0094] As mentioned above, providing Figures 5A-5D As an example. Other examples can be found related to... Figures 5A-5D The descriptions are different.

[0095] Figure 6A and 6B This is a diagram of an exemplary embodiment 600 that forms the semiconductor die package 100 (or a portion thereof) described herein. For example, exemplary embodiment 600 may include an example of bonding semiconductor dies 104 and 106 of the semiconductor die package 100 and performing a back-side processing on semiconductor die 102 after bonding. In some embodiments, one or more semiconductor processing equipment may be used to perform one or more of the operations described in exemplary embodiment 600, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, bonding equipment, and / or other types of semiconductor processing equipment.

[0096] like Figure 6A As shown, a bonding operation is performed to bond semiconductor dies 104 and 106 at bonding interface 108b, such that semiconductor dies 104 and 106 are vertically arranged or stacked in semiconductor die package 100. Semiconductor dies 104 and 106 can be vertically arranged or stacked in the following ways: WoW architecture, die-on-wafer architecture, die-on-die architecture, and / or another direct bonding architecture. A bonding machine can be used to perform the bonding operation to bond semiconductor dies 104 and 106 at bonding interface 108b. The bonding operation may include a direct physical connection through bonding pad 182 of semiconductor die 104 to bonding pad 198 of semiconductor die 106 and a direct physical connection through dielectric region 170 of semiconductor die 104 to dielectric region 194 of semiconductor die 106 to form a direct bond between semiconductor dies 104 and 106. Thus, the interconnect layer 168 on the back side of semiconductor die 104 and the interconnect layer 188 on the front side of semiconductor die 106 are opposite to each other in semiconductor die package 100.

[0097] Semiconductor die 106 can be formed by similar operations and / or using similar techniques, such as combining Figures 4A-4D As described for semiconductor die 104.

[0098] like Figure 6BAs shown, after bonding semiconductor dies 104 and 106 at bonding interface 108b, back-side processing can be performed on the back side of semiconductor die 102. Back-side processing may include additional processing to form pixel array 110, BLC region 112, and / or bonding pad region 114. For example, a DTI structure 126 may be formed in the back side of substrate 122 such that the DTI structure 126 laterally surrounds photodiode 124 of pixel sensor 116. As another example, a grid structure 128 may be formed above the back side of substrate 122, a color filter region 130 may be formed above photodiode 124 above the back side of substrate 122, and a microlens 132 may be formed above color filter region 130. As another example, a metal shielding layer may be formed over region 118 in BLC region 112. As another example, a bonding pad structure may be formed in bonding pad region 114.

[0099] As mentioned above, providing Figure 6A and Figure 6B As an example. Other examples can be found related to... Figure 6A and 6B The descriptions are different.

[0100] Figure 7A-7K This is a schematic diagram of a semiconductor die package 100 according to the exemplary embodiment described herein. Figure 7A-7K The example implementation shown includes Figure 1 Alternative arrangements of the example implementation shown.

[0101] Figure 7A An example embodiment 700 is shown, wherein the substrate layer 154 of the semiconductor die 104 includes an SOI substrate. In example embodiment 700, the substrate layer 154 includes a semiconductor layer 702 corresponding to the back side of the substrate layer 154 (e.g., the back side of the SOI substrate), an insulating layer 704 (e.g., a buried oxide (BOX) layer of the SOI substrate), and a semiconductor layer 706 corresponding to the front side of the substrate layer 154 (the front side of the SOI substrate).

[0102] Semiconductor layer 702, insulating layer 704, and semiconductor layer 706 are stacked and vertically arranged in semiconductor die 104. Semiconductor layer 702 is perpendicularly adjacent to interconnect layer 168 on a first side and perpendicularly adjacent to insulating layer 704 on a second opposite side. Insulator layer 704 is vertically located between semiconductor layer 702 and semiconductor layer 706. Semiconductor layer 706 is perpendicularly adjacent to interconnect layer 152 on a first side and perpendicularly adjacent to insulating layer 704 on a second opposite side.

[0103] Semiconductor layers 702 and 706 may each comprise a semiconductor material, such as silicon (Si), silicon doped with one or more types of dopants (e.g., p-type dopants, n-type dopants), germanium (Ge), silicon-germanium (SiGe), and / or another type of semiconductor material. Insulating layer 704 may comprise one or more dielectric materials, such as silicon oxide (SiO2). x For example, SiO2), silicon nitride materials (Si x N y (e.g., Si3N4) and / or another suitable dielectric material.

[0104] In Example Embodiment 700, the SOI substrate arrangement of substrate layer 154 can add electrical isolation between the front and back sides of substrate layer 154. Therefore, the SOI substrate arrangement of substrate layer 154 in Example Embodiment 700 can add electrical isolation between integrated circuit device 156 (which may be included in semiconductor layer 706) and capacitor structure 180 included in interconnect layer 168. In particular, insulating layer 704 can prevent leakage current from capacitor structure 180 and other devices on the back side of substrate layer 154 from interfering with the operation of integrated circuit device 156 in semiconductor layer 706.

[0105] Figure 7B An example embodiment 708 of the semiconductor die package 100 is shown, which is similar. Figure 1 The example embodiment is shown. However, in the example embodiment 708 of the semiconductor die package 100, the capacitor structure 180 in the interconnect layer 168 of the semiconductor die 104 is omitted, and one or more capacitor structures 710 are instead included in the back side, substrate layer 154, and semiconductor die 104. Therefore, the integrated circuit device 156 is included in the front side of the substrate layer 154, and the capacitor structure 710 is included in the back side of the substrate layer 154. One or more capacitor structures 710 may be structurally implemented as capacitor structure 200, capacitor structure 218, and / or arranged in another structure.

[0106] Figure 7C An example embodiment 712 of the semiconductor die package 100 is shown, which is similar. Figure 7B Example embodiment 708 is shown. However, in example embodiment 712, the substrate layer 154 of the semiconductor die 104 includes an SOI substrate, which includes a semiconductor layer 702, an insulating layer 704, and a semiconductor layer 706. The integrated circuit device 156 on the front side of the substrate layer 154 may be included in the semiconductor layer 706, and the capacitor structure 710 included on the back side of the substrate layer 154 may be included in the semiconductor layer 702. Therefore, the insulating layer 704 is vertically included between the integrated circuit device 156 and the capacitor structure 710.

[0107] In Example Embodiment 712, the SOI substrate arrangement of substrate 154 can provide increased electrical isolation between the front and back sides of substrate 154. Therefore, the SOI substrate arrangement of substrate 154 in Example Embodiment 712 can provide increased electrical isolation between the integrated circuit device 156 and the capacitor structure 710 included in substrate 154. Specifically, the insulating layer 704 can prevent current leakage from the capacitor structure 710 through substrate 154 from interfering with the operation of the integrated circuit device 156 in semiconductor layer 706.

[0108] Figure 7D An example embodiment 714 of the semiconductor die package 100 is shown, which is similar. Figure 1 The example embodiment is shown. However, in example embodiment 714 of the semiconductor die package 100, in addition to the capacitor structure 180 being included in the interconnect layer 168 of the semiconductor die 104, one or more capacitor structures 710 are also included in the back side of the substrate layer 154 of the semiconductor die 104. Including capacitor structures 180 and 710 on the back side of the semiconductor die 104 can further increase the capacitor density of the semiconductor die 104, and / or can enable fewer capacitor structures 148 to be included in the semiconductor die 102.

[0109] Figure 7E An example embodiment 716 of the semiconductor die package 100 is shown, which is similar. Figure 7D Example embodiment 714 is shown. However, in example embodiment 716, the substrate layer 154 of the semiconductor die 104 includes an SOI substrate, which includes a semiconductor layer 702, an insulating layer 704, and a semiconductor layer 706. The integrated circuit device 156 on the front side of the substrate layer 154 may be included in the semiconductor layer 706, and the capacitor structure 710 included on the back side or in the substrate layer 154 may be included in the semiconductor layer 702. Therefore, the insulating layer 704 is vertically included between the integrated circuit device 156 and the capacitor structure 710.

[0110] The SOI substrate arrangement of substrate 154 in Example Embodiment 712 can add electrical isolation between the front and back sides of substrate 154. Therefore, the SOI substrate arrangement of substrate 154 in Example Embodiment 712 can add electrical isolation between integrated circuit device 156 and capacitor structures 180 and 710 included on and / or above the back side of substrate 154.

[0111] Figure 7F An example embodiment 718 of the semiconductor die package 100 is shown, which is similar. Figure 7BExample embodiment 708 is shown. However, in example embodiment 718 of the semiconductor die package 100, one or more capacitor structures 720 are included on the front side of the substrate layer 154 of the semiconductor die 104. Therefore, the integrated circuit device 156 and the capacitor structure 720 are included on the front side of the substrate layer 154, and the capacitor structure 710 is included on the back side of the substrate layer 154. One or more capacitor structures 720 may be structurally implemented as capacitor structure 200, capacitor structure 218, and / or arranged in another structure. Including capacitor structure 166 and capacitor structure 720 on the front side of the semiconductor die 104 can further increase the capacitor density in the semiconductor die 104, and / or can enable the inclusion of fewer capacitor structures 148 in the semiconductor die 102.

[0112] Figure 7G An example embodiment 722 of the semiconductor die package 100 is shown, which is similar. Figure 7F Example embodiment 718 is shown. However, in example embodiment 722, the substrate layer 154 of the semiconductor die 104 includes an SOI substrate, which includes a semiconductor layer 702, an insulating layer 704, and a semiconductor layer 706. The integrated circuit device 156 and the capacitor structure 720 on the front side of the substrate layer 154 may be included in the semiconductor layer 706, and the capacitor structure 710 included on the back side of the substrate layer 154 may be included in the semiconductor layer 702. Therefore, the insulating layer 704 is vertically included between the integrated circuit device 156 and the capacitor structure 710, and vertically included between the capacitor structure 710 and the capacitor structure 720.

[0113] Figure 7H An example embodiment 724 of the semiconductor die package 100 is shown, which is similar. Figure 7F Example embodiment 718 is shown. However, in example embodiment 714 of the semiconductor die package 100, in addition to including capacitor structures (180) in the interconnect layer 168 of the semiconductor die 104, one or more capacitor structures 710 are also included in the back side of the substrate layer 154 of the semiconductor die 104. Including capacitor structures 180 and 710 on the back side of the semiconductor die 104, and capacitor structures 166 and 720 on the front side of the semiconductor die 104, can further increase the capacitor density of the semiconductor die 104 and / or can allow the semiconductor die 102 to contain fewer capacitor structures 148.

[0114] Figure 7I An example embodiment 726 of the semiconductor die package 100 is shown, which is similar. Figure 7HExample embodiment 724 is shown. However, in example embodiment 726, the substrate layer 154 of the semiconductor die 104 includes an SOI substrate, which includes a semiconductor layer 702, an insulating layer 704, and a semiconductor layer 706. The integrated circuit device 156 and the capacitor structure 720 on the front side of the substrate layer 154 may be included in the semiconductor layer 706, and the capacitor structure 710 included on the back side of the substrate layer 154 may be included in the semiconductor layer 702.

[0115] Figure 7J An example embodiment 728 of the semiconductor die package 100 is shown, which is similar. Figure 7I The example embodiment is shown. However, in example embodiment 728 of the semiconductor die package 100, one or more capacitor structures 720 are also included on the front side of the substrate layer 154 of the semiconductor die 104. Therefore, the integrated circuit device 156 and the capacitor structure 720 are included on the front side of the substrate layer 154, and the capacitor structure 180 is included in the interconnect layer 168 above (or below) the back side of the substrate layer 154.

[0116] Figure 7K An example embodiment 730 of the semiconductor die package 100 is shown, which is similar. Figure 7J Example embodiment 728. However, in example embodiment 730, the substrate layer 154 of the semiconductor die 104 includes an SOI substrate, which includes a semiconductor layer 702, an insulating layer 704, and a semiconductor layer 706. The integrated circuit device 156 and the capacitor structure 720 on the front side of the substrate layer 154 may be included in the semiconductor layer 706.

[0117] As mentioned above, providing Figure 7A-7K As an example. Other examples can be found related to... Figure 7A-7K The descriptions are different.

[0118] Figure 8 This is a flowchart of an example process 800 related to the formation of the semiconductor die package described herein. In some embodiments, Figure 8 One or more process blocks are performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, ion implantation equipment, annealing equipment, wafer / die transport equipment and / or other types of semiconductor processing equipment.

[0119] like Figure 8As shown, process 800 may include forming a first capacitor structure (block 810) in a first side of the substrate layer of a semiconductor die or in a first interconnect layer above the first side of the substrate layer. For example, one or more semiconductor processing equipment may be used to form the first capacitor structure (e.g., capacitor structure 166, capacitor structure 720) in a first side of the substrate layer (e.g., substrate layer 154) of a semiconductor die (e.g., semiconductor die 104) or in a first interconnect layer (e.g., interconnect layer 152) above the first side of the substrate layer.

[0120] like Figure 8 As further shown, process 800 may include forming a second interconnect layer (block 820) over a second side of a substrate layer perpendicular to the first side. For example, one or more semiconductor processing stations may be used to form a second interconnect layer (e.g., interconnect layer 168) over a second side of a substrate layer perpendicular to the first side, as described herein.

[0121] like Figure 8 As further shown, process 800 may include forming a second capacitor structure (block 830) in the second interconnect layer. For example, one or more semiconductor processing instruments may be used to form the second capacitor structure in the second interconnect layer (e.g., capacitor structure 180), as described herein.

[0122] Process 800 may include additional implementations, such as any single implementation or any combination of implementations described below and / or associated with one or more processes described elsewhere herein.

[0123] In a first embodiment, process 800 includes forming a first capacitor structure in a first interconnect layer and then bonding the first interconnect layer of the semiconductor die to a third interconnect layer (e.g., interconnect layer 138) of the image sensor die (e.g., semiconductor die 102).

[0124] In the second embodiment, forming the second capacitor structure, alone or in combination with the first embodiment, includes forming the second capacitor structure in the second interconnect layer after bonding the first interconnect layer of the semiconductor die to the third interconnect layer of the image sensor die.

[0125] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 800 includes, after forming a second capacitor structure in the second interconnect layer, bonding the second interconnect layer of the semiconductor die to a fourth interconnect layer (e.g., interconnect layer 188) of the signal processing die (e.g., semiconductor die 106).

[0126] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 800 includes forming a third capacitor structure (e.g., capacitor structure 720) in a first side of the substrate layer before forming the first capacitor structure.

[0127] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 800 includes forming a third capacitor structure (e.g., capacitor structure 710) in a second side of the substrate layer after forming the first capacitor structure and before forming the second capacitor structure.

[0128] although Figure 8 The example block for process 800 is shown, but in some embodiments, process 800 includes... Figure 8 The blocks depicted may be additional, fewer, different, or arranged differently. Alternatively, two or more of the blocks or processes in 800 may be executed in parallel.

[0129] Figure 9 This is a flowchart of an example process 900 related to the formation of the semiconductor die package described herein. In some embodiments, Figure 9 One or more process blocks are performed using one or more semiconductor processing equipment, such as deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, ion implantation equipment, annealing equipment, wafer / die transport equipment and / or other types of semiconductor processing equipment.

[0130] like Figure 9 As shown, process 900 may include forming a first capacitor structure (block 910) in a first side of the substrate layer of a semiconductor die or in a first interconnect layer above the first side of the substrate layer. For example, one or more semiconductor processing equipment may be used to form the first capacitor structure (e.g., capacitor structure 166, capacitor structure 720) in a first side of the substrate layer (e.g., substrate layer 154) of a semiconductor die (e.g., semiconductor die 104) or in a first interconnect layer (e.g., interconnect layer 152) above the first side of the substrate layer.

[0131] like Figure 9 As further shown, process 900 may include forming a second capacitor structure (block 920) on a first side perpendicular to the second side of the substrate. For example, one or more semiconductor processing equipment may be used to form the second capacitor structure (e.g., capacitor structure 710) in the second side of the substrate perpendicular to the first side, as described herein.

[0132] like Figure 9As further shown, process 900 may include forming a second interconnect layer (block 930) over a second side of the substrate after forming the second capacitor structure. For example, as described herein, after forming the second capacitor structure, one or more semiconductor processing equipment may be used to form the second interconnect layer (e.g., interconnect layer 168) over the second side of the substrate.

[0133] Process 900 may include other implementations, such as any single implementation or any combination of implementations in combination with one or more other processes described elsewhere herein.

[0134] although Figure 9 The example block for process 900 is shown, but in some embodiments, process 900, with Figure 9 Compared to those depicted in [the text], this includes additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more of the blocks or processes 900 can be executed in parallel.

[0135] Thus, the image sensor device includes capacitor structures within multiple semiconductor dies of the image sensor assembly. The capacitor structures can be configured to store charge associated with photocurrents generated by pixel sensors in the pixel sensor array of the sensor die of the image sensor device. In other examples, the capacitor structures can be located on the front side of the sensor die, on the front side of an application-specific integrated circuit (ASIC) die directly bonded to the sensor die, and on the back side of the ASIC die. Capacitor structures included on the back side of the ASIC die can be included in the back side of the semiconductor substrate of the ASIC die, and / or can be included in an interconnect layer perpendicularly adjacent to the semiconductor substrate. Including capacitor structures on the front and back sides of the ASIC die allows for more efficient use of the ASIC die area to integrate the capacitor structures, which can increase the density of capacitor structures in the image sensor device without sacrificing area on the sensor die.

[0136] As described in more detail above, some embodiments described herein provide semiconductor die packages. A semiconductor die package includes a first semiconductor die. The first semiconductor die includes a first substrate layer, a first interconnect layer perpendicularly adjacent to a first side of the first substrate layer, a second interconnect layer perpendicularly adjacent to a second side opposite to the first side of the first substrate layer, a first capacitor structure in the first interconnect layer, and a second capacitor structure in the second interconnect layer. A semiconductor die package also includes a second semiconductor die. The second semiconductor die includes a second substrate layer, a third interconnect layer perpendicularly adjacent to a first side of the second substrate layer, and a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors on a second side of the second substrate layer opposite to the first side. The first interconnect layer of the first semiconductor die is bonded to the third interconnect layer of the second semiconductor die.

[0137] In some embodiments, the semiconductor die package further includes: a third capacitor structure on a first side of the first substrate layer, wherein the third capacitor structure extends from the first side of the first substrate layer into the first substrate layer. In some embodiments, the semiconductor die package further includes: a third capacitor structure on a second side of the first substrate layer, wherein the third capacitor structure extends from the second side of the first substrate layer into the first substrate layer. In some embodiments, the first substrate layer comprises a silicon substrate layer. In some embodiments, the first substrate layer comprises silicon-on-insulator, the first substrate layer comprising: a first semiconductor layer perpendicularly adjacent to the first interconnect layer; a second semiconductor layer perpendicularly adjacent to the second interconnect layer; and an insulating layer perpendicularly located between the first semiconductor layer and the second semiconductor layer. In some embodiments, the semiconductor die package further includes: a third capacitor structure on a second side of the first substrate layer, wherein the third capacitor structure extends from the second side of the first substrate layer into the first semiconductor layer. In some embodiments, the semiconductor die package is characterized in that it further includes: a third semiconductor die, comprising: a third substrate layer; and a fourth interconnect layer perpendicularly adjacent to the third substrate layer, wherein the fourth interconnect layer of the third semiconductor die is bonded to the second interconnect layer of the first semiconductor die.

[0138] As described in more detail above, some embodiments described herein provide semiconductor die packages. A semiconductor die package includes a first semiconductor die. The first semiconductor die includes a first substrate layer, a first interconnect layer perpendicularly adjacent to a first side of the first substrate layer, a second interconnect layer perpendicularly adjacent to a second side of the first substrate layer opposite to the first side, a first capacitor structure in the first interconnect layer, and a second capacitor structure on a second side of the first substrate layer. The second capacitor structure extends from the second side of the first substrate layer into the first substrate layer. A semiconductor die package includes a second semiconductor die. The second semiconductor die includes a second substrate layer, a third interconnect layer perpendicularly adjacent to a first side of the second substrate layer, and a pixel sensor array. The pixel sensor array includes a plurality of pixel sensors on a second side of the second substrate layer opposite to the first side. The first interconnect layer of the first semiconductor die is bonded to the third interconnect layer of the second semiconductor die.

[0139] In some embodiments, the semiconductor die package further includes: a third capacitor structure in the third interconnect layer of the second semiconductor die. In some embodiments, the semiconductor die package further includes: a third capacitor structure on the first side of the first substrate layer, wherein the third capacitor structure extends from the first side of the first substrate layer into the first substrate layer. In some embodiments, the first substrate layer includes silicon-on-insulator, the first substrate layer including: a first semiconductor layer perpendicularly adjacent to the first interconnect layer; a second semiconductor layer perpendicularly adjacent to the second interconnect layer; and an insulating layer perpendicularly between the first semiconductor layer and the second semiconductor layer, wherein the third capacitor structure is contained in the first semiconductor layer. In some embodiments, the second capacitor structure is contained in the second semiconductor layer. In some embodiments, the semiconductor die package further includes: a third semiconductor die including: a third substrate layer; and a fourth interconnect layer perpendicularly adjacent to the third substrate layer, wherein the fourth interconnect layer of the third semiconductor die is bonded to the second interconnect layer of the first semiconductor die. In some embodiments, the first substrate layer includes silicon-on-insulator (SOI), the first substrate layer including: a first semiconductor layer, which is perpendicularly adjacent to the first interconnect layer; a second semiconductor layer, which is perpendicularly adjacent to the second interconnect layer; and an insulating layer, which is perpendicularly located between the first semiconductor layer and the second semiconductor layer, wherein the second capacitor structure is contained in the second semiconductor layer.

[0140] As described in more detail above, some embodiments described herein provide a method. This method includes forming a first interconnect layer over a first side of a substrate layer of a semiconductor die. The method includes forming a first capacitor structure in the first interconnect layer. The method includes forming a second interconnect layer over a second side of a substrate layer perpendicular to the first side. The method includes forming a second capacitor structure in the second interconnect layer.

[0141] The terms “approximately” and “generally” can mean that a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that the terms “approximately” and “generally” can refer to a percentage of the value of a given quantity in this disclosure.

[0142] The features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of the present invention. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor die package, characterized in that, include: The first semiconductor die includes: First substrate layer; The first inner interconnect layer is perpendicularly adjacent to the first side of the first substrate layer; The second inner interconnect layer is perpendicularly adjacent to the second side of the first substrate layer opposite to the first side; A first capacitor structure, within the first interconnect layer; and A second capacitor structure, within the second interconnect layer; and The second semiconductor die includes: Second substrate layer; A third inner interconnect layer is perpendicularly adjacent to a first side of the second substrate layer; and A pixel sensor array, comprising multiple pixel sensors, is located on a second side of the second substrate layer opposite to the first side. The first interconnect layer of the first semiconductor die is bonded to the third interconnect layer of the second semiconductor die.

2. The semiconductor die package according to claim 1, characterized in that, Also includes: Third capacitor structure, On the first side of the first substrate, the third capacitor structure extends from the first side of the first substrate into the first substrate, or On the second side of the first substrate layer The third capacitor structure extends from the second side of the first substrate into the first substrate.

3. The semiconductor die package according to claim 1, characterized in that, The first substrate layer comprises a silicon substrate layer.

4. The semiconductor die package according to claim 1, characterized in that, The first substrate layer comprises silicon-on-insulator, and the first substrate layer includes: The first semiconductor layer is perpendicularly adjacent to the first interconnect layer; A second semiconductor layer, perpendicularly adjacent to the second interconnect layer; and An insulating layer is vertically positioned between the first semiconductor layer and the second semiconductor layer. The semiconductor die package also includes: The third capacitor structure is located on the second side of the first substrate layer. The third capacitor structure extends from the second side of the first substrate into the first semiconductor layer.

5. The semiconductor die package according to claim 1, characterized in that, Also includes: The third semiconductor die includes: Third substrate layer; as well as The fourth inner interconnect layer is perpendicularly adjacent to the third substrate layer. The fourth interconnect layer of the third semiconductor die is bonded to the second interconnect layer of the first semiconductor die.

6. A semiconductor die package, characterized in that, include: The first semiconductor die includes: First substrate layer; The first inner interconnect layer is perpendicularly adjacent to the first side of the first substrate layer; The second inner interconnect layer is perpendicularly adjacent to the second side of the first side that is opposite to the first substrate layer; A first capacitor structure, within the first interconnect layer; and The second capacitor structure is located on the second side of the first substrate layer. The second capacitor structure extends from the second side of the first substrate layer into the first substrate layer; and The second semiconductor die includes: Second substrate layer; A third inner interconnect layer is perpendicularly adjacent to a first side of the second substrate layer; and A pixel sensor array, comprising a plurality of pixel sensors on a second side of the second substrate layer opposite to the first side. The first interconnect layer of the first semiconductor die is bonded to the third interconnect layer of the second semiconductor die.

7. The semiconductor die package according to claim 6, characterized in that, Also includes: A third capacitor structure is located in the third interconnect layer of the second semiconductor die.

8. The semiconductor die package according to claim 6, characterized in that, Also includes: The third capacitor structure is located on the first side of the first substrate layer. The third capacitor structure extends from the first side of the first substrate into the first substrate.

9. The semiconductor die package according to claim 8, characterized in that, The first substrate layer comprises silicon-on-insulator, and the first substrate layer includes: The first semiconductor layer is perpendicularly adjacent to the first interconnect layer; A second semiconductor layer, perpendicularly adjacent to the second interconnect layer; and An insulating layer is perpendicularly positioned between the first semiconductor layer and the second semiconductor layer. The third capacitor structure is contained in the first semiconductor layer, and the second capacitor structure is contained in the second semiconductor layer.

10. The semiconductor die package according to claim 6, characterized in that, Also includes: The third semiconductor die includes: Third substrate layer; as well as The fourth inner interconnect layer is perpendicularly adjacent to the third substrate layer. The fourth interconnect layer of the third semiconductor die is bonded to the second interconnect layer of the first semiconductor die.

Images