Solar cell and photovoltaic module

Abstract

The utility model discloses a solar cell and photovoltaic module, the solar cell includes silicon wafer, the silicon wafer includes opposite first surface and second surface, have doped structure and transparent conductive layer on the first surface and / or the second surface, be equipped with electrode on the transparent conductive layer, the electrode includes conductive base layer and first metal layer, the conductive base layer with the transparent conductive layer contact, the first metal layer is located the conductive base layer outside, the line width L2 of first metal layer is greater than the line width L1 of the conductive base layer, the cross -sectional area S1 of conductive base layer and the cross -sectional area S2 of first metal layer satisfy: 0.25≤S2 / S1≤0.95. The utility model discloses through the cross -sectional area of optimizing conductive base layer and first metal layer, can obtain electrical performance excellent, grid line fine and dense metallization structure, thereby has improved the battery efficiency and component power.

Description

Technical Field

[0001] This utility model belongs to the field of solar cell technology, specifically relating to a solar cell and a photovoltaic module. Background Technology

[0002] Heterojunction (HJT) solar cells are a hybrid type of solar cell made from crystalline silicon wafers and amorphous silicon thin films. They have many advantages, such as simple fabrication process, low processing temperature, high open-circuit voltage, high photoelectric conversion efficiency, and low temperature coefficient. They are one of the most widely used high-efficiency crystalline silicon solar cell technologies.

[0003] Copper-plated cell grid lines represent the ultimate path to eliminating silver in the current photovoltaic industry. Copper interconnect technology can effectively reduce the BOM cost of heterojunction cells and enhance the competitiveness of heterojunction cell products. However, existing copper interconnect technologies require the use of semiconductor photoluminescence equipment and photosensitive inks for patterning electroplating masks. The quality of the grid lines is closely related to the properties of the inks, and cell efficiency and module power are limited by the photosensitive inks.

[0004] Therefore, in order to address the aforementioned technical problems, it is necessary to provide a solar cell and a photovoltaic module. Utility Model Content

[0005] The purpose of this invention is to provide a solar cell and photovoltaic module to obtain a metallized structure with excellent electrical performance and fine grid lines.

[0006] To achieve the above objectives, the technical solution provided by an embodiment of this utility model is as follows: A solar cell includes a silicon wafer with opposing first and second surfaces. The first and / or second surfaces have doped structures and a transparent conductive layer. An electrode is disposed on the transparent conductive layer. Each electrode includes a conductive substrate and a first metal layer. The conductive substrate is in contact with the transparent conductive layer. The first metal layer is located outside the conductive substrate. The linewidth L2 of the first metal layer is greater than the linewidth L1 of the conductive substrate. The orthographic projection area of ​​the conductive substrate along the thickness direction of the silicon wafer is located within the orthographic projection area of ​​the first metal layer. The cross-sectional area S1 of the conductive substrate and the cross-sectional area S2 of the first metal layer satisfy: 0.25 ≤ S2 / S1 ≤ 0.95.

[0007] In one or more embodiments of the present invention, the conductive substrate comprises non-densely distributed metal particles and non-metal particles, and the first metal layer covers the surface of the conductive substrate and extends to cover the surface of the transparent conductive layer.

[0008] In one or more embodiments of this utility model, the volume percentage of metal particles in the conductive substrate is greater than or equal to 3%; and / or, The area ratio of metal particles within the cross-section of the conductive substrate is greater than or equal to 3%.

[0009] In one or more embodiments of this utility model, the volume percentage of metal particles in the conductive substrate is 85% to 95%; and / or, The area ratio of metal particles in the cross-section of the conductive substrate is 85% to 95%.

[0010] In one or more embodiments of this utility model, the cross-sectional area S1 of the conductive substrate and the cross-sectional area S2 of the first metal layer satisfy: 0.28≤S2 / S1≤0.95 or 0.46≤S2 / S1≤0.85.

[0011] In one or more embodiments of this utility model, the cross-sectional area S1 of the conductive substrate is 0.5 μm. 2 ~200μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm. 2 ~200μm 2 .

[0012] In one or more embodiments of the present invention, the solar cell further includes a dielectric layer covering the transparent conductive layer and the conductive base layer, wherein the dielectric layer discontinuously covers the surface of the conductive base layer and continuously covers the surface of the transparent conductive layer, and the first metal layer covers at least the dielectric layer discontinuously covered on the surface of the conductive base layer.

[0013] In one or more embodiments of this invention, the dielectric layer comprises SiN. X SiO X SiNO X One or more layers of Al2O3, ZrO2, MgF2; and / or, The thickness of the dielectric layer is 2nm to 10nm.

[0014] In one or more embodiments of this utility model, the cross-sectional area S1 of the conductive substrate and the cross-sectional area S2 of the first metal layer satisfy: 0.25≤S2 / S1≤0.75.

[0015] In one or more embodiments of this utility model, the cross-sectional area S1 of the conductive substrate is 0.5 μm. 2 ~200μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm. 2 ~200μm 2 .

[0016] In one or more embodiments of this utility model, the linewidth L1 of the conductive substrate is 5μm to 20μm; and / or, The height of the conductive substrate is 50 nm to 10 μm or 2 μm to 10 μm; and / or, The center-to-center distance between two adjacent conductive substrates is 1mm to 5mm or 2mm to 3mm.

[0017] In one or more embodiments of the present invention, the electrode further includes at least one second metal layer located outside the first metal layer, wherein the linewidth L3 of the second metal layer is greater than the linewidth L2 of the first metal layer.

[0018] In one or more embodiments of this utility model, the doped structure includes at least one intrinsic layer and at least one doped layer sequentially stacked on the surface of the silicon wafer; and / or, The thickness of the transparent conductive layer is 15nm to 150nm.

[0019] Another embodiment of this utility model provides the following technical solution: A photovoltaic module comprising the aforementioned solar cell.

[0020] Compared with the prior art, the present invention has the following beneficial effects: This invention optimizes the cross-sectional area of ​​the conductive substrate and the first metal layer to obtain a metallized structure with excellent electrical performance and fine grid lines, thereby improving battery efficiency and module power. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the heterojunction battery structure in Comparative Example 1 of this utility model; Figure 2 This is a schematic diagram of the heterojunction battery in Embodiment 1 of this utility model; Figure 3 for Figure 2 A magnified view of a portion of point A1 in the diagram; Figures 4a-4d This is a process flow diagram of the heterojunction battery preparation method in Embodiment 1 of this utility model; Figure 5This is a schematic diagram of the heterojunction battery in Embodiment 2 of this utility model; Figure 6 for Figure 5 A magnified view of a portion of point B1; Figure 7 This is a schematic diagram of the heterojunction battery in Embodiment 3 of this utility model; Figure 8 for Figure 7 A magnified view of a portion of point C1; Figure 9 This is a schematic diagram of the heterojunction battery in Embodiment 4 of this utility model; Figure 10 for Figure 9 A magnified view of a portion of point A2 in the diagram; Figures 11a-11e This is a process flow diagram of the heterojunction battery preparation method in Embodiment 4 of this utility model; Figure 12 This is a schematic diagram of the heterojunction battery in Embodiment 5 of this utility model; Figure 13 for Figure 12 A magnified view of a portion of point B2 in the middle; Figure 14 This is a schematic diagram of the heterojunction battery in Embodiment 6 of this utility model; Figure 15 for Figure 14 A magnified view of a portion of point C2.

[0023] Explanation of key figure labels: 10' - Silicon wafer, 21' - First intrinsic layer, 22' - Second intrinsic layer, 31' - First doped layer, 32' - Second doped layer, 41' - First transparent conductive layer, 42' - Second transparent conductive layer, 61' - First electrode, 62' - Second electrode; 10-Silicon wafer, 21-First intrinsic layer, 22-Second intrinsic layer, 31-First doped layer, 32-Second doped layer, 41-First transparent conductive layer, 42-Second transparent conductive layer, 51-First dielectric layer, 511-Discontinuous dielectric layer, 512-Continuous dielectric layer, 52-Second dielectric layer, 61-First electrode, 611-Conductive base layer, 612-First metal layer, 613-Second metal layer, 62-Second electrode. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions in the present utility model, the technical solutions in the embodiments of the present utility model will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only part of the embodiments of the present utility model, not all of them. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the present utility model.

[0025] In the present utility model, unless otherwise explicitly specified and defined, a first feature "on" or "under" a second feature may mean that the first feature and the second feature are in direct contact, or the first feature and the second feature are in indirect contact through an intermediate medium. Furthermore, the first feature being "above", "at the upper part of" and "on" the second feature may mean that the first feature is directly above or obliquely above the second feature, or it merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "at the lower part of" and "under" the second feature may mean that the first feature is directly below or obliquely below the second feature, or it merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0026] The present utility model discloses a solar cell, comprising a silicon wafer, the silicon wafer comprising a first surface and a second surface opposite to each other, a doped structure and a transparent conductive layer are provided on the first surface and / or the second surface, an electrode is provided on the transparent conductive layer, the electrode comprises a conductive base layer and a first metal layer, the conductive base layer is in contact with the transparent conductive layer, the first metal layer is located outside the conductive base layer, the line width L2 of the first metal layer is larger than the line width L1 of the conductive base layer, and the orthographic projection area of the conductive base layer along the thickness direction of the silicon wafer is within the orthographic projection area of the first metal layer, the cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.25≤S2 / S1≤0.95.

[0027] The present utility model also discloses a photovoltaic module, comprising the solar cell described above.

[0028] By optimizing the cross-sectional areas of the conductive base layer and the first metal layer, the present utility model can obtain a metallized structure with excellent electrical performance and fine grid lines, thereby improving cell efficiency and module power.

[0029] The present utility model will be further described below with reference to specific examples.

[0030] Comparative Example 1: Reference Figure 1 shows a schematic structural view of the heterojunction cell in this comparative example, the heterojunction cell comprises: a silicon wafer 10', which comprises oppositely arranged a front surface (i.e., a light-receiving surface) and a back surface (i.e., a backlight surface); a first intrinsic layer 21', a first doped layer 31' and a first transparent conductive layer 41' sequentially stacked on the front side; a second intrinsic layer 22', a second doped layer 32' and a second transparent conductive layer 42' sequentially stacked on the back side; a first electrode 61' in contact with the first transparent conductive layer 41'; a second electrode 62' in contact with the second transparent conductive layer 42'.

[0031] For example, the silicon wafer 10' is N-type doped; the first intrinsic layer 21' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, the first doped layer 31' is an N-type doped amorphous silicon layer or microcrystalline silicon layer; the second intrinsic layer 22' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, the second doped layer 32' is a P-type doped amorphous silicon layer or microcrystalline silicon layer; the first transparent conductive layer 41' and the second transparent conductive layer 42' can be a combination of one or more of transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO; both the first electrode 61' and the second electrode 62' are grid line electrodes.

[0032] Example 1: Refer Figure 2 to and in combination with Figure 3 as shown, the solar cell in this example is a heterojunction cell, which comprises: a silicon wafer 10, which comprises oppositely arranged front side (i.e., light-receiving side) and back side (i.e., backlight side), and the front side and the back side respectively comprise a metal region and a non-metal region; a first intrinsic layer 21, a first doped layer 31 and a first transparent conductive layer 41 sequentially stacked on the front side; a second intrinsic layer 22, a second doped layer 32 and a second transparent conductive layer 42 sequentially stacked on the back side; a first electrode 61, the first electrode 61 is located in the metal region on the front side of the silicon wafer 10 and distributed at intervals along a first direction (X direction), which comprises a conductive base layer 611 and a first metal layer 612, the conductive base layer 611 is in contact with the first transparent conductive layer 41, the first metal layer 612 covers the surface of the conductive base layer 611 and extends to cover the surface of the first transparent conductive layer 41.

[0033] a second electrode 62, the structure of the second electrode 62 is completely the same as that of the first electrode 61, which will not be repeated herein.

[0034] In this example, the silicon wafer 10 is an N-type monocrystalline silicon wafer with a resistivity of 0.5 Ω·m to 3 Ω·m, a thickness of 90 μm to 120 μm, and a size of 210 mm, and both the front side and the back side of the silicon wafer 10 are polished surfaces.

[0035] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron doped) amorphous silicon layer or microcrystalline silicon layer.

[0036] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be one or more of the following transparent conductive layers: ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc., preferably an ITO transparent conductive layer; the thickness is 15nm to 150nm, preferably 50nm.

[0037] The silicon wafer, intrinsic layer, doped layer, and transparent conductive layer in this embodiment are exactly the same as those in Comparative Example 1, and will not be described again here. The difference between this embodiment and Comparative Example 1 is that the structures of the first electrode 61 and the second electrode 62 are different.

[0038] The second electrode 62 is exactly the same as the first electrode 61, as shown in the figure. Figure 2 and combined Figure 3 As shown, the first electrode 61 on the front side of the silicon wafer will be described in detail below.

[0039] The first electrode 61 in this invention is a shell electrode consisting of a conductive base layer and a first metal layer (such as a metal electroplating layer), which can effectively reduce the resistivity of the electrode and has electrical advantages compared with existing slurry-based batteries. The first electrode 61 is a grid line electrode, and when the silicon wafer size is 210mm, the number of grid line electrodes is preferably 70 to 90.

[0040] Specifically, the conductive base layer 611 in the first electrode 61 is in direct contact with the first transparent conductive layer 41. The line width L1 of the conductive base layer 611, which is the width of the conductive base layer 611 along the first direction (X direction), is 5μm to 20μm. The height along the second direction (Z direction) is 50nm to 10μm, preferably 2μm to 10μm. The center-to-center distance between two adjacent conductive base layers 611 is 1mm to 5mm, preferably 2mm to 3mm.

[0041] The conductive substrate 611 in the first electrode 61 of this invention is a non-dense structure, which is prepared by screen printing or laser transfer (PTP) process. A patterned conductive substrate with a height of micrometer can be prepared by a relatively inexpensive and simple deposition process.

[0042] Specifically, the conductive base layer 611 comprises non-densely distributed metal particles and non-metal particles, which may also be referred to as metal particles or non-metallic particles. The metal particles comprise one or more selected from the group consisting of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn particles, etc. The non-metal particles comprise one or more selected from the group consisting of thermoplastic polymer resin particles, diluent particles, curing agent particles, thickener particles, coupling agent particles, organic solvent particles, etc. The thermoplastic polymer resin particles comprise one or more selected from the group consisting of acrylate resin particles, epoxy resin particles, etc. The conductive base layer 611 can be prepared from electrode paste, which is a mixture of a metal material and a non-metallic material, and a non-dense structure can be formed after drying.

[0043] Preferably, the volume ratio of the metal particles in the conductive base layer 611 of this embodiment is greater than or equal to 3%. When the metal particles and the non-metal particles are uniformly distributed, that is, the area ratio of the metal particles in the cross section of the conductive base layer 611 is greater than or equal to 3%.

[0044] More preferably, the conductive base layer 611 can be prepared by using a conventional electrode paste, and the electrode paste comprises metal particles and non-metal particles. After drying, the volume ratio of the metal particles in the conductive base layer 611 is 85% to 95%. When the metal particles and the non-metal particles are uniformly distributed, that is, the area ratio of the metal particles in the cross section of the conductive base layer 611 is 85% to 95%. For example, the volume ratio of the metal particles in the conductive base layer 611 or the area ratio of the metal particles in the cross section of the conductive base layer 611 can be 85%, 90%, 95%, etc. In this embodiment, 90% is taken as an example for description.

[0045] In addition, the first metal layer 612 in the first electrode 61 covers the surface of the conductive base layer 611 and extends to cover the surface of the first transparent conductive layer 41. It is not necessary to prepare a dielectric layer or open a window in the dielectric layer to achieve electrical contact between the first metal layer 612 and the conductive base layer 611. The line width L2 of the first metal layer 612, that is, the width of the first metal layer 612 along the first direction (X direction), is greater than the line width L1 of the conductive base layer 611. In the thickness direction of the silicon wafer 10 (that is, the second direction or Z direction), the orthographic projection area of the conductive base layer 611 is located within the orthographic projection area of the first metal layer 612, so that full coverage of the conductive base layer 611 by the first metal layer 612 can be achieved.

[0046] The material of the first metal layer 612 is one or more selected from the group consisting of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and it is prepared by an electroplating or electroless plating process, preferably an electroplating process.

[0047] Refer Figure 3As shown, the cross-sectional area S1 of the conductive base layer 611 is the cross-sectional area of ​​the conductive base layer 611 in the plane perpendicular to the extension direction of the conductive base layer 611, and the cross-sectional area S2 of the first metal layer 612 is the cross-sectional area of ​​the first metal layer 612 in the plane perpendicular to the extension direction of the first metal layer 612.

[0048] In this invention, S1 and S2 satisfy the following condition: 0.28 ≤ S2 / S1 ≤ 0.95, preferably: 0.46 ≤ S2 / S1 ≤ 0.85; wherein, S1 is 0.5 μm. 2 ~200μm 2 S2 is 0.25μm 2 ~200μm 2 .

[0049] In this embodiment, the outer surfaces of the conductive base layer 611 and the first metal layer 612 away from the silicon wafer 10 are both curved surfaces. The cross-section of the conductive base layer 611 is approximately semi-circular. The distance between the conductive base layer and the front surface of the first transparent conductive layer gradually decreases from the middle to both sides. In other embodiments, the cross-section of the conductive base layer can also be rectangular, triangular, trapezoidal, etc. The outer surfaces of the conductive base layer 611 and the first metal layer 612 can be curved surfaces, planes, or combinations thereof, or they can be irregular surfaces. Examples will not be given here.

[0050] The first electrode 61 on the front side of the silicon wafer in this embodiment has been described in detail above. The second electrode 62 on the back side of the silicon wafer is exactly the same as the first electrode 61 on the front side of the silicon wafer, and will not be described again here.

[0051] The specific method for preparing the solar cell in this embodiment is as follows: 1. Reference Figure 4a As shown, silicon wafers are provided.

[0052] In this embodiment, the silicon wafer 10 is an N-type monocrystalline silicon wafer with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm. Both the front and back sides of the silicon wafer 10 are polished with polishing slurry to form polished surfaces.

[0053] 2. Reference Figure 4b As shown, a first intrinsic layer 21, a first doped layer 31, and a first transparent conductive layer 41 are sequentially formed on the front side of the silicon wafer 10, and a second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 are sequentially formed on the back side of the silicon wafer 10.

[0054] Preferably, in this embodiment, the intrinsic layer and the doped layer are deposited using plasma chemical vapor deposition (PECVD), and the transparent conductive layer is deposited using reactive plasma deposition (RPD) or magnetron sputtering, as detailed below: First, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire front area of ​​silicon wafer 10 through PECVD process. Then, SiH4 gas, H2 gas and PH3 (phosphine) gas are introduced into the vacuum chamber, and an N-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer through PECVD process. Then, the wafer is flipped over, the tray is changed, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire back side of the silicon wafer 10 through the PECVD process. Then, SiH4 gas, H2 gas and B2H6 (diborane) gas are introduced into the vacuum chamber, and a P-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer through the PECVD process. Finally, reactive plasma deposition (RPD) or magnetron sputtering processes were used to deposit films on the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer. The back side was edge-masked using a carrier disk design (through a mask), with a specific masking area of ​​0.5mm–0.8mm around the perimeter. The transparent conductive layer was ITO (99.5%:0.5%)wt, with a thickness of 50nm and a carrier concentration of 2E20cm⁻¹. -3 ~3.5E20cm -3 Mobility 70cm 2 / Vs~100cm 2 / Vs.

[0055] In this embodiment, the carrier concentration of the first transparent conductive layer 41 and the second transparent conductive layer 42 is 2E20cm⁻¹. -3 ~3.5E20cm -3 The preferred size is 3E20cm. -3 The migration rate is 70cm. 2 / Vs~100cm 2 / Vs, preferably 80cm 2 / Vs, contact resistivity 0.8mΩ·cm 2～ 4mΩ·cm 2 Preferably 2mΩ·cm 2 Its refractive index is 2.0 to 2.1.

[0056] 3. Participate Figure 4c As shown, a conductive substrate is prepared on a transparent conductive layer.

[0057] Specifically, a screen printing process or a laser transfer printing (PTP) process is used to prepare a patterned conductive base layer, with a line width L1 of 5μm to 20μm and a height of 50nm to 10μm, preferably 2μm to 10μm. Low-temperature conductive paste is used as the paste, and the conductive paste is a mixture of a metal material and a non-metal material. The metal material in the conductive paste comprises one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., the non-metal material comprises one or more of thermoplastic polymer resin, diluent, curing agent, thickener, coupling agent, organic solvent, etc., and the thermoplastic polymer resin comprises acrylate resin, epoxy resin, etc.

[0058] Then sintering and curing are carried out at 150°C to 220°C to form a good ohmic contact. In this embodiment, the volume proportion of metal particles in the cured conductive base layer is about 90%.

[0059] 4. Refer Figure 4d as shown, a first metal layer is prepared on the conductive base layer.

[0060] Specifically, an electroplating or electroless plating process is used to prepare a patterned first metal layer on the conductive base layer. The line width L2 of the first metal layer is larger than the line width L1 of the conductive base layer, the material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and the prepared first metal layer can achieve full coverage of the conductive base layer.

[0061] By way of example, taking electroplated copper for the first metal layer, the copper electroplating solution comprises copper sulfate, sulfuric acid, copper balls and additives capable of optimizing the crystal structure of the copper layer, Cu in the copper electroplating solution 2+ has a concentration of 50g / L and a sulfuric acid concentration of 40g / L.

[0062] 5. Finally, the heterojunction cell is alkali-washed, and the prepared heterojunction cell is subjected to light injection treatment, wherein the temperature of the light injection treatment is 210°C, and the duration of the light injection treatment is 90s.

[0063] Example 2: Refer Figure 5 in combination with Figure 6 as shown, the solar cell in this embodiment is a heterojunction cell, its structure and preparation method are basically the same as those in Example 1, and the difference is that both the front side and the back side of the silicon wafer 10 in Example 1 are polished surfaces, while in this embodiment, it is a textured surface with a pyramid structure.

[0064] Before depositing the intrinsic layer, the silicon wafer 10 in this embodiment is subjected to double-sided texturing through an alkali texturing process, specifically: An HF solution with a mass fraction of 1% to 4% is used to remove the surface oxide layer, and a solution with a mass fraction of 1% to 3% such as KOH or NaOH is adopted. By virtue of anisotropic etching of monocrystalline silicon, a textured surface with pyramid structures is formed on the surface of the silicon wafer. Preferably, the size of the pyramid structures is 0.5 μm to 5 μm.

[0065] Referring to Figure 6 , as shown, the surface of the first transparent conductive layer 41 deposited on the surface of the silicon wafer 10 is a textured surface with pyramid structures.

[0066] Example 3: Referring to Figure 7 in combination with Figure 8 , as shown, the solar cell in this example is a heterojunction cell, whose structure and preparation method are basically the same as those in Example 1. The difference is that, in addition to the conductive base layer 611 and the first metal layer 612, the heterojunction cell in this example further comprises at least one second metal layer 613 outside the first metal layer 612.

[0067] Specifically, an electroplating or electroless plating process is used to prepare a patterned second metal layer 613 on the outer side of the first metal layer 612. The line width L3 of the second metal layer 613, that is, the width of the second metal layer 613 along the first direction (X direction), is greater than the line width L2 of the first metal layer 612, and the material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc.

[0068] For example, taking tin electroplating for the second metal layer as an example, the electroplating tin solution comprises stannous methanesulfonate and a tin plating additive, and Sn in the electroplating tin solution 2+ has a concentration of 30 g / L, and the concentration of stannous methanesulfonate is 200 g / L.

[0069] Example 4: Referring to Figure 9 in combination with Figure 10 , as shown, the solar cell in this example is a heterojunction cell, which comprises: a silicon wafer 10 comprising a front surface (i.e., a light-receiving surface) and a back surface (i.e., a backlight surface) that are arranged opposite to each other, wherein the front surface and the back surface respectively comprise a metal region and a non-metal region; a first intrinsic layer 21, a first doped layer 31 and a first transparent conductive layer 41 sequentially stacked on the front surface; a second intrinsic layer 22, a second doped layer 32 and a second transparent conductive layer 42 sequentially stacked on the back surface; The first dielectric layer 51 and the first electrode 61 are located in the metal region on the front side of the silicon wafer 10 and are spaced apart along the first direction (X direction). The first electrode 61 includes a conductive base layer 611 and a first metal layer 612. The conductive base layer 611 is in contact with the first transparent conductive layer 41. In the metal region, the first dielectric layer 51 covers the surface of the conductive base layer 611, and in the non-metal region, the first dielectric layer 51 covers the surface of the first transparent conductive layer 41.

[0070] Specifically, the first dielectric layer 51 is discontinuously covered on the surface of the conductive base layer 611 and continuously covered on the surface of the first transparent conductive layer 41. The first dielectric layer discontinuously covered on the surface of the conductive base layer 611 is a discontinuous segment dielectric layer 511, and the first dielectric layer continuously covered on the surface of the first transparent conductive layer 41 is a continuous segment dielectric layer 512. The first metal layer 612 covers at least the discontinuous segment dielectric layer 511 discontinuously covered on the surface of the conductive base layer 611 and extends to the continuous segment dielectric layer 512 on the surface of the first transparent conductive layer 41. The second dielectric layer 52 and the second electrode 62 have the same structure as the first dielectric layer 51 and the first electrode 61, and will not be described in detail here.

[0071] In this embodiment, silicon wafer 10 is an N-type single crystal silicon wafer with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm. Both the front and back sides of silicon wafer 10 are polished surfaces.

[0072] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron doped) amorphous silicon layer or microcrystalline silicon layer.

[0073] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be one or more of the following transparent conductive layers: ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc., preferably an ITO transparent conductive layer with a thickness of 15nm to 150nm, preferably 50nm.

[0074] The silicon wafer, intrinsic layer, doped layer, and transparent conductive layer in this embodiment are exactly the same as those in Comparative Example 1, and will not be described again here. The difference from Comparative Example 1 is that a first dielectric layer 51 and a second dielectric layer 52 are added in this embodiment, and the structures of the first electrode 61 and the second electrode 62 are also different from those in Comparative Example 1.

[0075] The second dielectric layer 52 and the second electrode 62 are exactly the same as the first dielectric layer 51 and the first electrode 61. Figure 9 and combined Figure 10As shown, the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer will be described in detail below.

[0076] The first dielectric layer 51 in this invention includes SiN X SiO X SiNO X The first dielectric layer 51 can be a single layer of Al2O3, ZrO2, MgF2, etc., or it can be a multilayer composite film. The thickness of the first dielectric layer 51 is 2nm to 10nm. When the first dielectric layer 51 is a multilayer composite film structure, it includes an outer dielectric layer and an inner dielectric layer. The thickness of the inner dielectric layer is less than the thickness of the outer dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

[0077] Preferably, SiN is selected in this embodiment. X The layers respectively serve as the first dielectric layer 51, SiN X The refractive index n of the layer is 2.0, and the thickness is 5 nm. SiN X The layer can be deposited on the first transparent conductive layer 41 and the conductive base layer 611 using a low-temperature PECVD process or a hot-wire CVD process.

[0078] Furthermore, in this embodiment, the refractive index of the first dielectric layer 51 is less than or equal to the refractive index of the first transparent conductive layer 41, which is more conducive to light incidence, reduces light reflection, and increases the short-circuit current Isc; at the same time, the chemical properties of the first dielectric layer are relatively stable, which can serve as a mask layer to effectively protect the first transparent conductive layer, reduce the risk of battery corrosion by chemical liquid, and improve the reliability of the component.

[0079] The first electrode 61 in this invention is a shell electrode consisting of a conductive base layer and a first metal layer (such as a metal electroplating layer), which can effectively reduce the resistivity of the electrode and has electrical advantages compared with existing slurry-based batteries. The first electrode 61 is a grid line electrode, and when the silicon wafer size is 210mm, the number of grid line electrodes is preferably 70 to 90.

[0080] Specifically, the conductive base layer 611 in the first electrode 61 is in direct contact with the first transparent conductive layer 41, and the first dielectric layer 51 is discontinuously covered on the surface of the conductive base layer 611. The linewidth L1 of the conductive base layer 611 is the width of the conductive base layer 611 along the first direction (X direction), which is 5μm to 20μm. The height along the second direction (Z direction) is 50nm to 10μm, preferably 2μm to 10μm. The center-to-center distance between two adjacent conductive base layers 611 is 1mm to 5mm, preferably 2mm to 3mm.

[0081] The material of the conductive base layer 611 is metal or a mixture of metal and organic polymer. The metal includes one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The organic polymer includes non-metallic particles in metal paste. The conductive base layer is prepared by screen printing process or laser transfer printing (PTP) process, and the patterned conductive base layer can be prepared by a relatively cheap and simple deposition process. The conductive base layer 611 can be the same as the conductive base layer 611 in Embodiment 1, and will not be repeated herein.

[0082] In addition, the first metal layer 612 in the first electrode 61 covers the discontinuous dielectric layer 511 that is non-continuously covered on the surface of the conductive base layer 611, so electrical contact between the first metal layer 612 and the conductive base layer 611 can be achieved without opening a window on the first dielectric layer 51. The line width L2 of the first metal layer 612, that is, the width of the first metal layer 612 along the first direction (X direction), is greater than the line width L1 of the conductive base layer 611. Along the thickness direction of the silicon wafer 10 (i.e., the second direction or Z direction), the orthographic projection area of the conductive base layer 611 is located within the orthographic projection area of the first metal layer 612, which can achieve full coverage of the conductive base layer 611 and the discontinuous dielectric layer 511 by the first metal layer 612.

[0083] The material of the first metal layer 612 is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., which is prepared by electroplating or electroless plating process, preferably electroplating process.

[0084] Referring Figure 10 , the cross-sectional area S1 of the conductive base layer 611 is the cross-sectional area of the conductive base layer 611 in a plane perpendicular to the extending direction of the conductive base layer 611, and the cross-sectional area S2 of the first metal layer 612 is the cross-sectional area of the first metal layer 612 in a plane perpendicular to the extending direction of the first metal layer 612.

[0085] In the present utility model, S1 and S2 satisfy: 0.25≤S2 / S1≤0.75, wherein S1 is 0.5μm 2 ~200μm 2 , S2 is 0.25μm 2 ~200μm 2 .

[0086] In this embodiment, the outer surfaces of the conductive base layer 611 and the first metal layer 612 away from the silicon wafer 10 are both curved surfaces. The cross-section of the conductive base layer 611 is approximately semi-circular. The distance between the conductive base layer and the front surface of the first transparent conductive layer gradually decreases from the middle to both sides. In other embodiments, the cross-section of the conductive base layer can also be rectangular, triangular, trapezoidal, etc. The outer surfaces of the conductive base layer 611 and the first metal layer 612 can be curved surfaces, planes, or combinations thereof, or they can be irregular surfaces. Examples will not be given here.

[0087] The first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer in this embodiment have been described in detail above. The second dielectric layer 52 and the second electrode 62 on the back side of the silicon wafer are exactly the same as the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer, and will not be described again here.

[0088] The specific method for preparing the solar cell in this embodiment is as follows: 1. Reference Figure 11a As shown, silicon wafers are provided.

[0089] In this embodiment, the silicon wafer 10 is an N-type monocrystalline silicon wafer with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm. Both the front and back sides of the silicon wafer 10 are polished with polishing slurry to form polished surfaces.

[0090] 2. Reference Figure 11b As shown, a first intrinsic layer 21, a first doped layer 31, and a first transparent conductive layer 41 are sequentially formed on the front side of the silicon wafer 10, and a second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 are sequentially formed on the back side of the silicon wafer 10.

[0091] Preferably, in this embodiment, the intrinsic layer and the doped layer are deposited using plasma chemical vapor deposition (PECVD), and the transparent conductive layer is deposited using reactive plasma deposition (RPD) or magnetron sputtering, as detailed below: First, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire front area of ​​silicon wafer 10 through PECVD process. Then, SiH4 gas, H2 gas and PH3 (phosphine) gas are introduced into the vacuum chamber, and an N-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer through PECVD process. Then, the wafer is flipped over, the tray is changed, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire back side of the silicon wafer 10 through the PECVD process. Then, SiH4 gas, H2 gas and B2H6 (diborane) gas are introduced into the vacuum chamber, and a P-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer through the PECVD process. Finally, reactive plasma deposition (RPD) or magnetron sputtering processes were used to deposit films on the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer. The back side was edge-masked using a carrier disk design (through a mask), with a specific masking area of ​​0.5mm–0.8mm around the perimeter. The transparent conductive layer was ITO (99.5%:0.5%)wt, with a thickness of 50nm and a carrier concentration of 2E20cm⁻¹. -3 ~3.5E20cm -3 Mobility 70cm 2 / Vs~100cm 2 / Vs.

[0092] In this embodiment, the carrier concentration of the first transparent conductive layer 41 and the second transparent conductive layer 42 is 2E20cm⁻¹. -3 ~3.5E20cm -3 The preferred size is 3E20cm. -3 The migration rate is 70cm. 2 / Vs~100cm 2 / Vs, preferably 80cm 2 / Vs, contact resistivity 0.8mΩ·cm 2～ 4mΩ·cm 2 Preferably 2mΩ·cm 2 Its refractive index is 2.0 to 2.1.

[0093] 3. Participate Figure 11c As shown, a conductive substrate is prepared on a transparent conductive layer.

[0094] Specifically, a patterned conductive substrate is prepared using screen printing or laser transfer (PTP) technology, with a line width L1 of 5μm to 20μm and a height of 50nm to 10μm, preferably 2μm to 10μm. The slurry is a low-temperature conductive slurry, which can be a metal or a mixture of metal and organic polymer. The conductive material in the conductive slurry includes one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc.

[0095] Then, sintering and curing are carried out at 150℃~220℃ to form good ohmic contact.

[0096] 4. Participate Figure 11d As shown, a dielectric layer is formed on the surface of the transparent conductive layer and the surface of the conductive substrate.

[0097] Taking the front side of silicon wafer 10 as an example, it is deposited on the first transparent conductive layer 41 and the conductive base layer 611 using a low-temperature PECVD process or a hot-wire CVD process. A first dielectric layer 51 is formed on the surface of the first transparent conductive layer 41 and the conductive base layer 611. The first dielectric layer 51 includes SiN X SiOX SiNO X One or more layers of Al2O3, ZrO2, and MgF2 are deposited at temperatures ranging from 20°C to 200°C, with a deposition thickness ranging from 2 nm to 10 nm.

[0098] Preferably, SiN is selected in this embodiment. X The layers respectively serve as the first dielectric layer 51, SiN X The refractive index n of the layer is 2.0, and the thickness is 5 nm.

[0099] Because the thickness of the conductive substrate 611 is on the micrometer scale, while the thickness of the deposited first dielectric layer 51 is on the nanometer scale, the first dielectric layer 51 cannot form a closed cover on the surface of the conductive substrate 611 due to the difference in film height. Ultimately, the first dielectric layer 51 forms a discontinuous cover on the surface of the conductive substrate 611, but a continuous cover on the surface of the first transparent conductive layer 41. This continuous first dielectric layer on the surface of the first transparent conductive layer 41 can act as a mask for the non-metallic areas.

[0100] 5. Perform heat treatment on the dielectric layer.

[0101] Specifically, the first dielectric layer 51 and the second dielectric layer 52 are heat-treated in an annealing furnace at a temperature of 50°C to 220°C, preferably 150°C to 220°C, for a time of 10 seconds to 25 minutes, preferably 30 seconds to 5 minutes. For example, in this embodiment, the heat treatment temperature is 100°C and the heat treatment time is 1 minute.

[0102] In this invention, to achieve a discontinuous distribution of the dielectric layer on the conductive substrate surface, the thickness of the dielectric layer needs to be controlled between 2nm and 10nm. However, a thin dielectric layer is easily corroded during subsequent electroplating or electroless plating, affecting passivation performance. This step, through heat treatment of the dielectric layer, densifies the dielectric layer on the transparent conductive layer, enabling the dielectric layer in the non-metallic region to have better corrosion resistance and maintain the obtained good passivation performance during subsequent electroplating or electroless plating.

[0103] 6. Participate Figure 11e As shown, a first metal layer is prepared on the dielectric layer.

[0104] Specifically, a patterned first metal layer is prepared on the dielectric layer using electroplating or chemical plating processes. The line width L2 of the first metal layer is greater than the line width L1 of the conductive substrate. The material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The prepared first metal layer can achieve full coverage of the conductive substrate.

[0105] For example, the first metal layer is electroplated copper, the electroplating copper solution comprises copper sulfate, sulfuric acid, copper balls and an additive capable of optimizing the crystal structure of the copper layer, and Cu in the electroplating copper solution 2+ has a concentration of 50 g / L and sulfuric acid has a concentration of 40 g / L.

[0106] In the present utility model, the thickness of the dielectric layer is 2 nm to 10 nm, and the height of the conductive base layer is 50 nm to 10 μm, preferably 2 μm to 10 μm. The height of the conductive base layer is much larger than the thickness of the dielectric layer, so the deposited dielectric layer forms discontinuous coverage on the surface of the conductive base layer. Electroplating can be directly performed subsequently on the discontinuously covered dielectric layer to achieve electrical contact between the first metal layer and the conductive base layer, so no additional window opening process is required for the dielectric layer, which optimizes the process flow and avoids damage to the dielectric layer caused by the window opening process.

[0107] 7. Finally, the heterojunction cell is subjected to alkali washing, and the prepared heterojunction cell is subjected to light injection treatment, wherein the temperature of the light injection treatment is 210°C, and the duration of the light injection treatment is 90 s.

[0108] Example 5: Reference Figure 12 and in combination with Figure 13 as shown, the solar cell in this embodiment is a heterojunction cell, the structure and preparation method thereof are substantially the same as those of Embodiment 1, and the difference is that in Embodiment 1, both the front side and the back side of the silicon wafer 10 are polished sides, while in this embodiment, they are textured surfaces with a pyramid structure.

[0109] The silicon wafer 10 in this embodiment is subjected to double-sided texturing through an alkali texturing process before depositing an intrinsic layer, specifically: A HF solution with a mass fraction of 1% to 4% is used to remove the surface oxide layer, then a solution with a mass fraction of 1% to 3% of KOH or NaOH is used to form a textured surface with a pyramid structure on the surface of the silicon wafer through anisotropic etching of monocrystalline silicon, preferably, the size of the pyramid structure is 0.5 μm to 5 μm.

[0110] Reference Figure 13 as shown, the surface of the first transparent conductive layer 41 deposited on the surface of the silicon wafer 10 is a textured surface with a pyramid structure, and the surface of the continuous segment dielectric layer 512 deposited thereon is also a textured surface with a pyramid structure.

[0111] Example 6: Reference Figure 14 and in combination with Figure 15 as shown, the solar cell in this embodiment is a heterojunction cell, the structure and preparation method thereof are substantially the same as those of Embodiment 1, and the difference is that in addition to the conductive base layer 611 and the first metal layer 612, the heterojunction cell in this embodiment further comprises at least one second metal layer 613 on the outer side of the first metal layer 612.

[0112] Specifically, a patterned second metal layer 613 is prepared on the outside of the first metal layer 612 using electroplating or chemical plating processes. The line width L3 of the second metal layer 613 is the width of the second metal layer 613 along the first direction (X direction), which is greater than the line width L2 of the first metal layer 612. The material is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc.

[0113] For example, the second metal layer is tin plating, and the tin plating solution includes tin methanesulfonate and tin plating additives, wherein Sn in the tin plating solution... 2+ The concentration of tin methanesulfonate is 30 g / L, and the concentration of tin methanesulfonate is 200 g / L.

[0114] IV performance tests were performed on different heterojunction solar cells, and the test data are shown in the table below: Among them, control group 1 is the heterojunction cell in comparative example 1. The grid line electrodes on the front and back sides are prepared by screen printing with low temperature silver paste. The grid line width is 25μm and the number is 60. Experimental groups 1-5 are heterojunction solar cells from Example 1, and experimental groups 6-10 are heterojunction solar cells from Example 4, with 80 grid electrodes on both the front and back sides. It is evident that experimental groups 1-10, compared to control group 1, can fabricate finer grid electrodes with smaller linewidths and spacing.

[0115] The conductive substrate can enhance the adhesion between the subsequent metal layer and the transparent conductive layer and reduce the contact resistivity through physical bonding and chemical adsorption. The metal layer can replace the low-temperature silver paste.

[0116] Since the linear resistivity of the metal layer is significantly better than that of the conductive substrate, the larger the cross-sectional area ratio S2 / S1 of the conductive substrate and the metal layer, the more effectively the series resistance Rs can be reduced and the fill factor FF can be improved. However, as the cross-sectional area ratio S2 / S1 increases, the lateral enhancement will increase, resulting in a decrease in the short-circuit current Isc.

[0117] As can be seen from experimental groups 1-5 and comparative example 1, in the absence of a dielectric layer, by optimizing the cross-sectional area ratio S2 / S1 of the conductive substrate and the metal layer, the battery efficiency Eta can be effectively improved within the range of 0.28≤S2 / S1≤0.95. In particular, within the range of 0.46≤S2 / S1≤0.85, the battery efficiency Eta can be improved by 0.06% to 0.08%.

[0118] In experimental groups 6-10, the introduction of a dielectric layer facilitates light incidence, enhances optical advantages, and effectively protects the transparent conductive layer, reducing the risk of corrosion by chemical solutions. In addition, the dielectric layer is discontinuously covered on the conductive substrate surface, eliminating the need for additional windowing processes on the dielectric layer, avoiding damage to the dielectric layer caused by conventional windowing processes, improving passivation performance, and ultimately effectively improving battery efficiency Eta.

[0119] As can be seen from experimental groups 6-10 and comparative example 1, in the presence of a dielectric layer, by optimizing the cross-sectional area ratio S2 / S1 of the conductive substrate and the metal layer, the battery efficiency Eta can be improved by 0.06% to 0.08% within the range of 0.25≤S2 / S1≤0.75.

[0120] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0121] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that, The device includes a silicon wafer, which has a first surface and a second surface facing each other. The first surface and / or the second surface has a doped structure and a transparent conductive layer. An electrode is provided on the transparent conductive layer. The electrode includes a conductive base layer and a first metal layer. The conductive base layer is in contact with the transparent conductive layer. The first metal layer is located outside the conductive base layer. The linewidth L2 of the first metal layer is greater than the linewidth L1 of the conductive base layer. The orthographic projection area of ​​the conductive base layer along the thickness direction of the silicon wafer is located within the orthographic projection area of ​​the first metal layer. The cross-sectional area S1 of the conductive base layer and the cross-sectional area S2 of the first metal layer satisfy: 0.25≤S2 / S1≤0.

95.

2. The solar cell according to claim 1, characterized in that, The first metal layer covers the surface of the conductive base layer and extends to cover the surface of the transparent conductive layer.

3. The solar cell according to claim 2, characterized in that, The cross-sectional area S1 of the conductive substrate and the cross-sectional area S2 of the first metal layer satisfy the following condition: 0.28≤S2 / S1≤0.

95.

4. The solar cell according to claim 2, characterized in that, The cross-sectional area S1 of the conductive substrate and the cross-sectional area S2 of the first metal layer satisfy the following condition: 0.46≤S2 / S1≤0.

85.

5. The solar cell according to claim 2, characterized in that, The cross-sectional area S1 of the conductive substrate is 0.5 μm. 2 ~200μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm. 2 ~200μm 2 .

6. The solar cell according to claim 1, characterized in that, The solar cell further includes a dielectric layer covering the transparent conductive layer and the conductive base layer, wherein the dielectric layer discontinuously covers the surface of the conductive base layer and continuously covers the surface of the transparent conductive layer, and the first metal layer covers at least the dielectric layer discontinuously covered on the surface of the conductive base layer.

7. The solar cell according to claim 6, characterized in that, The dielectric layer includes SiN X SiO X SiNO X One or more layers of Al2O3, ZrO2, MgF2; and / or, The thickness of the dielectric layer is 2nm to 10nm.

8. The solar cell according to claim 6, characterized in that, The cross-sectional area S1 of the conductive substrate and the cross-sectional area S2 of the first metal layer satisfy the condition: 0.25≤S2 / S1≤0.

75.

9. The solar cell according to claim 6, characterized in that, The cross-sectional area S1 of the conductive substrate is 0.5 μm. 2 ~200μm 2 ; and / or, The cross-sectional area S2 of the first metal layer is 0.25 μm. 2 ~200μm 2 .

10. The solar cell according to claim 1, characterized in that, The linewidth L1 of the conductive substrate is 5μm to 20μm; and / or, The height of the conductive substrate is 50 nm to 10 μm; and / or, The center-to-center distance between two adjacent conductive substrates is 1mm to 5mm.

11. The solar cell according to claim 1, characterized in that, The height of the conductive base layer is 2μm to 10μm; and / or, The center-to-center distance between two adjacent conductive substrates is 2mm to 3mm.

12. The solar cell according to claim 1, characterized in that, The electrode further includes at least one second metal layer located outside the first metal layer, wherein the linewidth L3 of the second metal layer is greater than the linewidth L2 of the first metal layer.

13. The solar cell according to claim 1, characterized in that, The doped structure includes at least one intrinsic layer and at least one doped layer sequentially stacked on the surface of the silicon wafer; and / or, The thickness of the transparent conductive layer is 15nm to 150nm.

14. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 13.

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