Stacked solar cells and photovoltaic modules

Abstract

The utility model discloses a laminated solar cell and photovoltaic module. The laminated solar cell has a plurality of through holes, and the laminated solar cell comprises a bottom cell and a top cell arranged in layers, and the plurality of through holes penetrate through the top cell and the bottom cell. The bottom cell comprises a substrate, the back surface of the substrate is provided with a P region, an N region and a spacing region between the P region and the N region, which are alternately distributed, and the orthographic projection of the through hole on the back surface of the substrate is located in the spacing region. The top cell comprises a perovskite light-absorbing layer, the front surface of the perovskite light-absorbing layer is provided with a transparent conductive oxide layer, and the transparent conductive oxide layer extends into the through hole. The laminated solar cell comprises a first electrode, and the first electrode extends from the back surface side of the substrate into the through hole and is in contact with the transparent conductive oxide layer. Thus, the shielding of the light by the front surface of the cell can be reduced, the utilization rate of the light can be improved, and the efficiency of the cell can be improved. The first electrode extends into the through hole, the transmission distance of the transparent conductive oxide layer can be shortened, and the current loss can be reduced.

Description

Technical Field

[0001] This utility model relates to the field of solar cell technology, specifically to tandem solar cells and photovoltaic modules. Background Technology

[0002] The development of perovskite tandem solar cell technology stems from the photovoltaic industry's urgent need to break through the efficiency limit (29.4%) of silicon-based cells and reduce costs. Perovskite materials, with their advantages of high light absorption, tunable bandgap, and low-cost solution preparation, have achieved single-junction efficiencies exceeding 26%. Tandem designs (such as perovskite / silicon) utilize spectral complementarity to increase theoretical efficiency to over 43%, with laboratory efficiencies reaching 34.8%. However, existing perovskite tandem solar cells require silver electrodes printed on a TCO (transparent conductive oxide) film on the front side for current collection; however, electrode shading affects cell efficiency.

[0003] Therefore, current tandem solar cells and photovoltaic modules still need improvement. Utility Model Content

[0004] This invention aims to at least alleviate or solve at least one of the aforementioned problems to some extent.

[0005] In one aspect, this utility model proposes a tandem solar cell. In some embodiments of this utility model, the tandem solar cell has multiple through-holes. The tandem solar cell includes a bottom cell and a top cell stacked together, with the multiple through-holes penetrating the top cell and the bottom cell. The bottom cell includes a substrate, and the back side of the substrate has alternately distributed P-regions, N-regions, and a spacer region between the P-regions and N-regions. The orthogonal projection of the through-holes on the back side of the substrate is located in the spacer region. The top cell includes a perovskite light-absorbing layer, and the front side of the perovskite light-absorbing layer has a transparent conductive oxide layer extending into the through-holes. The tandem solar cell includes a first electrode, which extends from one side of the back side of the substrate into the through-holes and contacts the transparent conductive oxide layer. Thus, the current collected on the front side of the top cell is transmitted to the first electrode via the transparent conductive oxide layer, reducing light shading on the front side of the cell and improving light utilization, thereby improving the photoelectric conversion efficiency of the cell. The first electrode extending into the through-holes shortens the transmission distance of the transparent conductive oxide layer, thereby reducing current loss and further improving the performance of the cell.

[0006] In some embodiments of this utility model, the first electrode is a solid electrode, and the first electrode extends from one end of the through hole to the other end of the through hole.

[0007] In some embodiments of this utility model, at least a portion of the first electrode is a hollow structure, and the first electrode extends from one end of the through hole to the other end of the through hole.

[0008] In some embodiments of this invention, the height to which the first electrode extends into the through-hole is less than the height of the through-hole. Therefore, the unfilled area within the through-hole can transmit light, which helps to further improve light utilization.

[0009] In some embodiments of this utility model, the stacked solar cell satisfies at least one of the following conditions: a back film is disposed on the back side of the substrate, the back film comprising an aluminum oxide layer and / or a silicon nitride layer, the back film extending into the via, and, in the via, the back film being located between the first electrode and the via wall; the top cell comprises a tin oxide layer, the tin oxide layer being located on the side of the perovskite light-absorbing layer away from the bottom cell and extending into the via, the tin oxide layer in the via being located between the transparent conductive oxide layer and the via wall; the transparent conductive oxide layer comprises The via contains at least one of indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and antimony-doped tin oxide; the thickness of the transparent conductive oxide layer in the via decreases along the direction from the top cell to the bottom cell; the diameter of the via is 150 μm-400 μm; the height of the first electrode extending into the via is 15 μm-40 μm; the first electrode has a first end located on the back side of the substrate, and the orthographic projection of the via onto the back side of the substrate falls within the orthographic projection of the first end onto the back side of the substrate. This is beneficial for further improving the overall performance of the battery.

[0010] In some embodiments of this utility model, the thickness of the tin oxide layer is 10nm-20nm; and / or, the thickness of the first end is 5μm-8μm; and / or, along the direction from the top cell to the bottom cell, the thickness of the tin oxide layer in the through hole shows a decreasing trend.

[0011] In some embodiments of this invention, the P-region includes a first tunneling oxide layer, a first doped polysilicon layer, and a second electrode. The first doped polysilicon layer is located on the side of the first tunneling oxide layer away from the substrate, and the second electrode is in contact with the first doped polysilicon layer. The N-region includes a second tunneling oxide layer, a second doped polysilicon layer, and a third electrode. The second doped polysilicon layer is located on the side of the second tunneling oxide layer away from the substrate, and the third electrode is in contact with the second doped polysilicon layer. The doping types of the first and second doped polysilicon layers are opposite. The top cell further includes a first transport layer and a second transport layer. The first transport layer is located on the side of the perovskite light-absorbing layer near the bottom cell, and the second transport layer is located between the perovskite light-absorbing layer and the transparent conductive oxide layer. The first transport layer transports holes, and the second transport layer transports electrons, or the first transport layer transports electrons, and the second transport layer transports holes.

[0012] In some embodiments of this invention, the tandem solar cell further includes a carrier transport layer located between the bottom cell and the top cell.

[0013] In some embodiments of this invention, the carrier transport layer includes at least one of indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, and a doped polycrystalline silicon layer.

[0014] In some embodiments of this invention, the thickness of the charge carrier transport layer is 5nm-10nm.

[0015] In some embodiments of the present invention, the tandem solar cell further includes a third doped polycrystalline silicon layer, which is located between the bottom cell and the carrier transport layer.

[0016] In some embodiments of this invention, the stacked solar cell further includes a third tunneling oxide layer, which is located between the carrier transport layer and the bottom cell.

[0017] In another aspect, this utility model provides a photovoltaic module. In some embodiments of this utility model, the photovoltaic module includes the aforementioned tandem solar cell. Therefore, this photovoltaic module possesses all the features and advantages of the aforementioned tandem solar cell, which will not be repeated here. In general, this photovoltaic module has high light utilization and photoelectric conversion efficiency. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A schematic diagram of a stacked solar cell according to an embodiment of the present invention is shown; Figure 2 A schematic diagram of a stacked solar cell according to another embodiment of the present invention is shown; Figure 3 This shows a schematic diagram of the structure of a stacked solar cell according to yet another embodiment of the present invention; Figure 4 This shows a schematic diagram of the structure of a stacked solar cell according to yet another embodiment of the present invention; Figure 5 This shows a schematic diagram of the structure of a stacked solar cell according to yet another embodiment of the present invention; Figure 6 This shows a partial structural schematic diagram of a stacked solar cell according to an embodiment of the present invention; Figure 7 This diagram shows a partial structural schematic of a tandem solar cell according to an embodiment of the present invention, as well as a schematic diagram of the arrangement of through holes. Figure 8 A schematic diagram of a stacked solar cell according to yet another embodiment of the present invention is shown.

[0019] Explanation of reference numerals in the attached figures: 1: Through-hole; 2: P-region; 3: N-region; 4: Spacer region; 5: First electrode; 6: Carrier transport layer; 7: Third doped polysilicon layer; 8: Third tunneling oxide layer; 51: First end; 10: Bottom cell; 11: Substrate; 12: First tunneling oxide layer; 13: First doped polysilicon layer; 14: Second tunneling oxide layer; 15: Second doped polysilicon layer; 16: Back film; 16-1: Alumina layer; 16-2: Silicon nitride layer; 17: Second electrode; 18: Third electrode; 20: Top cell; 21: Perovskite light-absorbing layer; 22: First transport layer; 23: Second transport layer; 24: Tin oxide layer; 25: Transparent conductive oxide layer; 31: First negative electrode; 32: Second negative electrode; 40: Positive electrode. Detailed Implementation

[0020] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0021] In one aspect, this utility model provides a tandem solar cell. In some embodiments of this utility model, reference is made to... Figures 1 to 5The tandem solar cell has multiple through-holes 1. The tandem solar cell includes a bottom cell 10 and a top cell 20 stacked together, with the multiple through-holes 1 penetrating the top cell 20 and the bottom cell 10. The bottom cell 10 includes a substrate 11, on the back side of which are alternately distributed P-regions 2 and N-regions 3, and a spacer region 4 located between the P-regions 2 and N-regions 3. The orthogonal projection of the through-holes 1 onto the back side of the substrate 11 is located in the spacer region 4. The top cell 20 includes a perovskite light-absorbing layer 21, on the front side of which is a transparent conductive oxide layer 25, and the transparent conductive oxide layer 25 extends into the through-holes 1. The tandem solar cell includes a first electrode 5, which extends from one side of the back side of the substrate 11 into the through-holes 1 and contacts the transparent conductive oxide layer 25.

[0022] To improve the light absorption efficiency and photoelectric conversion efficiency of the tandem solar cell by placing the electrodes of the top cell on the back side, this invention aims to transmit current to the back side of the cell via a transparent conductive oxide (TCO) layer, from which it is then conducted out by the electrodes. However, TCO's conductivity is lower than Ag. If all current collection on the front side relies on the TCO to transmit to the back side of the cell and then conduct out through the electrodes, significant current loss will occur due to the high resistance of the TCO itself. Shortening the transmission distance of the TCO can reduce this loss. In this invention, the transparent conductive oxide layer on the front side of the perovskite light-absorbing layer extends to the back side of the tandem solar cell through a via. The first electrode extends from the back side of the cell into the via and contacts the transparent conductive oxide layer, shortening the TCO transmission distance and improving current collection efficiency. Placing the electrodes of the top cell on the back side of the tandem solar cell and in the via reduces shading on the front side of the tandem solar cell, maximizing light utilization and thus improving the photoelectric conversion efficiency.

[0023] It should be noted that the substrate has opposing front and back sides. The back side is the side of the tandem solar cell that faces away from the sun when in use, and the front side is the side that faces the sun when the cell is in use. Similarly, the perovskite light-absorbing layer also has opposing front and back sides, which are the side facing the sun and the side facing away from the sun when the cell is in use, respectively. It should also be noted that the entire tandem solar cell has multiple through-holes; "multiple" refers to two or more. Figures 1 to 5 The image shows only one through hole as an example to illustrate the location, shape, and other characteristics of the through hole.

[0024] In this invention, the first electrode 5 can have different structures. The structure of the first electrode 5 will be described in detail below with reference to the accompanying drawings.

[0025] In some embodiments, reference Figure 2The first electrode 5 can be a solid electrode. The first electrode 5 extends from one end of the through hole 1 to the other end of the through hole 1, that is to say, the first electrode 5 penetrates through the through hole.

[0026] In other embodiments, reference is made to... Figure 1 At least a portion of the first electrode 5 can be a hollow structure, extending from one end of the through-hole 1 to the other end. In some embodiments, the side of the first electrode 5 furthest from the substrate can extend a distance horizontally from the through-hole (the horizontal direction is perpendicular to the battery thickness direction). This may occur during the fabrication of the first electrode due to the good fluidity of the electrode slurry. In other embodiments, the height to which the first electrode 5 extends into the through-hole can be substantially equal to the height of the through-hole.

[0027] In some embodiments, reference Figure 1 The portion of the first electrode 5 extending into the through hole 1 is a hollow structure, while the first end 51 of the first electrode 5 can be a solid structure. In other embodiments, the portion of the first electrode 5 extending into the through hole 1 is a hollow structure, and the first end 51 can also be a hollow structure.

[0028] In some embodiments, reference Figures 3 to 5 The height to which the first electrode 5 extends into the through hole 1 can be less than the height of the through hole 1. Therefore, the first electrode does not fill the entire through hole, and the unfilled portion of the through hole allows light to pass through, thereby further improving light utilization efficiency. In other embodiments, the height to which the first electrode 5, which has a hollow structure, extends into the through hole 1 can also be less than the height of the through hole 1.

[0029] Figures 1 to 5 The structure of the first electrode shown can collect the current of the top cell, reduce the shading on the front of the tandem solar cell, and thus help improve the utilization rate of light and the photoelectric conversion efficiency of the tandem solar cell.

[0030] In some embodiments of this utility model, reference is made to Figures 1 to 6 The diameter of the via 1 can be 150μm-400μm, for example, the diameter of the via 1 can be 150μm, 170μm, 200μm, 220μm, 250μm, 300μm, 350μm, 400μm, etc. The diameter of the via within the above range is beneficial for the transparent conductive oxide layer 25 to transmit current to the first electrode 5 through the via 1.

[0031] In some embodiments, the diameter of the through hole 1 can be 150μm-250μm.

[0032] It should be noted that the reference Figures 1 to 6 Along the direction from the top cell to the bottom cell ( Figures 1 to 5In the X direction shown, the diameter of the through hole may not be exactly the same. Figure 6 The structure of the battery is omitted in the middle section, and the hole wall of the through hole 1 is shown. It can be seen that the diameter of the through hole in the bottom battery region can be larger than the diameter of the through hole in the top battery region.

[0033] In this invention, the multiple through holes 1 can be arranged as needed. In some embodiments of this invention, refer to... Figure 7 Multiple through holes 1 can be distributed in a lattice.

[0034] In some embodiments of this invention, the substrate 11 may be an N-type silicon wafer. In some embodiments, the thickness of the substrate 11 may be approximately 130 μm.

[0035] In some embodiments, reference Figures 1 to 5 The back side of the substrate 11 is provided with alternating P-regions 2, N-regions 3, and a spacer region 4 between them. The P-region 2 includes a first tunneling oxide layer 12, a first doped polysilicon layer 13, and a second electrode 17. The first doped polysilicon layer 13 is located on the side of the first tunneling oxide layer 12 away from the substrate 11, and the second electrode 17 is in contact with the first doped polysilicon layer 13. The N-region 3 includes a second tunneling oxide layer 14, a second doped polysilicon layer 15, and a third electrode 18. The second doped polysilicon layer 15 is located on the side of the second tunneling oxide layer 14 away from the substrate 11, and the third electrode 18 is in contact with the second doped polysilicon layer 15. The doping types of the first doped polysilicon layer 13 and the second doped polysilicon layer 15 are opposite. In some embodiments, the first doped polysilicon layer 13 is a P-type doped polysilicon layer, specifically a boron-doped polysilicon layer; the second doped polysilicon layer 15 is an N-type doped polysilicon layer, specifically a phosphorus-doped polysilicon layer. Thus, both the P-region and the N-region can transmit and collect current.

[0036] In some embodiments, the first tunneling oxide layer 13 may include silicon oxide, and further, the thickness of the first tunneling oxide layer may be 1.7 nm to 2.3 nm.

[0037] In some embodiments, the second tunneling oxide layer 15 may include silicon oxide, and further, the thickness of the second tunneling oxide layer 15 may be 1.65 nm to 2.25 nm.

[0038] In some embodiments, the first electrode 5, the second electrode 17, and the third electrode 18 can be metal electrodes, for example, the first electrode 5, the second electrode 17, and the third electrode 18 can all be silver electrodes.

[0039] In some embodiments of this utility model, reference is made to Figures 1 to 5 and Figure 7A back film 16 is disposed on the back side of the substrate 11. The back film 16 may include an aluminum oxide layer 16-1 and / or a silicon nitride layer 16-2. The back film 16 extends into the via 1, and is located between the first electrode 5 and the via wall in the via 1. Thus, the back film located in the via can passivate the via and, as a protective layer, electrically insulate the first electrode from the bottom battery.

[0040] In some embodiments of this invention, the thickness of the alumina layer 16-1 can be 4.2nm-4.4nm.

[0041] In some embodiments of this utility model, the silicon nitride layer 16-2 may include multiple sub-film layers stacked together. For example, it may include a first silicon nitride layer, a second silicon nitride layer and a third silicon nitride layer stacked sequentially. Each sub-film layer has a different refractive index and a thickness of 10nm-30nm. The overall thickness of the silicon nitride layer 16-2 may be 78nm-90nm and the refractive index may be 2.07-2.17.

[0042] In some embodiments of this utility model, reference is made to Figures 1 to 5 The top-mounted battery 20 includes a perovskite light-absorbing layer 21 and a transparent conductive oxide layer 25. In some embodiments of this invention, the material of the perovskite light-absorbing layer 21 can be ABX3, wherein A is a monovalent cation, including but not limited to one or more monovalent cation mixtures selected from cesium (Cs), rubidium (Rb), methylamino (CH3NH3), and formamidinyl (CH2(NH2)2); B is a divalent cation, including but not limited to one or more divalent cation mixtures selected from lead (Pb) and tin (Sn); and X is a monovalent anion, including but not limited to one or more monovalent anion mixtures selected from iodine (I), bromine (Br), chloride (Cl), fluorine (F), and thiocyanate (SCN). In some specific embodiments, the material of the perovskite light-absorbing layer 21 can be Cs. x FA 1-x Pb(I y Br 1-y 3, x and y are 0 and 1 respectively.

[0043] In some specific embodiments, the material of the perovskite light-absorbing layer 21 can be Cs. 0.22 FA 0.78 Pb(I 0.85 Br 0.15 3.

[0044] In some embodiments, the transparent conductive oxide layer 25 may include at least one selected from indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and antimony-doped tin oxide. These materials possess a certain degree of conductivity, enabling them to transmit current, and also exhibit good light transmittance, allowing light to pass through.

[0045] In some embodiments of this invention, the thickness of the transparent conductive oxide layer 25 can be 80nm-100nm, for example, the thickness of the transparent conductive oxide layer 25 can be 80nm, 85nm, 90nm, 95nm, 100nm, etc. Films of these thicknesses have good light transmittance, which is beneficial for improving the light utilization rate of the tandem solar cell.

[0046] In some embodiments of this utility model, reference is made to Figures 3 to 5 The unfilled portion of the through hole 1 allows light to pass through. Along the direction from the top cell 20 to the bottom cell 10 (X direction), the thickness of the transparent conductive oxide layer 25 in the through hole 1 can decrease. This increases the refraction and reflection of light in the through hole, thereby further improving the utilization rate of light.

[0047] In some embodiments of this utility model, reference is made to Figure 4 and Figure 5 The height d of the first electrode 5 extending into the through-hole 1 can be 15μm-40μm. For example, the height d of the first electrode 5 extending into the through-hole 1 can be 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, etc. Typically, the substrate thickness is above 100nm. With a smaller height of the first electrode 5 extending into the through-hole 1, most of the substrate at the hole wall is not blocked by the first electrode, which can further improve the utilization rate of light by the battery, thereby further improving the overall performance of the battery.

[0048] In some embodiments of this utility model, reference is made to Figures 1 to 5 The top cell 20 may include a tin oxide layer 24, which is located on the side of the perovskite light-absorbing layer 21 away from the bottom cell 10 and extends into the via 1. The tin oxide layer 24 in the via 1 is located between the transparent conductive oxide layer 25 and the via wall. The tin oxide layer has high density and hole blocking effect. The tin oxide layer located on the front side of the perovskite light-absorbing layer can play a tunneling, passivation, and protection role, and can effectively block the intrusion of water vapor and oxygen. The tin oxide layer located in the via can play a good protective role and can passivate the via.

[0049] In some embodiments of this invention, the thickness of the tin oxide layer 24 can be 10nm-20nm, for example, the thickness of the tin oxide layer 24 can be 10nm, 12nm, 15nm, 18nm, 20nm, etc. Tin oxide layers of the above thicknesses can provide good protection and effectively passivate vias.

[0050] In some embodiments of this utility model, reference is made to Figures 3 to 5Along the direction (X direction) from the top cell 20 to the bottom cell 10, the thickness of the tin oxide layer 24 in the through hole 1 decreases. Therefore, the portion of the through hole not filled by the first electrode can increase the refraction and reflection of light, thereby further improving light utilization.

[0051] In some embodiments of this utility model, reference is made to Figures 1 to 3 The tin oxide layer 24 can extend from the through-hole 1 to the back side of the tandem solar cell. In some other embodiments of this invention, reference is made to... Figure 4 The tin oxide layer 24 can extend from one end of the via 1 to the other end of the via. In some embodiments, reference... Figure 5 The tin oxide layer 24 can extend a certain distance from one end of the via 1 along the X direction, but not to the other end of the via 1, just enough to cover the top battery area at the via 1.

[0052] In some embodiments of this utility model, reference is made to Figures 1 to 4 The transparent conductive oxide layer 25 can extend from one end of the through-hole 1 to the other end of the through-hole 1. In some other embodiments of this utility model, reference is made to... Figure 5 The transparent conductive oxide layer 25 can extend a certain distance from one end of the through hole 1 along the X direction, but not to the other end of the through hole 1, as long as it can form good contact with the first electrode 5.

[0053] In some embodiments of this utility model, reference is made to Figures 1 to 5 The first electrode 5 has a first end 51, which is located on the back side of the substrate 11. The orthographic projection of the through hole 1 on the back side of the substrate 11 falls within the orthographic projection of the first end 51 on the back side of the substrate 11. The width of the first end is greater than the diameter of the through hole, which facilitates subsequent welding contact and helps to improve the overall structural stability of the tandem solar cell.

[0054] In some embodiments of this utility model, reference is made to Figures 1 to 5 The thickness h of the first end 51 is 5μm-8μm. For example, the thickness h of the first end can be 5μm, 6μm, 7μm, 8μm, etc. A thicker first end is beneficial to improving the contact effect, thereby further improving the performance of the battery.

[0055] In some embodiments of this utility model, reference is made to Figures 1 to 5The top cell 20 may further include a first transport layer 22 and a second transport layer 23. The first transport layer 22 is located on the side of the perovskite light-absorbing layer 21 near the bottom cell 10, and the second transport layer 23 is located between the perovskite light-absorbing layer 21 and the transparent conductive oxide layer 25. The first transport layer 22 transports holes, and the second transport layer 23 transports electrons, or vice versa. Thus, the two transport layers can transport electrons and holes respectively, promoting current collection.

[0056] In some embodiments of this utility model, reference is made to Figures 1 to 5 The tandem solar cell may further include a carrier transport layer 6, which is located between the bottom cell 10 and the top cell 20. In some embodiments, the carrier transport layer can recombine carriers (electrons or holes) collected by the front film layer of the bottom cell with carriers (holes or electrons) collected by the first transport layer, thereby reducing charge accumulation. In other embodiments, the carrier transport layer can provide a transport path for holes or electrons.

[0057] In some embodiments of this invention, the carrier transport layer 6 may include at least one of indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, and a doped polycrystalline silicon layer. The carrier transport layer formed by the above materials can serve as a carrier recombination interface, reducing charge accumulation, or it can provide a transport path for holes or electrons; furthermore, it can connect the top and bottom cells.

[0058] In some embodiments of this invention, the thickness of the carrier transport layer 6 is 5nm-10nm. For example, the thickness of the carrier transport layer 6 can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc. A thinner carrier transport layer increases light transmittance, reduces parasitic absorption, increases the number of photons captured by the bottom cell, and improves the bottom cell current. It can also shorten the carrier transport path, reduce interface resistance loss, and reduce surface roughness, resulting in tighter contact and reducing recombination caused by poor contact.

[0059] In some embodiments of this utility model, reference is made to Figures 1 to 5The tandem solar cell may further include a third doped polysilicon layer 7, which is located between the bottom cell 10 and the carrier transport layer 6. In some embodiments, the third doped polysilicon layer 7 may transport the opposite type of carrier to the first transport layer 22, and the carriers transported by both may recombine in the carrier transport layer 6. In some embodiments, the third doped polysilicon layer 7 may be an N-type doped polysilicon layer, such as a phosphorus-doped polysilicon layer, in which the third doped polysilicon layer 7 transports electrons and the first transport layer 22 transports holes. In other embodiments, the third doped polysilicon layer 7 may be a P-type doped polysilicon layer, such as a boron-doped polysilicon layer, in which the third doped polysilicon layer 7 transports holes and the first transport layer 22 transports electrons.

[0060] In other embodiments, the third doped polysilicon layer 7 may transmit the same type of carrier as the first transport layer 22. In some specific embodiments, both the third doped polysilicon layer 7 and the first transport layer 22 may transmit holes, and the carrier transport layer 6 may still provide a transport path for the holes collected by the first transport layer 22.

[0061] In some specific embodiments, the first transport layer 22 is a hole transport layer, such as a nickel oxide layer, with a thickness of 6nm-10nm; the second transport layer 23 is an electron transport layer, such as a C60 film layer, with a thickness of 15nm-30nm; and the third doped polysilicon layer 7 is a phosphorus-doped polysilicon layer.

[0062] In other specific embodiments, the first transport layer 22 is a hole transport layer, such as a nickel oxide layer, with a thickness of 6nm-10nm; the second transport layer 23 is an electron transport layer, such as a C60 film layer, with a thickness of 15nm-30nm; and the third doped polysilicon layer 7 is a boron doped polysilicon layer.

[0063] In some embodiments, reference Figures 1 to 5 The tandem solar cell may further include a third tunneling oxide layer 8, which is located between the carrier transport layer 6 and the bottom cell 10. In some specific embodiments, the third tunneling oxide layer 8 may include silicon oxide, and its thickness may be 1.65 nm to 2.25 nm.

[0064] In some embodiments, reference Figures 1 to 5 The third tunneling oxide layer 8 can be located between the third doped polysilicon layer 7 and the bottom cell 10.

[0065] In some embodiments of this utility model, reference is made to Figure 8 , Figure 8A through hole and its surrounding area are outlined in a circle. The tandem solar cell may also include a first negative electrode 31, a second negative electrode 32 and a positive electrode 40. The electrode of P region 2 is connected to the positive electrode 40 through a wire, the electrode of N region 3 is connected to the first negative electrode 31 through a conductive wire, and the electrode at the spacer region 4 is connected to the second negative electrode 32 through a wire.

[0066] This invention provides a method for preparing the aforementioned tandem solar cell. In some embodiments of this invention, the method for preparing the aforementioned tandem solar cell may include the following steps: S10: Drill holes in the substrate to form multiple through holes that penetrate the substrate.

[0067] In some embodiments, the substrate may be an N-type silicon wafer.

[0068] In some embodiments of this invention, laser drilling can be used to form multiple vias on a substrate, with the diameter of the vias ranging from 150 μm to 400 μm. In some embodiments, the multiple vias 1 can be arranged in a lattice pattern, such as... Figure 7 As shown. In other embodiments, the arrangement of the multiple through holes 1 can also be set and adjusted as needed.

[0069] In some embodiments of this invention, after forming multiple through holes, the substrate can be double-sided polished in a wet alkaline polishing tank. In some specific embodiments, the alkaline solution used for double-sided polishing is composed of H2O, NaOH, and polishing additives in a volume ratio of 450:30:5, the process time is 250s-400s, and the tank temperature of the wet alkaline polishing tank is 60℃-75℃.

[0070] S20: Alternating P-regions, N-regions, and spacer regions between the P-regions and N-regions are formed on the back side of the substrate to obtain the bottom cell.

[0071] In this invention, the orthographic projection of the through hole 1 on the back side of the substrate 11 is located in the spacer region 4.

[0072] In some embodiments of this utility model, step S20 may include the following steps: S21: Form the first tunneling oxide layer on the substrate.

[0073] In some specific embodiments, the first tunneling oxide layer (silicon oxide layer) can be prepared by low-pressure chemical vapor deposition, with a deposition time of 1000s-3000s, a deposition temperature of 590℃-630℃, and a thickness of 1.7nm-2.3nm.

[0074] S22: A first doped polysilicon layer and a borosilicate glass layer are formed on the side of the first tunneling oxide layer away from the substrate.

[0075] In some specific embodiments, a low-pressure chemical vapor deposition method can be used to form a polycrystalline silicon layer, with a deposition time of 11000s-13000s, a deposition temperature of 550℃-570℃, and a polycrystalline silicon layer thickness of 250nm-350nm. Subsequently, boron diffusion was performed. The pre-crystallization temperature was 950℃-980℃, and the crystallization time was 2500s-3000s; the diffusion temperature was 800℃-870℃, and the diffusion time was 300s-600s; the advance temperature was 930℃-960℃, and the advance time was 500s-800s; the oxidation temperature was 850℃-950℃, and the oxidation time was 3000s-3500s; the post-annealing temperature was 950℃-980℃, resulting in a first doped polycrystalline silicon layer (boron-doped polycrystalline silicon layer) and a BSG layer (borosilicate glass layer). The thickness of the BSG layer was 55nm-65nm, and the sheet resistance was 100Ω / □-140Ω / □.

[0076] S23: Remove the borosilicate glass layer and the first doped polysilicon layer from the N-region and the spacer region.

[0077] In some embodiments, a laser is used to remove the borosilicate glass layer in the N-region and the spacer region. The laser power is 40W-50W, the overlap rate is 50%-60%, the frequency is 500kHz-600kHz, and the pulse width is 0.8μs-1.2μs. Next, acid pickling is performed using a wet chain machine to remove BSG (including BSG in through holes) from the front and sides. The temperature of the wet acid tank chain machine is 20℃-50℃, and the overall process time is 50s-80s. The chain machine has two acid tanks. The acid solution in the first acid tank is composed of H2O and HF in a volume ratio of 2:5, and the acid solution in the second acid tank is composed of H2O and HF in a volume ratio of 3:4. Alkali washing is then performed using a wet alkaline washing machine to remove the first doped polysilicon layer on the front and sides, as well as the first doped polysilicon layer in the spacer region and N region. The temperature of the wet alkaline polishing tank is 50℃-75℃, and the process time is 200s-300s. The alkaline solution used for alkaline washing is composed of H2O, NaOH, and polishing additives in a volume ratio of 450:25:7.

[0078] S24: Formation of the second tunneling oxide layer.

[0079] In some embodiments of this invention, a second tunneling oxide layer (silicon oxide layer) can be prepared using a low-pressure chemical vapor deposition method, with a process time of 500s-1200s, a temperature of 590℃-630℃, and a thickness of 1.65-2.25nm.

[0080] S25: A second doped polysilicon layer and a phosphorus silica glass layer are formed on the side of the second tunneling oxide layer away from the substrate.

[0081] In some specific embodiments, a polycrystalline silicon layer can be formed using low-pressure chemical vapor deposition (LPCVD) with a deposition time of 3500-5000 s, a deposition temperature of 605℃-620℃, and a polycrystalline silicon layer thickness of 250 nm-310 nm. Subsequently, phosphorus diffusion is performed at a diffusion temperature of 800℃-820℃ and a diffusion time of 1200-1500 s, a drive-through temperature of 870℃-890℃ and a drive-through time of 800-1200 s, and an oxidation temperature of 910℃-930℃ and an oxidation time of 600-900 s, resulting in a second doped polycrystalline silicon layer and a phosphosilicate glass (PSG) layer. The PSG layer has a thickness of 45 nm-55 nm and a sheet resistance of 20 Ω / □-30 Ω / □.

[0082] S26: Remove the phosphorus silica glass layer and the second doped polycrystalline silicon layer from the P-region and the spacer region.

[0083] In some embodiments, a laser is used to remove the PSG layer in the back P-region and the spacer region. The laser power is 40W-50W, the overlap rate is 50%-60%, the frequency is 500kHz-600kHz, and the pulse width is 0.8μs-1.2μs. Then, a laminar flow chute is used to remove the second doped polysilicon layer in the side surfaces, P-region, and spacer region. The alkaline solution used is composed of H2O, NaOH, and polishing additives in a volume ratio of 470:6:11. The solution temperature is 70℃-80℃, and the process time is 450s-650s. Finally, an acid solution is used to remove the residual PSG on the front surface, the BSG in the back P-region, and the PSG in the N-region.

[0084] During the preparation of the second tunneling oxide layer in step 24 and the second doped polysilicon layer in step 25, a corresponding oxide layer and a doped polysilicon layer will also be formed on the front side of the substrate. In order to distinguish them from the film layers on the back side of the substrate, the two film layers on the front side of the substrate are respectively referred to as the third tunneling oxide layer and the third doped polysilicon layer.

[0085] S27: A back film is formed on the back side of the substrate, extending into the via.

[0086] In some embodiments of this invention, an aluminum oxide layer is formed on the back side of the substrate using a double-insertion method. The aluminum oxide layer can be prepared using atomic layer deposition (ALD) at a temperature of 300°C for 900 seconds, resulting in an aluminum oxide thickness of 4.3 ± 1 nm. Subsequently, a silicon nitride layer is formed on the side of the aluminum oxide layer furthest from the substrate. Specifically, a first silicon nitride layer, a second silicon nitride layer, and a third silicon nitride layer can be deposited sequentially from the substrate outwards at a temperature of 530°C. The three layers differ in refractive index, and their thicknesses are all between 10 nm and 30 nm. The final overall film thickness is 78 nm to 90 nm, with a refractive index of 2.07 to 2.17.

[0087] During the process of preparing an aluminum oxide layer on the back side of the substrate, an aluminum oxide layer will also be formed on the front side of the substrate. An acid solution can be used to remove the aluminum oxide layer that is coated on the front side of the substrate. The acid solution can be composed of H2O and HCl in a volume ratio of 3:4.

[0088] S28: Forms the second and third electrodes.

[0089] Metal gate lines are formed on the back side of a substrate using screen printing. High-temperature sintering then creates ohmic contacts between the metal and semiconductor layers (first and second doped polysilicon layers) to collect and conduct current. Typically, a three-pass printing process is used: the first pass prints the main gate on the back side of the substrate, with 9-24 gate lines; the second pass prints the N-region fine gate on the back side of the substrate, with 150-250 fine gate lines, a linewidth of 20-35 μm, and a height of 5-13 μm; the third pass prints the P-region fine gate on the back side of the substrate, with 150-250 fine gate lines, a linewidth of 20-35 μm, and a height of 4-13 μm. The peak sintering temperature is generally 680℃-750℃.

[0090] S30: A perovskite light-absorbing layer is formed on the front side of the substrate.

[0091] Before forming the perovskite light-absorbing layer, a carrier transport layer can be formed on the front side of the substrate. In some embodiments, the carrier transport layer is deposited on the front side of the substrate by magnetron sputtering at a sputtering pressure of 2 × 10⁻⁶. -4 -6×10 - 4 Pa, with a film thickness of 5-10 nm. In some embodiments, the film material can be selected from one or more of indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and antimony-doped tin oxide. In some embodiments, a doped polysilicon layer can be deposited on the front side of the substrate as a carrier transport layer. When a third doped polysilicon layer is formed on the front side of the substrate, the doping type of the doped polysilicon layer serving as the carrier transport layer is opposite to that of the third doped polysilicon layer.

[0092] In some embodiments of this invention, a first transport layer can be formed on the front side of the substrate before forming the perovskite light-absorbing layer. In some specific embodiments, the first transport layer can be a hole transport layer, which can be deposited on the front side of the substrate as a hole transport layer using magnetron sputtering at a sputtering pressure of 2 × 10⁻⁶. -4 -6×10 -4 Pa, sputtering oxygen partial pressure is 0.2%-0.6%, and sputtering film thickness is 6-10 nm.

[0093] In some embodiments of this invention, after forming the first transport layer, a modification layer can be formed on the side of the first transport layer away from the substrate. In some specific embodiments, a SAM (self-assembled monolayer) solution with a concentration of 0.5-1.5 mg / mL can be prepared and precisely sprayed onto the effective area by inkjet printing, followed by annealing on a hot plate at 100°C for 10 min, resulting in a film thickness of 1-3 nm. In some embodiments, the material of the modification layer may include one or more of the following: 2PACz, 4PACz, Me-4PACz, MeO-4PACz, Me-2PACz, 4PADCB, and MeO-2PACz.

[0094] In some embodiments of this utility model, the perovskite light-absorbing layer can be prepared by the following method: a perovskite precursor solution of appropriate concentration is prepared, with a solution concentration of 1.3-1.8M, and it is precisely coated on the substrate surface by inkjet printing. The film layer is pre-crystallized by VCD (Vacuum Condensation Device), and then the perovskite layer is crystallized by thermal annealing at a temperature of 100-130℃, with a film thickness of 500-1000nm.

[0095] In some embodiments of this invention, after forming the perovskite light-absorbing layer, a second transport layer is formed on the side of the perovskite light-absorbing layer away from the substrate. In some specific embodiments, the second transport layer can be an electron transport layer, which can be formed by depositing a C60 layer on the surface of the perovskite light-absorbing layer using vacuum evaporation, with a film thickness of 15-30 nm.

[0096] S40: Use a laser to process the opening area to remove the top battery film layer located in the opening area.

[0097] In some embodiments of this invention, a laser is used to remove residual top cell film layers (first transport layer, modification layer, perovskite light-absorbing layer, second transport layer, etc.) and carrier transport layer in the vias. When a back film is formed, the back film in the vias is retained during laser processing of the opening area to passivate the vias.

[0098] S50: A transparent conductive oxide layer is formed on the front side of the perovskite light-absorbing layer, and the transparent conductive oxide layer extends into the through hole.

[0099] In some embodiments of this invention, a transparent conductive oxide layer can be deposited on the side of the perovskite light-absorbing layer away from the substrate using magnetron sputtering, and the transparent conductive oxide layer can extend into the via. In some embodiments, the thickness of the transparent conductive oxide layer is 80 nm-100 nm.

[0100] In some embodiments, a transparent conductive oxide layer may be deposited in the direction from the top cell to the bottom cell, such that the thickness of the transparent conductive oxide layer in the via decreases in the direction from the top cell to the bottom cell.

[0101] In some embodiments, before forming the transparent conductive oxide layer, a tin oxide layer may be formed on the side of the perovskite light-absorbing layer away from the bottom cell and the tin oxide layer may extend into the via.

[0102] In some specific embodiments, an atomic layer deposition method can be used to deposit a tin oxide layer on the side of the perovskite light-absorbing layer away from the bottom cell, with a film thickness of 15 nm-20 nm. The tin oxide layer extends into the via as a protective layer. During the subsequent formation of the transparent conductive oxide layer using magnetron sputtering, the thickness of the tin oxide layer may be damaged to some extent, for example, reduced by 5 nm-10 nm, leaving a thinner tin oxide layer. In some embodiments, the thickness of this film layer in the via can decrease along the direction from the top cell to the bottom cell.

[0103] Tin oxide layers prepared by atomic layer deposition have high density and hole blocking effect, and can effectively block the intrusion of water vapor and oxygen, thus playing a good passivation role.

[0104] S60: Form the first electrode.

[0105] In this invention, the first electrode extends from the back side of the substrate into the via and contacts the transparent conductive oxide layer. The transparent conductive oxide layer can transmit the current collected on the front side of the top cell to the first electrode through the via.

[0106] In some embodiments of this utility model, reference is made to Figure 2 A first electrode 5 with a solid structure can be formed, which extends from one end of the through hole 1 to the other end of the through hole 1.

[0107] In other embodiments of this utility model, reference is made to Figure 1 The first electrode 5, which is at least partially hollow, can be formed, and the first electrode 5 extends from one end of the through hole 1 to the other end of the through hole 1.

[0108] In other embodiments of this utility model, reference is made to Figures 3 to 5 The first electrode paste can be filled into the via from the back side of the substrate, with the height of the first electrode paste filling the via being less than the height of the via, thus obtaining the first electrode. Compared to Figure 1 and Figure 2 The first electrode structure shown, Figures 3 to 5The first electrode in the cell can be obtained by increasing the viscosity of the electrode slurry. Electrode slurries with higher viscosity have poorer fluidity and flow from the back to the front of the cell. The height of the slurry extending into the through hole can be controlled by adjusting the preparation time.

[0109] The method proposed in this invention for fabricating tandem solar cells allows the transparent conductive oxide layer on the front side of the top cell to extend into the via, transmitting current to the first electrode via the via. Positioning the electrode on the back side reduces shading on the front side, improving the cell's light utilization efficiency (light absorption efficiency) and photoelectric conversion efficiency. Extending the first electrode into the via shortens the transmission distance of the transparent conductive oxide layer, reducing current loss due to its high resistance, thus achieving both improved light utilization and efficient current collection. If holes are drilled after cell fabrication, the perovskite's temperature sensitivity makes it difficult to reconcile the high-temperature deposition processes of alumina and silicon nitride after via formation, hindering the deposition of alumina and silicon nitride passivation structures within the vias. This invention, by drilling holes on the substrate first, allows for compatibility with the high-temperature deposition processes of alumina and silicon nitride. During backsheet fabrication, the alumina and silicon nitride films extend into the vias, passivating them and improving the cell's passivation effect.

[0110] In another aspect, this invention provides a photovoltaic module. In some embodiments, the photovoltaic module includes the aforementioned tandem solar cells. Thus, the photovoltaic module possesses all the features and advantages of the aforementioned tandem solar cells, which will not be repeated here.

[0111] In some embodiments of this invention, the photovoltaic module may include one or more tandem solar cells.

[0112] The present invention will be described below through specific embodiments. Those skilled in the art will understand that the following specific embodiments are merely illustrative and do not limit the scope of the present invention in any way. Furthermore, in the following embodiments, unless otherwise specified, the materials and equipment used are commercially available. If specific processing conditions and methods are not explicitly described in the later embodiments, conditions and methods known in the art can be used for processing.

[0113] Example 1 1. Drilling: Multiple through holes are made on an N-type silicon wafer using a laser, with the diameter of the through holes ranging from 150μm to 400μm.

[0114] 2. Double-sided polishing: N-type silicon wafers are double-sided polished in a wet alkaline polishing tank. The alkaline solution used is composed of H2O, NaOH and polishing additives in a volume ratio of 450:30:5. The process time is 300s, and the tank temperature of the wet alkaline polishing tank is 70℃.

[0115] 3. LP1 (First Low-Pressure Chemical Vapor Deposition): The deposition time of the first tunneling oxide layer (silicon oxide layer) is 1500s and the deposition temperature is 610℃; the deposition time of the polycrystalline silicon layer is 12000s and the deposition temperature is 560℃.

[0116] 4. Boron diffusion: The pre-crystallization temperature of boron diffusion is 965℃, and the crystallization time is 2800s; the diffusion temperature is 835℃, and the diffusion time is 450s; the advance temperature is 945℃, and the advance time is 650s; the oxidation temperature is 900℃, and the oxidation time is 3200s; the post-annealing temperature is 960℃, resulting in a P-type doped polycrystalline silicon layer (P-poly) and a BSG layer, with the BSG layer having a thickness of 60nm.

[0117] 5. First laser processing: The BSG in the back N region and the spacer region is removed by laser. The laser power is 45W, the overlap rate is 55%, the frequency is 550kHz, and the pulse width is 1μs.

[0118] 6. First cleaning treatment: Alkali washing is carried out by wet alkaline washing to remove P-poly in the N-zone. The tank temperature of the wet alkaline washing tank is 65℃, the process time is 250s, and the alkaline solution used for alkaline washing is composed of H2O, NaOH and polishing additives in a volume ratio of 450:25:7.

[0119] 7. LP2 (Second Low Pressure Chemical Vapor Deposition): The deposition time for the tunneling oxide layer (silicon oxide layer) is 1100s, and the temperature is 620℃. The tunneling oxide layer is formed on both the front and back sides of the silicon wafer; the deposition time for polycrystalline silicon is 4500s, and the deposition temperature is 610℃.

[0120] 8. Phosphorus diffusion: The diffusion temperature is 810℃ and the diffusion time is 1300s. The propagation temperature is 880℃ and the propagation time is 1000s. The oxidation temperature is 920℃ and the oxidation time is 700s. An N-type doped polysilicon layer (N-poly) and a PSG layer are formed on both the front and back sides of the silicon wafer. The thickness of the PSG layer is 50nm.

[0121] 9. Second laser processing: The PSG in the P-region and spacer region on the back of the silicon wafer is removed by laser. The laser power is 45W, the overlap rate is 55%, the frequency is 550kHz, and the pulse width is 1μs.

[0122] 10. Second cleaning process: Acid pickling is performed using a wet chain machine to remove PSG from the front and sides (including PSG in the through holes). The tank temperature of the wet acid tank chain machine is 30℃, and the overall process time is 70s. The chain machine has two acid tanks. The acid solution in the first acid tank is composed of H2O and HF in a volume ratio of 2:5, and the acid solution in the second acid tank is composed of H2O and HF in a volume ratio of 3:4. A pass-through machine is used to remove N-poly from the front, sides, P area, and interstitial areas. The alkaline solution used is composed of H2O, NaOH, and polishing additives in a volume ratio of 470:6:11. The solution temperature is 75℃, and the process time is 550s. Finally, acid solution is used to remove residual BSG from the front, BSG from the P area on the back, and PSG from the N area.

[0123] 11. Preparation of aluminum oxide layer: An aluminum oxide layer is deposited on the back side of the silicon wafer using the ALD process with a positive-to-positive double insertion method at a temperature of 300℃ and a process time of 900s.

[0124] 12. Preparation of silicon nitride layer: The deposition process temperature is 530℃, and it is divided into 3 layers. The deposition order from the silicon wafer outward is silicon nitride 1, silicon nitride 2, and silicon nitride 3. The difference between the 3 silicon nitride layers is the refractive index. The thickness of each layer is between 10-30nm, and the final overall film thickness is 84±6nm with a refractive index of 2.12±0.05.

[0125] 13. Removal of aluminum oxide: Use an acid solution to remove the aluminum oxide coating on the front side of the silicon wafer. The acid solution is composed of H2O and HCl in a volume ratio of 3:4.

[0126] 14. Metal grid lines are formed on the back of the silicon wafer by screen printing. After high-temperature sintering, the metal and semiconductor (boron-doped polycrystalline silicon layer and phosphorus-doped polycrystalline silicon layer) form an ohmic contact for collecting and discharging current.

[0127] 15. Fabrication of the carrier transport layer: A transparent conductive oxide transport layer was deposited on the P-poly surface on the front side of the silicon wafer using magnetron sputtering at a sputtering pressure of 4 × 10⁻⁶. -4 Pa, film thickness is 7 nm, film material is ITO (indium tin oxide).

[0128] 16. Preparation of the hole transport layer: Nickel oxide was deposited as the hole transport layer on the surface of the carrier transport layer using magnetron sputtering at a sputtering pressure of 3 × 10⁻⁶. -4 Pa, sputtering oxygen partial pressure is 0.4%, and film thickness is 8 nm.

[0129] 17. Preparation of the modified layer: Prepare a SAM (MeO-4PACz) solution with a concentration of 1 mg / mol, and spray it onto the hole transport layer by inkjet printing. Then, anneal it on a hot plate at 100℃ for 10 min to achieve a film thickness of 2 nm.

[0130] 18. Preparation of the perovskite absorbing layer: A perovskite precursor solution with a concentration of 1.5 M was prepared and sprayed onto the modification layer using inkjet printing. The film was pre-crystallized, and then thermally annealed at 120℃ to crystallize the film and form the perovskite absorbing layer. The film thickness was 700 nm. The material of the prepared perovskite absorbing layer was Cs. 0.22 FA 0.78 Pb(I 0.85 Br 0.15 )3 (1.68eV wide bandwidth).

[0131] 19. Preparation of electron transport layer: A C60 layer with a thickness of 20 nm was deposited on the surface of the perovskite light-absorbing layer by vacuum evaporation.

[0132] 20. Third laser treatment: Use a laser to process the opening area to remove the residual top cell film layer in the through hole and retain the bottom cell passivation film layer (alumina layer and silicon nitride layer).

[0133] 21. Preparation of tin oxide layer: A SnO2 film with a thickness of 20 nm is deposited on the surface of C60 film using atomic layer deposition. The film covers the C60 surface and extends into the via, forming a passivation protective layer.

[0134] 22. Preparation of transparent conductive oxide layer: A transparent conductive oxide layer is deposited on the surface of tin oxide layer by magnetron sputtering. The film thickness is 80-100 nm and extends into the via. Along the direction from the top cell to the bottom cell, the thickness of the transparent conductive oxide layer in the via shows a decreasing trend.

[0135] 23. Fabrication of the first electrode: The first electrode is fabricated using low-temperature silver paste, and a contact point is formed at the bottom cell end. The first electrode extends from one side of the back of the silicon wafer into the through-hole. The structure of the first electrode in Example 1 is as follows. Figure 1 As shown.

[0136] Example 2 The difference from Example 1 is that in step 23, the viscosity of the low-temperature silver paste is increased, resulting in the structure of the first electrode as shown in Example 1. Figure 3 As shown, the remaining parameters and steps are the same as in Example 1.

[0137] Comparative Example 1 In Comparative Example 1, no holes were drilled in the silicon wafer. Double-sided polishing and subsequent film preparation were performed directly. The preparation parameters and conditions for each film layer were the same as in Example 1. After forming a transparent conductive oxide layer, the electrode of the top cell was formed on the front side.

[0138] The batteries prepared in the examples and comparative examples were subjected to performance tests, and the test results are recorded in Table 1.

[0139] Table 1

[0140] Table 1 shows various test data for the top and bottom batteries in Examples 1-2 and Comparative Example 1.

[0141] As shown in Table 1, compared with Comparative Example 1, in Examples 1 and 2, by drilling holes in the silicon wafer and placing the silver electrode on the front side of the top cell on the back side of the stacked cell, the absorption and utilization of light by the cell can be improved, thereby increasing the overall photoelectric conversion efficiency of the stacked cell. Compared with Example 1, in Example 2, the silver electrode only fills a portion of the through hole, which can further improve the utilization rate of light by the cell, thereby further improving the photoelectric conversion efficiency of the cell.

[0142] In the description of this utility model, the terms "front", "back", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and do not require that this utility model must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this utility model.

[0143] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," and "other embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction. Additionally, it should be noted that in this specification, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0144] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A tandem solar cell, characterized in that, The stacked solar cell has multiple through holes, and the stacked solar cell includes a bottom cell and a top cell stacked together, with the multiple through holes penetrating the top cell and the bottom cell; The bottom battery includes a substrate, and the back side of the substrate is provided with alternating P regions, N regions and a spacer region located between the P regions and N regions. The orthographic projection of the via on the back side of the substrate is located in the spacer region. The top battery includes a perovskite light-absorbing layer, and a transparent conductive oxide layer is disposed on the front side of the perovskite light-absorbing layer, the transparent conductive oxide layer extending into the through hole; The tandem solar cell includes a first electrode that extends from the back side of the substrate into the via and contacts the transparent conductive oxide layer.

2. The tandem solar cell according to claim 1, characterized in that, One of the following conditions must be met: The first electrode is a solid electrode, and the first electrode extends from one end of the through hole to the other end of the through hole; At least a portion of the first electrode is a hollow structure, and the first electrode extends from one end of the through hole to the other end of the through hole; The height to which the first electrode extends into the through hole is less than the height of the through hole.

3. The tandem solar cell according to claim 1, characterized in that, At least one of the following conditions must be met: A back film is disposed on the back side of the substrate, the back film comprising an aluminum oxide layer and / or a silicon nitride layer, the back film extending into the via, and in the via, the back film being located between the first electrode and the via wall; The top cell includes a tin oxide layer located on the side of the perovskite light-absorbing layer away from the bottom cell and extending into the through hole. The tin oxide layer in the through hole is located between the transparent conductive oxide layer and the hole wall. The transparent conductive oxide layer includes at least one of indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and antimony-doped tin oxide. Along the direction from the top cell to the bottom cell, the thickness of the transparent conductive oxide layer in the through hole shows a decreasing trend; The diameter of the through hole is 150μm-400μm; The height of the first electrode extending into the through hole is 15μm-40μm; The first electrode has a first end located on the back side of the substrate, and the orthographic projection of the via on the back side of the substrate falls within the orthographic projection of the first end on the back side of the substrate.

4. The tandem solar cell according to claim 3, characterized in that, The thickness of the tin oxide layer is 10nm-20nm; And / or, the thickness of the first end is 5μm-8μm; And / or, along the direction from the top cell to the bottom cell, the thickness of the tin oxide layer in the via shows a decreasing trend.

5. The tandem solar cell according to any one of claims 1-4, characterized in that, The P region includes a first tunneling oxide layer, a first doped polysilicon layer, and a second electrode. The first doped polysilicon layer is located on the side of the first tunneling oxide layer away from the substrate, and the second electrode is in contact with the first doped polysilicon layer. The N-region includes a second tunneling oxide layer, a second doped polysilicon layer, and a third electrode. The second doped polysilicon layer is located on the side of the second tunneling oxide layer away from the substrate. The third electrode is in contact with the second doped polysilicon layer. The doping types of the first doped polysilicon layer and the second doped polysilicon layer are opposite. The top cell further includes a first transport layer and a second transport layer. The first transport layer is located on the side of the perovskite light-absorbing layer near the bottom cell. The second transport layer is located between the perovskite light-absorbing layer and the transparent conductive oxide layer. The first transport layer transports holes and the second transport layer transports electrons, or the first transport layer transports electrons and the second transport layer transports holes.

6. The tandem solar cell according to any one of claims 1-4, characterized in that, The tandem solar cell further includes a carrier transport layer located between the bottom cell and the top cell.

7. The tandem solar cell according to claim 6, characterized in that, The carrier transport layer includes at least one of indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, and a doped polysilicon layer. And / or, the thickness of the carrier transport layer is 5nm-10nm.

8. The tandem solar cell according to claim 6, characterized in that, The tandem solar cell further includes a third doped polycrystalline silicon layer, which is located between the bottom cell and the carrier transport layer.

9. The tandem solar cell according to claim 8, characterized in that, The tandem solar cell further includes a third tunneling oxide layer, which is located between the carrier transport layer and the bottom cell.

10. A photovoltaic module, characterized in that, The tandem solar cell includes any one of claims 1-9.

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