Wafer test structure and semiconductor chip

Abstract

The utility model provides a kind of wafer test structure and semiconductor chip, specifically related to semiconductor technical field.The wafer test structure includes: first metal layer, second metal layer and a plurality of metal vias, the first metal layer includes a plurality of first metal conductive wires arranged at intervals, the second metal layer is set to the top of the first metal layer, and the second metal layer includes a plurality of second metal conductive wires arranged at intervals;A plurality of the metal vias are arranged between the first metal layer and the second metal layer;Wherein, each the first metal conductive wire and the second metal conductive wire corresponding thereto are connected to form an independent closed loop structure by two adjacent metal vias.The test structure can effectively detect whether there is a defect in the metal via through the difference between bright and dark imaging of electron beam defect scanning machine.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, specifically to a wafer testing structure and a semiconductor chip. Background Technology

[0002] Semiconductor devices may encounter various defects during fabrication, such as via defects. Therefore, after fabrication, devices must undergo wafer acceptance testing (WAT) to verify their operational capability. Test structures are indispensable for the reliability assessment of semiconductor integrated circuits.

[0003] Through-hole chains are a commonly used testing structure, typically used in conjunction with an electron beam defect scanner to detect defects in metal through-holes. Because the metal wires in the through-hole chain test structure are connected to measuring electrodes (WAT PADs) at both ends, electrons from the metal wires are continuously replenished from the outside through the measuring electrodes during the test. Even if defects exist in the metal through-hole, the electron beam defect scanner will detect these external electrons and display the metal wire image as bright (e.g., ...). Figure 1 As shown in the figure, this makes it impossible to determine whether there are defects in the metal through-hole.

[0004] Therefore, there is a need to provide a wafer testing structure to improve the capture rate of via defects. Utility Model Content

[0005] In view of the problems existing in the prior art, the present invention provides a wafer testing structure and semiconductor chip to improve the problem that electron beam defect scanners cannot effectively identify via defects.

[0006] To achieve the above and other related objectives, this utility model provides a wafer testing structure, which includes a first metal layer, a second metal layer, and a plurality of metal vias. The first metal layer includes a plurality of spaced-apart first metal wires. The second metal layer is disposed above the first metal layer and includes a plurality of spaced-apart second metal wires. The plurality of metal vias are spaced apart between the first metal layer and the second metal layer. Each first metal wire and its corresponding second metal wire are connected through two adjacent metal vias to form an independent closed-loop structure.

[0007] In one embodiment of the present invention, the orthographic projection of the second metal wire onto the first metal layer at least partially overlaps with the first metal wire below the second metal wire.

[0008] In one embodiment of the present invention, the orthographic projection of the second metal wire onto the first metal layer completely overlaps with the first metal wire below the second metal wire.

[0009] In one embodiment of the present invention, a plurality of first metal wires are arranged in an array, a plurality of second metal wires are arranged in an array, and the second metal wires extend in the same direction as the first metal wires.

[0010] In one embodiment of the present invention, both the first metal wire and the second metal wire extend laterally.

[0011] In one embodiment of the present invention, each closed-loop structure includes a first metal wire, a second metal wire, and two adjacent metal through holes. The tops of the two metal through holes are respectively connected to the second metal wire of the closed-loop structure, and the bottoms of the two metal through holes are respectively connected to the first metal wire of the closed-loop structure.

[0012] In one embodiment of this utility model, adjacent closed-loop structures are independent of each other.

[0013] In one embodiment of this utility model, the materials of the first metal wire, the second metal wire, and the metal through hole each independently include copper or aluminum.

[0014] In one embodiment of the present invention, the wafer testing structure further includes an insulating dielectric layer, wherein the first metal layer, the second metal layer, and a plurality of metal vias are all formed in the insulating dielectric layer.

[0015] This utility model also provides a semiconductor chip, which includes any of the wafer testing structures described above.

[0016] This invention's wafer testing structure connects each first metal wire in the first metal layer and its corresponding second metal wire in the second metal layer through metal vias to form a closed-loop structure. Furthermore, the metal wires in the same layer are spaced apart, eliminating the need for measurement electrodes and creating a relatively independent upper and lower layer connection structure. An unexpected benefit is that the entire testing structure receives no external electron supplementation. When a defect appears in the metal via, the electron beam defect scanner's emitted electrons remain between the defect and the independent metal wires. In this case, the electron beam defect scanner cannot collect secondary electrons, and the image of the metal wire is dark. If there is no defect in the metal via, the electron beam defect scanner can collect secondary electrons, and the image of the metal wire is bright. Utilizing the difference in brightness between the two images obtained by the electron beam defect scanner, defects in the vias can be effectively detected, thereby improving the via defect capture rate.

[0017] In addition, the wafer testing structure of this invention can be designed in advance to achieve the effect of throttling the electron source. After the wafer fabrication, there is no need to perform other electron source throttling actions, such as focused ion beam cutting process or pad grounding treatment, which makes it more feasible and reliable. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a wafer testing structure in the prior art when a metal via defect is detected by an electron beam defect scanner.

[0020] Figure 2 This is a schematic diagram of the wafer testing structure of this utility model in one embodiment;

[0021] Figure 3 This is a top view schematic diagram of the wafer testing structure of this utility model in one embodiment;

[0022] Figure 4 This is a schematic diagram of the wafer testing structure of this utility model in another embodiment;

[0023] Figure 5 This is a schematic diagram of the wafer testing structure of this utility model in yet another embodiment;

[0024] Figure 6 This is a schematic diagram of a wafer testing structure according to one embodiment of the present invention when a metal via defect is detected by an electron beam defect scanner.

[0025] Component designation explanation:

[0026] 100, First metal layer; 110, First metal conductor; 200, Second metal layer; 210, Second metal conductor; 300, Metal via; 310, Closed-loop structure; a, Defect. Detailed Implementation

[0027] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. It should also be understood that the terminology used in the embodiments of this utility model is for describing specific implementation schemes and not for limiting the scope of protection of this utility model. Test methods in the following embodiments that do not specify specific conditions are generally performed under conventional conditions or according to the conditions recommended by the respective manufacturers.

[0028] When numerical ranges are given in the embodiments, it should be understood that, unless otherwise specified in this invention, both endpoints of each numerical range and any value between the two endpoints may be selected. Unless otherwise defined, all technical and scientific terms used in this invention, as well as the prior art known to those skilled in the art and the description of this invention, may be implemented using any prior art methods, equipment, and materials similar to or equivalent to those in the embodiments of this invention.

[0029] It should be noted that the terms such as "upper", "lower", "left", "right", "middle" and "one" used in this specification are only for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered as within the scope of implementation of this utility model.

[0030] The wafer test structure is a via array test structure similar to the actual metal interconnect structure, designed in a similar manner to the metal interconnect structure. This wafer test structure is formed simultaneously with the metal interconnect structure. Through a single test structure, the vias between the metal layers in a multilayer metal interconnect process can be effectively tested.

[0031] like Figure 1 As shown, in existing test structures, the metal wires of the front layer metal and the metal wires of the current layer metal are staggered and connected end-to-end through metal vias to form a series chain structure. Measurement electrodes are placed at both ends of the chain structure, and external testing equipment is directly or indirectly connected to these electrodes for metal via defect testing. When using an electron beam defect scanner to detect defects in a metal via, electrons from the current layer metal wires are continuously replenished from the outside through the measurement electrodes. This ensures that even if defect 'a' exists in the metal via, the image of the current layer metal wires detected by the electron beam defect scanner remains bright (e.g., ...). Figure 1As shown, Figure 1 The direction indicated by the middle arrow is the direction of electron movement, making it impossible to determine whether there are defects in the metal through-hole.

[0032] To address the aforementioned problems, this invention provides a wafer testing structure and a semiconductor chip incorporating the wafer testing structure. This wafer testing structure does not involve external electron supplementation. When a defect exists in a metal via, the image of the metal conductor detected by the electron beam defect scanner is dark; when there is no defect in the metal via, the image of the metal conductor detected by the electron beam defect scanner is bright. By utilizing the difference in brightness between the bright and dark images detected by the electron beam defect scanner, the presence of defects in the metal via can be effectively detected.

[0033] Please see Figure 2 The wafer testing structure provided by this utility model includes a first metal layer 100, a second metal layer 200, and a plurality of metal vias 300. The first metal layer 100 includes a plurality of spaced-apart first metal wires 110. The second metal layer 200 is disposed above the first metal layer 100 and includes a plurality of second metal wires 210. The plurality of metal vias 300 are spaced-apart between the first metal layer 100 and the second metal layer 200. Each first metal wire 110 in the first metal layer 100 and its corresponding second metal wire 210 in the second metal layer 200 are connected by two adjacent metal vias 300 to form independent upper and lower closed-loop structures 310. It should be noted that the first metal layer 100 and the second metal layer 200 in this application are not used to limit the number of metal layers, but only to illustrate the relationship between the metal layers. For example, the second metal layer 200 represents the current metal layer, and the first metal layer 100 represents the adjacent and lower front metal layer; or the first metal layer 100 represents the current metal layer, and the second metal layer 200 represents the adjacent and upper back metal layer.

[0034] The materials of the first metal layer 100, the second metal layer 200, and the metal via 300 can be any material with excellent electrical conductivity, such as copper (Cu), aluminum (Al), tungsten (W), etc. These materials can be the same or different. For example, the first metal layer 100 is made of Cu, and the Cu metal layer can be formed using a corresponding Cu interconnect process. The second metal layer 200 is made of Al, and the Al metal layer can be formed using a corresponding Al interconnect process. The metal via 300 is made of Cu, and the Cu via can be formed using a corresponding via process, such as a damascus inlay process. It is understood that the materials and formation processes of the first metal layer 100, the second metal layer 200, and the metal via 300 must be consistent with the corresponding device structure.

[0035] Please see Figure 2 and Figure 3 In one embodiment, a plurality of first metal wires 110 in the first metal layer 100 are arranged in an array, and the shapes of the first metal wires 110 are regular shapes, such as rectangles, squares, or trapezoids. Second metal wires 210 in the second metal layer 200 are also arranged in an array, and the shapes of the second metal wires 210 are also regular shapes, such as rectangles, squares, or trapezoids. The shape of the second metal wires 210 can be the same as or different from the shape of the first metal wires 110. For example, both the first metal wires 110 and the second metal wires 210 are rectangles, or the first metal wires 110 are rectangles and the second metal wires 210 are squares. Further, the first metal wires 110 and the second metal wires 210 extend in the same direction. For example, both the first metal wires 110 and the second metal wires 210 extend laterally, or both extend longitudinally. The extension direction of the metal through-hole 300 is perpendicular to the extension direction of the metal wire, and the top end of the metal through-hole 300 is connected to the second metal wire 210, while the bottom end of the metal through-hole 300 is connected to the first metal wire 110. A plurality of metal through-holes 300 are arranged at intervals along the extension direction of the metal wire. Since each first metal wire 110 of the first metal layer 100 forms a closed structure with one second metal wire 210 and two metal through-holes 300 of the second metal layer 200, the number of first metal wires 110 is the same as the number of second metal wires 210, and the number of metal through-holes 300 is twice the number of first metal wires 110 or second metal wires 210.

[0036] Please see Figures 2 to 5 In one embodiment, the orthographic projection of each second metal wire 210 in the second metal layer 200 onto the first metal layer 100 at least partially overlaps with the first metal wire 110 below the second metal wire 210, that is, there is an overlapping area between the second metal wire 210 and the first metal wire 110, and the area of ​​the overlapping area is at least large enough to allow for the provision of two metal vias 300, so that the first metal wire 110 and the second metal wire 210 form a closed loop through the two metal vias 300.

[0037] Please see Figure 2 and Figure 3 For example, the orthographic projection of the second metal wire 210 onto the first metal layer 100 completely coincides with the first metal wire 110 below the second metal wire 210, that is, the second metal wire 210 and the first metal wire 110 have the same size and shape, and the second metal wire 210 and the first metal wire 110 are arranged in a one-to-one correspondence. The two metal through holes 300 are arranged perpendicular to the extension direction of the metal wires, therefore... Figure 3In the top view, the first metal wire 110 and the second metal wire 210 completely overlap.

[0038] Please see Figure 4 For example, the second metal wire 210 is provided in a one-to-one correspondence with the first metal wire 110, but the size of the second metal wire 210 is larger or smaller than the first metal wire 110. Two metal through holes 300 are provided at intervals between the first metal wire 110 and the second metal wire 210, and the top of the metal through hole 300 is connected to the second metal wire 210, and the bottom of the metal through hole 300 is connected to the first metal wire 110.

[0039] Please see Figure 5 For example, the second metal wire 210 is offset from the first metal wire 110, and there is an overlapping area between the second metal wire 210 and the first metal wire 110. Two metal through holes 300 are spaced apart in the overlapping area of ​​the first metal wire 110 and the second metal wire 210, and the top of the metal through hole 300 is connected to the second metal wire 210, and the bottom of the metal through hole 300 is connected to the first metal wire 110.

[0040] In one embodiment, the wafer testing structure further includes an insulating dielectric layer (not shown in the figure), in which a first metal layer 100, a second metal layer 200 and a plurality of metal vias 300 are formed, and the insulating dielectric layer electrically isolates each of the first metal wires 110, the second metal wires 210 and the metal vias 300.

[0041] See Figure 6 When using the wafer testing structure of this invention for testing, an electron beam defect scanner is used to irradiate each closed-loop structure of the test structure. Since the closed-loop structures 310 do not interfere with each other and there is no external electron injection, when there is a defect a in the metal via 300 of the closed-loop structure 310, the electron emitted by the electron beam defect scanner will remain in the defect and the metal wire of the closed-loop structure 310. At this time, the electron beam defect scanner cannot collect secondary electrons, and the image of the metal wire is dark. If there is no defect in the metal via 300 of the closed-loop structure 310, the electron beam defect scanner can collect secondary electrons, and the image of the metal wire is bright. Thus, the presence of a defect in the metal via 300 can be determined based on the difference in brightness of the electron beam defect scanner's image.

[0042] While the above embodiments describe a wafer test structure formed by two metal layers and a metal via between the metal layers, the scope of this invention is not limited thereto. This invention may also include three or more metal layers, wherein any two metal layers and the metal via between them can form a test structure.

[0043] This invention also provides a semiconductor chip, which includes a semiconductor structure and a test structure formed on the semiconductor structure. The test structure may be any of the wafer test structures described above.

[0044] The wafer testing structure provided by this invention connects each first metal wire in the first metal layer and its corresponding second metal wire in the second metal layer through metal vias to form a closed-loop structure. The metal wires in the same layer are spaced apart, eliminating the need for measurement electrodes and creating a relatively independent upper and lower layer connection structure. Since there is no external electron supplementation in the entire testing structure, when a defect appears in the metal via, the electron beam defect scanner emits electrons that remain between the defect and the independent metal wires. In this case, the electron beam defect scanner cannot collect secondary electrons, and the image of the metal wire is dark. If there is no defect in the metal via, the electron beam defect scanner can collect secondary electrons, and the image of the metal wire is bright. By utilizing the difference in brightness between the bright and dark images of the electron beam defect scanner, defects in the via can be effectively detected. Therefore, this invention effectively overcomes some practical problems in the prior art, thus having high utilization value and practical significance.

[0045] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A wafer testing structure, characterized in that, include: The first metal layer includes a plurality of first metal wires arranged at intervals; A second metal layer is disposed above the first metal layer, and the second metal layer includes a plurality of second metal wires arranged at intervals; A plurality of metal through-holes are spaced apart between the first metal layer and the second metal layer; Each of the first metal wires and its corresponding second metal wires is connected through two adjacent metal through holes to form an independent closed-loop structure.

2. The wafer testing structure according to claim 1, characterized in that, The orthographic projection of the second metal wire onto the first metal layer at least partially overlaps with the first metal wire below the second metal wire.

3. The wafer testing structure according to claim 2, characterized in that, The orthographic projection of the second metal wire onto the first metal layer completely coincides with the first metal wire below the second metal wire.

4. The wafer testing structure according to any one of claims 1-3, characterized in that, A plurality of the first metal wires are arranged in an array, and a plurality of the second metal wires are arranged in an array, wherein the extension direction of the second metal wires is the same as the extension direction of the first metal wires.

5. The wafer testing structure according to claim 4, characterized in that, Both the first metal wire and the second metal wire extend laterally.

6. The wafer testing structure according to claim 1, characterized in that, Each of the closed-loop structures includes a first metal wire, a second metal wire, and two adjacent metal through holes. The tops of the two metal through holes are respectively connected to the second metal wire of the closed-loop structure, and the bottoms of the two metal through holes are respectively connected to the first metal wire of the closed-loop structure.

7. The wafer testing structure according to claim 6, characterized in that, The adjacent closed-loop structures are independent of each other.

8. The wafer testing structure according to claim 1, characterized in that, The materials of the first metal wire, the second metal wire, and the metal through-hole each independently include copper or aluminum.

9. The wafer testing structure according to claim 1, characterized in that, The wafer testing structure further includes an insulating dielectric layer, in which the first metal layer, the second metal layer, and a plurality of metal vias are formed.

10. A semiconductor chip, characterized in that, The semiconductor chip includes the wafer testing structure according to any one of claims 1-9.

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