Integrated circuit device

Abstract

According to some embodiments of this disclosure, an integrated circuit device includes a first power rail, a second power rail, and a third power rail. A plurality of active regions extend above a substrate, and a plurality of conductive contacts extend above the first and second active regions. A first via is connected to the first conductive contact and the third power rail. A second via is connected to the second conductive contact and the third power rail. A first portion of the first conductive contact on a second side of the third power rail is electrically disconnected from the first via, and a second portion of the second conductive contact on a first side of the third power rail is electrically disconnected from the second via.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device, and more particularly to an integrated circuit device having a power grid. Background Technology

[0002] For the operation of integrated circuits (ICs), power is supplied and distributed among the various devices within the IC, including the proper allocation of operating voltages VDD and VSS. The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby integrating more devices into a given area. As IC performance and design complexity increase, so do power consumption requirements and complexity. Sometimes, complex power distribution schemes are employed to distribute power and other signals to these components, such as power grid arrangements, where operating voltages VDD and VSS are distributed by the power structure forming the grid. Utility Model Content

[0003] According to some embodiments of this disclosure, an integrated circuit device is provided, including a substrate, and having a first power rail, a second power rail, and a third power rail extending parallel to each other over the substrate along a first direction. The third power rail is located between the first and second power rails in a second direction, which intersects the first direction. A plurality of active regions extend over the substrate in the first direction and include a first active region on a first side of the third power rail and a second active region on a second side of the third power rail opposite to the first side. A plurality of gate structures extend over the substrate in the second direction and include a first gate structure. A plurality of conductive contacts extend over the first and second active regions in the second direction to form source / drain regions. The plurality of conductive contacts include a first conductive contact on a first side of the first gate structure and a second conductive contact adjacent to the first conductive contact on a second side of the first gate structure. A first via extends upward in a third direction and connects to the first conductive contact and the third power rail, the third direction intersects the first and second directions. A second via extends upward in a third direction and connects to the second conductive contact and the third power rail. The first portion of the first conductive contact on the second side of the third power rail is electrically disconnected from the first through hole, and the second portion of the second conductive contact on the first side of the third power rail is electrically disconnected from the second through hole.

[0004] According to some embodiments of this disclosure, an integrated circuit device is provided, including a substrate, and having a first power rail, a second power rail, and a third power rail extending parallel to each other in a first direction above the substrate. The third power rail is located between the first and second power rails in a second direction, which intersects the first direction. A plurality of active regions extend above the substrate along the first direction. The active regions include a first active region on a first side of the third power rail and a second active region on a second side of the third power rail opposite to the first side. A plurality of gate structures extend above the substrate in the second direction and are connected to the first and second active regions, including the first gate structure. A plurality of conductive contacts extend above the substrate in the second direction and are connected to the first and second active regions to form source / drain regions. The plurality of conductive contacts include a first conductive contact on a first side of the first gate structure and a second conductive contact adjacent to the first conductive contact on a second side of the first gate structure. A first via extends upward in a third direction and is connected to the first conductive contact and the third power rail, which intersects the first and second directions. A second via extends upward in a third direction and is connected to the second conductive contact and the third power rail. The first via is connected to the second via in the second direction.

[0005] According to some embodiments of this disclosure, an integrated circuit device is provided, including a substrate, and having a first power rail, a second power rail, and a third power rail extending parallel to each other along a first direction above the substrate. The third power rail is located between the first and second power rails in a second direction, which intersects the first direction. A plurality of active regions extend above the substrate in the first direction and include a first active region on a first side of the third power rail and a second active region on a second side of the third power rail opposite to the first side. A plurality of gate structures extend above the substrate in the second direction, including a first gate structure. A plurality of conductive contacts extend above the first and second active regions in the second direction to form source / drain regions. A first via extends upward in a third direction and connects to the conductive contacts and the third power rail, which intersects the first and second directions. A second via extends upward in a third direction and connects to the conductive contacts and the third power rail. A fourth power rail extends along the second direction and is located between the first and second power rails, with the third power rail on a first side of the substrate along the third direction and the fourth power rail on a second side of the substrate, which is opposite to the first side. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Furthermore, the accompanying drawings are illustrative of embodiments of this disclosure and are not intended to be limiting.

[0007] Figure 1 A schematic diagram of an IC device including a power grid according to a disclosed embodiment is shown conceptually.

[0008] Figure 2A According to the disclosed embodiments Figure 1 A top view of an example of an IC device shown;

[0009] Figure 2B According to the disclosed embodiments Figure 2A The first cross-sectional view of the IC device shown;

[0010] Figure 2C According to the disclosed embodiments Figure 2A The second cross-sectional view of the IC device shown;

[0011] Figure 3 yes Figure 2A An alternative second cross-sectional view of the IC device shown;

[0012] Figure 4 According to the disclosed embodiments Figure 2A An alternative second cross-sectional view of the IC device shown;

[0013] Figure 5 According to the disclosed embodiments Figure 2A Bottom view of an example of the back of the IC device shown;

[0014] Figure 6 According to the disclosed embodiments Figure 2A and Figure 5 First cross-sectional view of the IC device shown;

[0015] Figure 7 According to the disclosed embodiments Figure 2A and Figure 5 An alternative first cross-sectional view of the IC device shown;

[0016] Figure 8 According to the disclosed embodiments Figure 2A and Figure 5 Second cross-sectional view of the IC device shown;

[0017] Figure 9 This is an exemplary top view of another IC device shown according to the disclosed embodiments;

[0018] Figure 10 According to the disclosed embodiments Figure 9 Bottom view of an example of the back of the IC device shown;

[0019] Figure 11 This is a block diagram of an IC device shown according to the disclosed embodiments;

[0020] Figure 12 This is a flowchart of an exemplary method for forming an IC including a power grid, according to the disclosed embodiments.

[0021] [Symbol Explanation]

[0022] 100: Device

[0023] 100a: Upper unit

[0024] 100b: Lower device

[0025] 102: Back

[0026] 110:Substrate

[0027] 112: Conductive contact

[0028] 112a: Conductive contact, first conductive contact

[0029] 112a1: Part 1

[0030] 112b: Conductive contact, second conductive contact

[0031] 112b2: Part Two

[0032] 112c: Conductive contact

[0033] 112d: Conductive contact

[0034] 116: Power rail, first power rail

[0035] 118: Power rail, third power rail

[0036] 119: Power rail, fourth power rail

[0037] 119a: Power rail, fifth power rail

[0038] 120: Power rail, second power rail

[0039] 200: Power Grid

[0040] 210: Through hole

[0041] 211: Backside through hole

[0042] 211a: First back-side through hole

[0043] 211b: Second back-side through hole

[0044] 212: Through hole

[0045] 212a: Through hole, first through hole

[0046] 212b: Through hole, second through hole

[0047] 214: Through hole

[0048] 214a: Through hole

[0049] 216: Transistor, First Transistor

[0050] 216a: Transistor

[0051] 216b: Transistor

[0052] 216c: Transistor

[0053] 216d: Transistor

[0054] 218: Separated structure, interrupted structure, CMD, cut metal structure

[0055] 218a:CMD

[0056] 218b:CMD

[0057] 218c:CMD

[0058] 218d:CMD

[0059] 220: Transistor, second transistor

[0060] 220a: Transistor

[0061] 312: Active Region, First Active Region

[0062] 316: Active region, second active region

[0063] 318: Gate structure

[0064] 318a: First gate structure

[0065] 318b: Gate structure

[0066] 320: Insulating material, dielectric layer

[0067] 330: Fins

[0068] 332: Fins

[0069] 334: Planar Structure

[0070] 336: Planar Structure

[0071] 338: Nanosheets, Nanosheet Structures

[0072] 340: Nanosheets, Nanosheet Structures

[0073] 400: Device

[0074] 410: Power grid layout

[0075] 412: Power grid layout

[0076] 414: Power Grid Layout

[0077] 416: Power grid layout

[0078] 500: Methods

[0079] 502: Operation

[0080] 504: Operation

[0081] 506: Operation

[0082] 508: Operation

[0083] 510: Operation

[0084] 512: Operation

[0085] 514: Operation

[0086] A-A': line

[0087] B-B': line

[0088] BM0: First metal layer on the back

[0089] CMD: Cutting Diffusion Metal Region

[0090] M0: First metal layer

[0091] MD: Diffused Metal Region

[0092] OD: Oxide diffusion region

[0093] PO: Doped polycrystalline silicon

[0094] X: Direction

[0095] Y: direction

[0096] Z: Direction Detailed Implementation

[0097] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the content of this disclosure, specific elements and layout examples will be described below. Of course, these are merely examples and are not intended to be limiting. For example, the first feature described below may be located on or overlaying a second feature; this may include embodiments where the first and second features are in direct contact, or embodiments where another feature is formed between the first and second features, such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplification and clarity and does not imply any specific association between the embodiments and / or configurations.

[0098] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “lower,” “lower,” “above,” and “higher” to describe the relationship between one element or feature and another, as shown in the accompanying drawings. The use of these spatial relative terms is intended to cover different orientations of the device during use or operation, and is not limited to those shown in the accompanying drawings. The device may also have other orientations (e.g., rotation of 90 degrees or other angles), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0099] As integrated circuit (IC) designs become increasingly complex, power distribution within IC devices also becomes more complex. Some embodiments disclosed herein include directed power mesh structures containing staggered vias to optimize current and address IR issues.

[0100] As integrated circuit (IC) devices operate, they require appropriate power supplies (e.g., VSS and VDD) and distribution. Various power distribution schemes can be employed to distribute the operating voltages VDD and VSS throughout the IC device. A power grid refers to the network of power lines and reference lines across the IC setup, providing stable and efficient power distribution to the various components and subsystems within the circuit. The power grid is used to minimize voltage drop, reduce noise, and maintain consistent power delivery throughout the circuit.

[0101] Attempting to save wafer space by reducing the size (spacing) of the power grid can introduce IR issues into the mid- and back-end metal wiring, especially with fewer vias and power lines. Such miniaturized power structures can create resistance bottlenecks. To address this, various methods can be employed, such as adjusting parameters like size, thickness, or material resistivity. Furthermore, the power grid is critical to wafer speed; a superior power IR grid can improve overall wafer performance.

[0102] Device design can attempt to address these issues by adjusting dimensions, thickness, or material resistance. Other designs may increase via size to reduce resistance. However, these methods can reduce wafer layout flexibility due to increased device area. Furthermore, denser power grids are sometimes used to minimize IR voltage drop. This can lead to increased power pad size, further increasing wafer area and manufacturing costs.

[0103] Some of the disclosed embodiments provide enhanced internal and external IR performance, reduced contact poly pitch (CPP), and a power grid structure with parallel power rails that contributes to process uniformity. Furthermore, by increasing the size of the power vias, more flexible placement can be achieved, further improving power efficiency. For example, increasing the number of power vias can reduce IR and provide a more robust power rail process. For instance, these embodiments increase the number of vias connecting the power rails and use cut metal structures to achieve the required connections to the power rails.

[0104] Figure 1 An integrated circuit (IC) device according to a disclosed embodiment is conceptually illustrated. Device 100 includes a power grid 200. Figure 1 In this document, various electrical connectors are shown as resistors to represent the resistance of the connecting wires. A first power rail 116 (e.g., a VDD power rail) couples a plurality of first transistors 216 to a source / drain (S / D) region via a plurality of vias 210. As used herein, depending on the context, the source / drain region may individually or collectively represent the source or drain.

[0105] A second power rail 120 (e.g., another VDD power rail) is coupled to the S / D regions of a plurality of second transistors 220 through a plurality of vias 214. A third power rail 118 (e.g., a VSS or ground rail) is located between the first power rail 116 and the second power rail 120. The third power rail 118 is coupled to the S / D regions of the plurality of first transistors 216 and the plurality of second transistors 220 through a plurality of vias 212.

[0106] As will be discussed further below, the conductive contact regions forming the S / D regions (e.g., metal over diffusion (MD) regions) include a separation structure 218 or a break structure 218 that selectively disconnects predetermined S / D regions of a plurality of first transistors 216 and a plurality of second transistors 220 from predetermined vias in vias 210, vias 212 and / or vias 214.

[0107] Figure 2AThis is a top view illustrating an exemplary layout of a device 100 including a power grid 200 according to the disclosed embodiment. In this embodiment, the device 100 includes a substrate 110, which may comprise silicon or another semiconductor material. A first power rail 116, a second power rail 120, and a third power rail 118 extend parallel to each other above the substrate in the X direction (e.g., horizontal). The third power rail 118 is located between the first power rail 116 and the second power rail 120 in the Y direction, which intersects (e.g., perpendicularly or orthogonally) the X direction. Power rails 116, 118, and 120 may be formed in a first metal layer M0.

[0108] Multiple active regions or active areas extend along the X direction above the substrate 110. For example, the active regions include a first active region 312 on a first side (e.g., above) of the third power rail 118 and a second active region 316 on a second side (e.g., below) of the third power rail 118. Active regions 312 and 316 form current flow channels in the transistor. In this disclosure, the active regions may sometimes be referred to as oxide diffusion (OD) regions, where the OD region layout pattern can be used to form the S / D region of the transistor. As discussed further below, active regions 312 and 316 may include planar structures, vertical (i.e., fin field-effect transistor (FinFET)) structures, stacked nanosheet structures, etc.

[0109] Multiple conductive contacts 112 extend over the substrate 110 along the Y direction and are located above or around the first active region 312 and the second active region 316 to form S / D regions or contacts. The conductive contacts 112 may be formed of metal and are sometimes referred to as diffused metal (MD) regions.

[0110] Multiple gate structures 318 extend along the Y direction over the substrate 110 above the first active region 312 and the second active region 316. The gate structures 318 may be made of a conductive material, such as doped polysilicon (i.e., "poly" or "PO") or a metal. The gate structures 318 are used to control the current flow in the transistor. The gate structures 318 extend over and / or around the active regions 312 and 316. The multiple gate structures 318 may also include an oxide disposed between the active regions 312 and 316 and the polysilicon.

[0111] According to the disclosed embodiments, a plurality of vias 210, 212, and 214 connect conductive contacts 112 to the first power rail 116, the second power rail 118, and the third power rail 120. For some known power grid structures, the third power rail (i.e., VSS) is connected to the first S / D contact of the transistor via vias extending between the VSS power rail and alternating or every other conductive contact (i.e., MD region). Second S / D contacts are connected to the first or second power rail (i.e., VDD) via vias extending between the remaining conductive contacts and the first or second VDD power rail. In other words, the first conductive contact is connected to the VSS power rail via vias, and the second conductive contact adjacent to the first conductive contact is connected to the first and second VDD power rails via corresponding vias (but not to the VSS power rail). The third conductive contact adjacent to the second conductive contact will be connected to the VSS power rail through a corresponding through-hole, and the fourth conductive contact adjacent to the second conductive contact will be connected to the first VDD power rail or the second VDD power rail, etc., through a corresponding through-hole. Therefore, alternating conductive contacts are connected to the VSS or VDD power rail through corresponding through-holes.

[0112] According to the disclosed embodiments, each conductive contact 112 is connected to a third power rail 118 (VSS) and a first power rail 116 or a second power rail 120 via a corresponding through-hole. For ease of explanation, a first conductive contact 112a and a second conductive contact 112b among a plurality of conductive contacts, and a first gate structure 318a among a plurality of gate structures will be described.

[0113] Please refer to Figure 1 and Figure 2A The first conductive contact 112a is located on the first side of the first gate structure 318a, and the second conductive contact 112b adjacent to the first conductive contact 112a is located on the second side of the first gate structure 318a. Therefore, the first conductive contact 112a, the first gate structure 318a, and the second conductive contact 112b respectively form the first S / D terminal, the gate, and the second S / D terminal of the transistor 216 or the transistor 220.

[0114] Multiple through-holes 212 connect the third power rail 118 to the conductive contact 112, which is also connected to the first power rail 116 and the second power rail 120 via through-holes 210 and 214 in the manner described herein. Through-holes 210, 212, and 214 extend in a third direction or Z direction that intersects (i.e., is perpendicular to) the X and Y directions. A first through-hole 212a connects to the first conductive contact 112a and the third power rail 118. A second through-hole 212b connects to the second conductive contact 112b and the third power rail 118.

[0115] Instead of both conductive contacts 112a and 112b connecting the S / D contact of a transistor (e.g., transistor 216a or transistor 220a) to the third power rail 118 via through holes 212a and 212b, conductive contact 112 is divided into two parts. The first part 112a1 of the first conductive contact 112a below the third power rail 118 is electrically disconnected from the first through hole 212a, and the second part 112b2 of the second conductive contact 112b above the third power rail 118 is electrically disconnected from the second through hole 212b.

[0116] In some embodiments, the conductive contact 112 (i.e., the MD region) can be separated or cut to provide a cut MD region (CMD) 218. In this way, the via 212a connects the third power rail 118 to the conductive contact 112a (i.e., one S / D of transistor 216a, see...). Figure 1 However, since CMD 218a, via 212a, and the third power rail 118 are not connected to any S / D of transistor 216b. Similarly, via 212b connects the third power rail 118 to conductive contact 112b (i.e., one S / D of transistor 216c), but since CMD 218a, via 212b, and the third power rail 118 are not connected to any S / D of transistor 216d.

[0117] Figure 2B The diagram shows a horizontal (i.e., X-direction) cross-sectional view of the device 100 taken along line A-A'. Figure 2B As shown, in this embodiment, each of the plurality of through-holes 214 extends through the dielectric or insulating material 320 and is connected together. Through-holes in the plurality of first through-holes 210 are formed on one or more conductive contacts 112 spaced apart. A plurality of third through-holes 214 are formed on one or more conductive contacts 112 spaced apart opposite the plurality of first through-holes 210. A plurality of second through-holes 212 are formed on each conductive contact 112, although CMD 218 disconnects some of the through-holes 212 (and the third power rail 118) from the corresponding conductive contact 112. Because the plurality of through-holes 214 are connected together, the resistance between the third power rail 118 and the conductive contact 112 is reduced.

[0118] Figure 2C A vertical (Y-direction) cross-sectional view of device 100 taken along line B-B' is shown. CMD 218 divides conductive contact 112 into two parts, such that the shown through-hole 212 connects the third power rail 118 to the left side portion of the shown conductive contact 112 (i.e., one S / D of transistor 216a, see...). Figure 1However, because CMD 218, through-hole 212, and the third power rail 118 are not connected to the right side of the conductive contact 112 shown. Figure 2C In this example, active regions 312 and 316 include vertical (i.e., FinFET) structures. Active region 312 includes a plurality of vertically extending (i.e., Z-direction) fins 330, and active region 316 includes fins 332.

[0119] As described above, other embodiments may employ different active region structures. Figure 3 An example of using an alternative active region with a planar structure is shown. Figure 3 In the active region 312, planar structure 334 is included, and active region 316 includes planar structure 336. Figure 4 This illustrates another paradigm using alternative active regions with nanosheet structures. Figure 4 In the active region 312, stacked nanosheets 338 are included, and active region 316 includes stacked nanosheets 340.

[0120] Figure 5 An embodiment is shown in which additional power rails are provided on the back side 102 of device 100. The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. To increase power distribution capability, certain bifacial power rail devices can be employed. Utilizing such a bifacial power rail device, the power grid 200 includes front and back interconnect structures, where advantages in area and resistance can be achieved.

[0121] exist Figure 2A The top of the device 100 is shown in the image. Figure 5 An example of the back surface 102 of device 100 is shown. The back surface 102 includes an additional configuration of a power grid 200, which includes a fourth power rail 119, which may be another VSS power rail. The power rail 119 may be disposed on the first metal layer BMO of the back surface. The power grid of the back surface 102 is similar to... Figure 2A The front structure shown depicts conductive contacts 112 connected to the fourth power rail 119 via corresponding rear through-holes 211. Figure 2A As shown on the front side, the cut metal structure 218 separates a portion of the conductive contact 112 from the fourth power rail 119.

[0122] One of the conductive contacts 112c is located on a first side of the gate structure 318b, and another conductive contact 112d adjacent to the conductive contact 112c is located on a second side of the gate structure 318b. A plurality of back vias 211 extending along the Z-direction connect a fourth power rail 119 to the conductive contact 112. A first back via 211a connects the conductive contact 112c and the fourth power rail 119. A second back via 211b connects the conductive contact 112d and the fourth power rail 119.

[0123] The bottom of the conductive contact 112c below the fourth power rail 119 is electrically disconnected from the first back through hole 211a via CMD 218c, and the upper part of the conductive contact 112d above the fourth power rail 119 is electrically disconnected from the second back through hole 211b via CMD 218d.

[0124] Figure 6 It is along Figure 5 The side view taken by the A-A' line. Figure 6 The rear surface 102 of the device 100 is shown, including a power grid 200. Figure 6 In some examples, the back vias 211 each extend in the Z direction and are discrete or separated from each other in the X direction. As previously mentioned, in some examples, the third power rail 118 is connected to the via 210 of the conductive contact 112 in the X direction. Figure 7 An alternative example of the power grid 200 on the back side 102 is shown, wherein, in the X direction, a fourth power rail 119 is connected to the back through-hole 211 of the conductive contact 112.

[0125] Figure 8 It is along Figure 5 The view intercepted by line B-B', wherein active regions 312 and 316 include, according to Figure 4 The nanosheet structures 338 and 340 of the illustrated embodiments are shown. Other examples using the back-side power grid 200 can employ other active region structures, such as... Figure 2C The vertical (i.e., FinFET) structure shown is or Figure 3 The planar structure shown.

[0126] Figure 9 Another example is shown, in which device 100 includes two power grids 200 that distribute power to... Figure 2A The two devices shown. Figure 5 In the device 100, there are an upper device 100a and a lower device 100b. The upper device 100a is separated from the lower device 100b by a cutting metal structure 218, wherein the conductive contact 112 of the upper device 100a is separated from the conductive contact 112 of the lower device 100b.

[0127] exist Figure 9 In the example, the lower device 100b is a mirror image of the corresponding structure of the upper device 100a, and more specifically the through hole 212 and the adjacent cut metal structure 218 are mirror images of the corresponding structure of the upper device 100a.

[0128] Figure 10 An embodiment with a rear power grid 200 is shown. Figure 9 The back surface 102 of the device 100 shown. (And...) Figure 5 Similar to the back side 102 shown, the back side through-hole 211 connects the conductive contact 112 to the back side power rail. Figure 10 In addition to the fourth power rail 119, the rear power grid also includes a fifth power rail 119a. In some implementations, both the rear power rails 119 and 119a are VSS power rails, but in other examples, one or more rear power rails can be configured as VDD power rails.

[0129] and Figure 5 As in the example, conductive contact 112 is connected to the fifth power rail 119a via a corresponding back through-hole 211. With Figure 2A Similar to the front side shown, the cut metal structure 218 separates a portion of the conductive contact 112 from the fifth power rail 119a. The back through-hole 211 of the lower device 100b and the adjacent cut metal structure 218 are configured as mirror images of the back through-hole 211 of the upper device 100a and the adjacent cut metal structure 218.

[0130] The power grid structure disclosed in this paper can provide an improved IR power distribution structure. Figure 9 and Figure 10 The example shown illustrates two devices disposed on a single substrate 110. In various IC devices, additional devices and circuitry can be divided into different areas of the device.

[0131] The Power Grid 200 is designed to address issues such as voltage drop, noise or interference, and IR problems. Different power grid structures are used for various circuits and devices in different areas of the device, depending on power requirements. Figure 11 This concept is illustrated in which different power grid structures are used in different regions of IC device 400 according to IR requirements.

[0132] For example, device 400 includes power grid layouts 410, 412, 414, and 416. For instance, a power grid layout including a rear power rail can provide enhanced IR performance, and a rear power grid arrangement with a rear via connected therein (…). Figure 7Compared to other configurations, improved IR performance can be provided by a rear power grid arrangement with connected rear vias. In this embodiment, power grid arrangement 410 produces the best IR performance. Power grid arrangement 412 has general IR performance. Power grid arrangements 414 and 416 both have moderate IR performance.

[0133] Figure 12 This is a flowchart illustrating a method 500 for manufacturing an apparatus (e.g., the apparatus 100 described above). Reference Figure 11 and Figure 2A In operation 502, substrate 110 is provided. Substrate 110 may be a silicon substrate, but in alternative embodiments other semiconductor materials, such as germanium or compound semiconductors, are used.

[0134] In operation 504, a first active region 312 and a second active region 316 extending along a first direction (i.e., the X direction) are formed on or above the substrate 110. In some examples, an epitaxial layer is grown on top of the substrate 110. The active layer or active regions 312 and 316 are formed by selectively doping regions of the substrate or epitaxial layer to create N-type and P-type regions.

[0135] In operation 506, a gate structure 318 is formed. The gate structure 318 includes a first gate structure extending along a second direction (i.e., the Y direction) over the first active region 312 and the second active region 316. Forming the gate structure 318 may include forming a gate electrode layer made of a conductive material such as doped polysilicon or a metal. Furthermore, a gate oxide made of a high-k dielectric material (e.g., hafnium oxide (HfO2)) may be formed to separate the gate electrode from the channel region (i.e., the active region).

[0136] Conductive contacts are formed in operation 508. Conductive contact 112 extends in the second direction or the Y direction and forms a source / drain (S / D) contact. The first conductive contact 112 is located on a first side of the first gate structure 318, and the second conductive contact 112 is located on a second side of the first gate structure 318 opposite to the first side. The second conductive contact extends in the second direction above the first active region and the second active region to form a second S / D contact.

[0137] In operation 510, a diced metal region 218 is formed, which separates a first portion of the first conductive contact 112 from a second portion of the second conductive contact 112. In some examples, a line divider pattern (CMD, i.e., a "diced MD pattern") is used to represent a separation step during a semiconductor manufacturing process, by which a continuous conductive contact extending along the Y direction is divided into a first portion and a second portion, as in combination. Figure 1 and Figure 2A discuss.

[0138] In some embodiments, the CMD process includes removing one or more contact portions from the conductive contact 112. The removed portion of the conductive contact 112 corresponds to the CMD region 218 or CMD structure 218. In some embodiments, a portion of the conductive contact 112 removed in operation 510 is identified in the layout design by cutting a feature pattern. In some embodiments, the cutting feature pattern is identified as the location where the contact was removed.

[0139] The removal process described above for forming the CMD structure 218 may include one or more etching processes suitable for removing a portion of the conductive contact 112. In some embodiments, the etching process includes identifying the portion of the conductive contact 112 to be removed and etching the portion of the conductive contact 112 to be removed. In some embodiments, a mask is used to specify the portion of the conductive contact 112 to be cut or removed. In some embodiments, the mask is a hard mask, while in other embodiments, the mask is a soft mask. Etching may include, for example, plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, and other suitable processes or combinations thereof. After the contact portion is removed from the conductive contact 112, the removed space may be filled with a dielectric material (e.g., an oxide material) to form a CMD structure 218 that divides the conductive contact 112 into a first portion and a second portion.

[0140] In operation 512, vias are formed extending in a third direction (i.e., the Z direction) intersecting the first and second directions. For example, a first via 214 connects to a first portion of a first conductive contact, while a second via connects to a second portion of a second conductive contact. In some examples, a dielectric layer, such as silicon dioxide or silicon nitride, separates the various layers of the device structure and provides electrical isolation. Thus, a dielectric layer 320 is disposed between the power rails and conductive contacts 112 in the MO metal layer. Openings are formed in the dielectric layer, and these openings are filled with a conductive material to vertically connect the different layers of the device 100, as described herein. In some examples, a photoresist layer is applied to the surface of the dielectric layer. A mask containing the desired via pattern (such as vias 211 and 212 connected in the horizontal or X direction) is aligned and placed over the photoresist layer. Ultraviolet (UV) light passes through the mask, exposing the photoresist at the desired via locations. The exposed photoresist is then developed using a developer solution, thereby removing the desired areas to create the via locations. In other examples, the via regions are selectively etched away using a suitable etchant. The via openings are then filled using conductive material deposition techniques such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0141] In operation 514, a first power rail, a second power rail, and a third power rail extending along a first direction are formed. In some examples, the first power rail 116, the third power rail 118, and the second power rail 120 are formed in a first metal layer (i.e., M0). The front power rails 116, 118, 120, and other interconnect structures can be formed by any acceptable process, such as damascene, dual damascene, etc.

[0142] In some embodiments, a carrier wafer is bonded to the top surface of device 100 to form the back power rail 119. After the carrier wafer is bonded to the front side of device 100, the device can be flipped so that the back side 102 of device 100 faces upward. A thinning process can be performed on the back side 102 of substrate 110. The thinning process may include planarization processes (e.g., mechanical polishing, CMP, etc.), etch-back processes, combinations thereof, etc. Next, a back power grid structure, such as power rails 119 and back vias 211, is formed. In the exemplary embodiment, the back power rail 119 is formed in the back metal layer BMO.

[0143] The first through-hole 212a electrically connects the third power rail 118 to a first portion of the first conductive contact 112a, and due to the CMD structure 218a, the second portion of the first conductive contact 112a is not electrically connected to the third power rail 118. The second through-hole 212b electrically connects the third power rail 118 to a second portion of the second conductive contact 112b, and due to the CMD structure 218a, the first portion of the second conductive contact 112b is not electrically connected to the third power rail 118.

[0144] According to some embodiments of this disclosure, an IC device includes a substrate and has a first power rail, a second power rail, and a third power rail extending parallel to each other over the substrate along a first direction. The third power rail is located between the first and second power rails in a second direction, which intersects the first direction. A plurality of active regions extend over the substrate in the first direction and include a first active region on a first side of the third power rail and a second active region on a second side of the third power rail opposite to the first side. A plurality of gate structures extend over the substrate in the second direction. A plurality of conductive contacts extend over the first and second active regions in the second direction to form source / drain (S / D) regions. The plurality of conductive contacts include a first conductive contact on a first side of a first gate structure and a second conductive contact adjacent to the first conductive contact on a second side of the first gate structure. A first via extends upward in a third direction and connects to the first conductive contact and the third power rail, the third direction intersects the first and second directions. A second via extends upward in a third direction and connects to the second conductive contact and the third power rail. The first portion of the first conductive contact on the second side of the third power rail is electrically disconnected from the first through hole, and the second portion of the second conductive contact on the first side of the third power rail is electrically disconnected from the second through hole.

[0145] In some embodiments, a third through-hole extending upward in a third direction is included, the third through-hole connecting a first portion of the first conductive contact to a second power rail. In some embodiments, a fourth through-hole extending upward in a third direction is included, the fourth through-hole connecting a second portion of the second conductive contact to the first power rail. In some embodiments, the first through-hole is connected to the second through-hole. In some embodiments, the active region is a planar structure. In some embodiments, the active region is a fin field-effect transistor structure. In some embodiments, the second direction is perpendicular to the first direction, and the third direction is perpendicular to both the first and second directions. In some embodiments, the first conductive contact includes a first cut metal structure separating the first portion of the first conductive contact from the first through-hole, and wherein the second conductive contact includes a second cut metal structure separating the second portion of the second conductive contact from the second through-hole. In some embodiments, a fourth power rail, a third through-hole, and a fourth through-hole are further included, the fourth power rail extending along the second direction and located between the first power rail and the second power rail. The third through-hole extends along the third direction and connects the first conductive contact and the fourth power rail. The fourth through-hole connects the second conductive contact and the fourth power rail. A first portion of the first conductive contact is electrically disconnected from the third through-hole, wherein a second portion of the second conductive contact is electrically disconnected from the fourth through-hole. In some embodiments, a third power rail is located on a first side of the substrate in a third direction, and a fourth power rail is located on a second side of the substrate in a third direction upward, the second side being opposite to the first side. In some embodiments, the third through-hole is connected to the fourth through-hole.

[0146] According to other embodiments of this disclosure, an IC device includes a substrate having a first power rail, a second power rail, and a third power rail extending parallel to each other in a first direction above the substrate. The third power rail is located between the first and second power rails in a second direction, which intersects the first direction. A plurality of active regions extend above the substrate along the first direction. The active regions include a first active region on a first side of the third power rail and a second active region on a second side of the third power rail opposite to the first side. A plurality of gate structures extend above the substrate in the second direction and are connected to the first and second active regions. A plurality of conductive contacts extend above the substrate in the second direction and are connected to the first and second active regions to form a source / drain (S / D) region. The plurality of conductive contacts include a first conductive contact on a first side of a first gate structure and a second conductive contact adjacent to the first conductive contact on a second side of the first gate structure. A first via extends upward in a third direction and is connected to the first conductive contact and the third power rail, which intersects the first and second directions. A second via extends upward in a third direction and is connected to the second conductive contact and the third power rail. The first via is connected to the second via in the second direction.

[0147] In some embodiments, a first portion of a first conductive contact on a second side of a third power rail is electrically disconnected from a first through-hole, and a second portion of a second conductive contact on a first side of the third power rail is electrically disconnected from a second through-hole. In some embodiments, the first conductive contact includes a first cut metal structure separating the first portion of the first conductive contact from the first through-hole, and the second conductive contact includes a second cut metal structure separating the second portion of the second conductive contact from the second through-hole. In some embodiments, a third through-hole and a fourth through-hole are included. The third through-hole extends in a third direction and connects to the first portion of the first conductive contact and the second power rail. The fourth through-hole connects to the second portion of the second conductive contact and the first power rail. In some embodiments, a fourth power rail, a third through-hole, and a fourth through-hole are included. The fourth power rail is located in a second direction between the first power rail and the second power rail. The third through-hole extends in the third direction and connects to the first conductive contact and the fourth power rail, and the fourth through-hole connects to the second conductive contact and the fourth power rail, wherein the third through-hole connects to the fourth through-hole in the second direction. In some embodiments, the first portion of the first conductive contact is electrically disconnected from the third through-hole, and the second portion of the second conductive contact is electrically disconnected from the fourth through-hole.

[0148] According to other embodiments of this disclosure, a method for forming an IC device includes providing a substrate, and forming a first active region and a second active region extending along a first direction on or above the substrate. A first gate structure extending along a second direction and intersecting the first direction is formed above the first and second active regions. A first conductive contact is formed on a first side of the first gate structure, extending along the second direction above the first and second active regions to form a first source / drain (S / D) contact. A second conductive contact is formed on a second side of the first gate structure opposite to the first side, extending along the second direction above the first and second active regions to form a second S / D contact. A first cleaved metal region is formed to separate a first portion of the first conductive contact from a second portion of the first conductive contact. A second cleaved metal region is formed to separate a first portion of the second conductive contact from a second portion of the second conductive contact. A first through-hole is formed extending along a third direction intersecting the first and second directions. The first through-hole is connected to the first portion of the first conductive contact. A second through-hole is formed to extend upward in a third direction and connect to the second portion of the second conductive contact. A first power rail and a second power rail extending along the first direction are formed. A third power rail is formed extending along a first direction between the first and second power rails. A first through-hole electrically connects the third power rail to a first portion of a first conductive contact, and a second portion of the first conductive contact is not electrically connected to the third power rail. A second through-hole electrically connects the third power rail to a second portion of a second conductive contact, and a first portion of the second conductive contact is not electrically connected to the third power rail.

[0149] In some embodiments, the method further includes forming a third through-hole extending upward in a third direction, the third through-hole being connected to a second portion of the first conductive contact, and forming a fourth through-hole extending upward in a third direction, the fourth through-hole being connected to a first portion of the second conductive contact, wherein the third through-hole electrically connects a second power rail to the first portion of the first conductive contact, and wherein the second through-hole electrically connects the first power rail to the first portion of the second conductive contact. In some embodiments, the method further includes forming a first through-hole and a second through-hole such that the first through-hole is connected to the second through-hole in a first direction.

[0150] According to some embodiments of this disclosure, an integrated circuit device is provided, including a substrate, and having a first power rail, a second power rail, and a third power rail extending parallel to each other along a first direction above the substrate. The third power rail is located between the first and second power rails in a second direction, which intersects the first direction. A plurality of active regions extend above the substrate in the first direction and include a first active region on a first side of the third power rail and a second active region on a second side of the third power rail opposite to the first side. A plurality of gate structures extend above the substrate in the second direction, including a first gate structure. A plurality of conductive contacts extend above the first and second active regions in the second direction to form source / drain regions. A first via extends upward in a third direction and connects to the conductive contacts and the third power rail, which intersects the first and second directions. A second via extends upward in a third direction and connects to the conductive contacts and the third power rail. A fourth power rail extends along the second direction and is located between the first and second power rails, with the third power rail on a first side of the substrate along the third direction and the fourth power rail on a second side of the substrate, which is opposite to the first side.

[0151] This disclosure outlines various embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, characterized in that, include: One substrate; A first power rail, a second power rail, and a third power rail extend parallel to each other on a substrate along a first direction, wherein the third power rail is located between the first power rail and the second power rail in a second direction, and the second direction intersects the first direction. Multiple active regions extend above the substrate along the first direction, including a first active region located on a first side of the third power rail and a second active region located on a second side of the third power rail opposite to the first side. Multiple gate structures extend over the substrate along the second direction, including a first gate structure; Multiple conductive contacts extend along the second direction above the first active region and the second active region to form a source / drain region. The multiple conductive contacts include a first conductive contact on a first side of the first gate structure and a second conductive contact on a second side of the first gate structure and adjacent to the first conductive contact. A first through-hole extends along a third direction, which intersects the first direction and the second direction, and the first through-hole connects to the first conductive contact and the third power rail; and A second through hole extends along the third direction and connects to the second conductive contact and the third power rail; and A first portion of the first conductive contact on the second side of the third power rail is electrically disconnected from the first through hole, and a second portion of the second conductive contact on the first side of the third power rail is electrically disconnected from the second through hole.

2. The integrated circuit device as claimed in claim 1, characterized in that, It further includes a third through-hole extending upward from the third party, the third through-hole being connected to the first portion of the first conductive contact and the second power rail.

3. The integrated circuit device as claimed in claim 2, characterized in that, It further includes a fourth through hole extending upward from the third party, the fourth through hole being connected to the second portion of the second conductive contact and the first power rail.

4. The integrated circuit device as claimed in claim 1, characterized in that, The first through hole is connected to the second through hole.

5. The integrated circuit device as claimed in claim 1, characterized in that, The second direction is perpendicular to the first direction, and the third direction is perpendicular to both the first and second directions.

6. An integrated circuit device, characterized in that, include: One substrate; A first power rail, a second power rail, and a third power rail extend parallel to each other on a substrate along a first direction, wherein the third power rail is located between the first power rail and the second power rail in a second direction, and the second direction intersects the first direction. Multiple active regions extend above the substrate along the first direction, including a first active region located on a first side of the third power rail and a second active region located on a second side of the third power rail opposite to the first side. Multiple gate structures extend above the substrate along the second direction and connect the first active region and the second active region, including a first gate structure; Multiple conductive contacts extend above the substrate along the second direction and connect the first active region and the second active region to form a source / drain region. The multiple conductive contacts include a first conductive contact on a first side of the first gate structure and a second conductive contact on a second side of the first gate structure and adjacent to the first conductive contact. A first through-hole extends along a third direction, which intersects the first direction and the second direction, and the first through-hole connects to the first conductive contact and the third power rail; and A second through hole extends along the third direction and connects to the second conductive contact and the third power rail; and The first through hole is connected to the second through hole in the second direction.

7. The integrated circuit device as claimed in claim 6, characterized in that, A first portion of the first conductive contact on the second side of the third power rail is electrically disconnected from the first through hole, and a second portion of the second conductive contact on the first side of the third power rail is electrically disconnected from the second through hole.

8. The integrated circuit device as claimed in claim 7, characterized in that, The first conductive contact includes a first cut metal structure that separates the first portion of the first conductive contact from the first through hole, and the second conductive contact includes a second cut metal structure that separates the second portion of the second conductive contact from the second through hole.

9. The integrated circuit device as claimed in claim 7, characterized in that, Further includes: A third through hole, extending along the third direction, connects to the first portion of the first conductive contact and the second power rail; and A fourth through hole is connected to the second portion of the second conductive contact and the first power rail.

10. An integrated circuit device, characterized in that, include: One substrate; A first power rail, a second power rail, and a third power rail extend parallel to each other on a substrate along a first direction, wherein the third power rail is located between the first power rail and the second power rail in a second direction, and the second direction intersects the first direction. Multiple active regions extend above the substrate along the first direction, including a first active region located on a first side of the third power rail and a second active region located on a second side of the third power rail opposite to the first side. Multiple gate structures extend over the substrate along the second direction, including a first gate structure; Multiple conductive contacts extend along the second direction above the first active region and the second active region to form a source / drain region; A first through hole extends along a third direction, which intersects the first direction and the second direction, and the first through hole is connected to the plurality of conductive contacts and the third power rail; A second through hole extends along the third direction and connects to the plurality of conductive contacts and the third power rail; A fourth power rail extends along the second direction and is located between the first power rail and the second power rail, wherein the third power rail is on a first side of the substrate along the third direction, and the fourth power rail is on a second side of the substrate along the third direction, the second side being opposite to the first side.

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