Chip heat dissipation assembly and packaging structure thereof
Patent Information
- Application Number
- CN202522343227.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-09-29
- Estimated Expiration
- 2035-11-05
AI Technical Summary
[0005]基于以上所述，本实用新型的目的在于提供一种芯片散热组件及其封装结构，以解决背景技术中的芯片散热结构在封装的过程中导热界面材料容易出现位移以及形变溢出的问题
[0021]本实用新型提供一种芯片散热组件，该散热组件包括用于对芯片进行热量扩散的散热盖板；中层框架，封装于散热盖板的底部，中层框架和散热盖板之间形成第一腔体，第一腔体的顶面为散热端面；底层框架，封装于中层框架的底部，底层框架和中层框架之间形成用于容置芯片的第二腔体，第二腔体的面积大于第一腔体的面积；导热界面层，设于第一腔体，其顶面紧密贴合于散热端面，其底面齐平于中层框架的底面。
Smart Images
Figure CN224818593U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip heat dissipation technology, specifically a chip heat dissipation component and its packaging structure. Background Technology
[0002] With the rapid development of semiconductor technology, the integration level of integrated circuits is constantly increasing. In chip packaging structures, chips are gradually shifting from single chips to multi-chip integration or large-scale monolithic integration. This shift brings higher performance and functional density, but it also poses a more severe challenge to the heat dissipation performance of chips.
[0003] Existing chip heat dissipation structures typically involve encapsulating a heat sink on the chip for heat dissipation. The bottom of the heat sink has a recessed cavity to provide clearance for the chip during encapsulation, allowing the chip to be completely placed within the cavity. The bottom perimeter of the heat sink (i.e., the edge of the recessed cavity) can be sealed against the substrate for encapsulation. A thermally conductive interface material is placed between the heat sink and the chip to facilitate rapid heat transfer, thereby reducing the thermal resistance between the heat sink and the chip and improving heat dissipation efficiency. In the existing structure described above, the thermal interface material is first placed on the chip, and then the heat sink is used to cover and encapsulate the chip. Since most thermal interface materials are soft materials that are easily deformed (e.g., indium), the thermal interface material is prone to displacement on the chip during the process of grasping the thermal interface material and placing it on the chip, as well as during the process of the heat sink and the chip assembly being closed. This results in a "void" between the chip and the heat sink, which increases the thermal resistance between the heat sink and the chip and reduces the heat conduction efficiency. On the other hand, when the heat sink is closed with the chip assembly, a certain pressure is generated between the bottom of the heat sink (i.e., the top of the cavity) and the thermal interface material, which can easily cause the thermal interface material to deform and overflow in all directions and fall onto the circuit board, causing a short circuit.
[0004] Therefore, there is an urgent need for a chip heat dissipation component and its packaging structure to solve the above problems. Utility Model Content
[0005] Based on the above, the purpose of this utility model is to provide a chip heat dissipation component and its packaging structure to solve the problem that the thermal interface material of the chip heat dissipation structure in the background art is prone to displacement and deformation overflow during the packaging process.
[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0007] The present invention provides a chip heat dissipation component, characterized in that it includes a heat dissipation cover plate for dissipating heat from the chip;
[0008] A middle frame is encapsulated at the bottom of the heat dissipation cover plate, and a first cavity is formed between the middle frame and the heat dissipation cover plate. The top surface of the first cavity is a heat dissipation end face.
[0009] The bottom frame is encapsulated at the bottom of the middle frame, and a second cavity for accommodating the chip is formed between the bottom frame and the middle frame. The area of the second cavity is larger than the area of the first cavity.
[0010] A thermally conductive interface layer is disposed in the first cavity, with its top surface tightly attached to the heat dissipation end face and its bottom surface flush with the bottom surface of the middle frame.
[0011] As an optional technical solution for chip heat dissipation components, the side surface of the first cavity is inclined, and the cross-section of the first cavity is in the shape of an inverted trapezoid.
[0012] As an optional technical solution for chip heat dissipation components, the depth of the first cavity and the thermal interface layer are equal.
[0013] As an optional technical solution for chip heat dissipation components, the bottom of the heat dissipation cover is provided with an annular overflow groove, which is located in the first cavity and surrounds the heat dissipation end face.
[0014] As an optional technical solution for chip heat dissipation components, the bottom of the heat dissipation cover is provided with an exhaust groove. One end of the exhaust groove is connected to the annular overflow groove, and the other end passes through the side of the heat dissipation cover. After the heat dissipation cover and the middle frame are encapsulated, an exhaust hole is formed between the exhaust groove and the middle frame.
[0015] As an optional technical solution for chip heat dissipation components, the heat dissipation end face is provided with a gold-plated layer, and the thermally conductive interface layer is attached to the gold-plated layer.
[0016] As an optional technical solution for chip heat dissipation components, the thermal interface layer is an indium layer with a thickness of 1mm to 3mm.
[0017] As an optional technical solution for chip heat dissipation components, the heat dissipation cover is a copper heat dissipation cover, a vacuum chamber heat dissipation plate, or a liquid-cooled heat dissipation cover.
[0018] On the other hand, the present invention also provides a chip packaging structure, including a chip, a substrate and the chip heat dissipation component described above. The chip is electrically fixedly connected to the substrate, the chip heat dissipation component is packaged on the substrate and located above the chip, and the side of the thermal interface layer facing away from the heat dissipation end face is tightly attached to the surface of the chip.
[0019] As an optional chip packaging structure, the chip heat dissipation component and the substrate are bonded together using adhesive encapsulation, screw locking encapsulation, or snap-fit encapsulation.
[0020] The beneficial effects of this utility model are as follows:
[0021] This utility model provides a chip heat dissipation assembly, which includes a heat dissipation cover plate for heat diffusion of the chip; a middle frame encapsulated at the bottom of the heat dissipation cover plate, forming a first cavity between the middle frame and the heat dissipation cover plate, the top surface of the first cavity being a heat dissipation end face; a bottom frame encapsulated at the bottom of the middle frame, forming a second cavity between the bottom frame and the middle frame for accommodating the chip, the area of the second cavity being larger than the area of the first cavity; and a thermally conductive interface layer disposed in the first cavity, the top surface of which is tightly attached to the heat dissipation end face, and the bottom surface of which is flush with the bottom surface of the middle frame.
[0022] In the above structure, the second cavity provides clearance during chip packaging, allowing the chip heat dissipation components to be mounted on the substrate in a fully sealed manner, providing dust protection and shielding for the chip. The thermal interface layer is placed within the first cavity, with its top surface tightly fitted to the heat dissipation end face and its bottom surface flush with the bottom surface of the middle frame. This allows the sidewalls of the first cavity to restrict the position of the thermal interface layer, preventing misalignment of the thermal interface layer during packaging and avoiding "voids" between the heat dissipation cover and the chip, which would increase thermal resistance and reduce heat transfer efficiency. Simultaneously, the sidewalls of the first cavity effectively prevent the thermal interface layer from being squeezed outwards during packaging, potentially causing short circuits.
[0023] On the other hand, the chip packaging structure provided by this utility model has a thermal interface layer pre-set in the first cavity. Therefore, during the packaging process of the chip heat dissipation component and the chip and substrate, it is not necessary to install or place the thermal interface layer on the chip, which improves the packaging efficiency of the chip. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the overall structure of the chip heat dissipation assembly in Embodiment 1 of this utility model;
[0025] Figure 2 This is an exploded view of the chip heat dissipation assembly in Embodiment 1 of this utility model;
[0026] Figure 3 This is a cross-sectional schematic diagram of the heat dissipation cover, the middle frame, and the bottom frame in Embodiment 1 of this utility model;
[0027] Figure 4 This is a bottom view of the heat dissipation cover plate in Embodiment 1 of this utility model;
[0028] Figure 5 This is an overall schematic diagram of the chip packaging structure in Embodiment 2 of this utility model;
[0029] Figure 6 This is a cross-sectional schematic diagram of the chip packaging structure in Embodiment 2 of this utility model.
[0030] In the picture:
[0031] 1. Heat dissipation cover; 10. Annular overflow groove; 11. Exhaust groove; 12. Exhaust hole; 13. Heat dissipation end face;
[0032] 2. Middle layer frame; 20. First cavity;
[0033] 3. Underlying frame; 30. Second cavity;
[0034] 4. Thermally conductive interface layer;
[0035] 5. Substrate; 50. Chip. Detailed Implementation
[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, not the entire structure.
[0037] In the description of this utility model, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0038] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0039] In the description of this embodiment, terms such as "upper," "lower," "left," and "right" are based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of description and simplification of operation, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0040] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Furthermore, the terms "first" and "second" are used merely for descriptive distinction and have no specific meaning.
[0041] Example 1
[0042] like Figure 1-4 As shown, this utility model provides a chip heat dissipation assembly, which includes a heat dissipation cover plate 1 for heat diffusion of chip 50; a middle frame 2, encapsulated at the bottom of the heat dissipation cover plate 1, forming a first cavity 20 between the middle frame 2 and the heat dissipation cover plate 1, the top surface of the first cavity 20 being a heat dissipation end face 13; a bottom frame 3, encapsulated at the bottom of the middle frame 2, forming a second cavity 30 between the bottom frame 3 and the middle frame 2 for accommodating chip 50, the area of the second cavity 30 being larger than the area of the first cavity 20; and a thermally conductive interface layer 4, disposed in the first cavity 20, its top surface tightly attached to the heat dissipation end face 13, and its bottom surface flush with the bottom surface of the middle frame 2.
[0043] The second cavity 30 in the chip heat dissipation assembly provided by this utility model provides clearance space when packaging the chip 50, enabling the chip heat dissipation assembly to be fully sealed and mounted on the substrate 5, providing dust protection and protection for the chip 50. A thermal interface layer 4 is disposed within the first cavity 20, with its top surface tightly attached to the heat dissipation end face 13 and its bottom surface flush with the bottom surface of the middle frame 2. This allows the sidewalls of the first cavity 20 to restrict the position of the thermal interface layer 4, preventing the thermal interface layer 4 from shifting between the heat dissipation cover 1 and the chip 50 during packaging, thus preventing a "void" phenomenon between them, which would lead to increased thermal resistance and reduced heat transfer efficiency. Simultaneously, the sidewalls of the first cavity 20 effectively prevent the thermal interface layer 4 from being squeezed during packaging, overflowing and falling onto the circuit board, causing a short circuit.
[0044] In this embodiment, as Figures 1 to 3As shown, the heat dissipation cover 1, the middle frame 2, and the bottom frame 3 are laminated and encapsulated using diffusion soldering. The middle frame 2 is hollow. After the middle frame 2 and the heat dissipation cover 1 are welded and encapsulated, a first cavity 20 is formed between the bottom of the middle frame 2 and the bottom of the heat dissipation cover 1. The side surface of the first cavity 20 is inclined, specifically, the inclination angle is 60 degrees, so that the cross-section of the first cavity 20 is an inverted trapezoid. After the bottom frame 3 and the middle frame 2 are welded and encapsulated, a second cavity 30 is formed between the bottom surface of the bottom frame 3 and the bottom surface of the middle frame 2. The second cavity 30 provides clearance space when encapsulating the chip 50, so that the chip 50 is placed in the second cavity 30, which plays a role in dust prevention and protection for the chip 50 and surrounding electronic components on the substrate 5.
[0045] In the above structure, the thermal interface layer 4 is disposed within the first cavity 20, with its top surface tightly attached to the heat dissipation end face 13. The thickness of the thermal interface layer 4 is equal to the thickness of the first cavity 20, making the bottom surface of the thermal interface layer 4 flush with the bottom surface of the middle frame 2. The inclined sidewalls of the first cavity 20 restrict the position of the thermal interface layer 4, preventing the thermal interface layer 4 from shifting during the packaging process of the heat dissipation cover 1 of the chip 50 and the chip 50, thus preventing a "void" phenomenon between the heat dissipation cover 1 and the chip 50, which would lead to increased thermal resistance and reduced heat transfer efficiency. At the same time, the sidewalls of the first cavity 20 effectively prevent the thermal interface layer 4 from being squeezed during the packaging process, causing it to overflow and fall onto the circuit board, resulting in a short circuit.
[0046] Specifically, the thermal interface layer 4 is made of a material with high thermal conductivity. In this embodiment, the thermal interface layer 4 is preferably an indium layer with a thickness of 1mm to 3mm, preferably 1mm. When the chip 50 inputs 1000W, the actual experimental test shows that when the indium thickness is 1mm, its thermal resistance is 0.05℃ / W and its thermal conductivity is 1000W / MK; when the indium thickness is 2mm, its thermal resistance is 0.08℃ / W and its thermal conductivity is 800W / MK; when the indium thickness is 3mm, its thermal resistance is 0.1℃ / W and its thermal conductivity is 600W / MK. That is to say, the greater the thickness of the indium, the higher its thermal resistance, and conversely, the lower its thermal conductivity. When the thickness of the indium is less than 1mm, on the one hand, it is not convenient for bonding operations, and on the other hand, the indium thickness is too thin and it is easy to create a gap between the heat dissipation end face 13 and the chip 50. Therefore, when the thickness of the indium is set to 1mm, its thermal resistance and thermal conductivity can achieve the best efficiency, while ensuring that the heat dissipation end face 13, the indium layer and the chip 50 are tightly bonded, thereby improving the overall heat dissipation efficiency.
[0047] It should be noted that in this embodiment, the indium layer can be injected into the first cavity 20 by hot melting and filling, so that the indium layer can fill the first cavity 20 and adapt to the shape of the first cavity 20.
[0048] In this embodiment, the heat dissipation end face 13 can also be plated with a gold layer. The gold plating layer can prevent surface oxidation of the heat dissipation end face 13 and the indium layer, thus preventing an increase in thermal resistance. Furthermore, it strengthens the affinity between the heat dissipation end face 13 and the indium layer, resulting in a higher degree of adhesion and effectively improving heat conduction efficiency. When the heat dissipation end face 13 is plated with a gold layer, the depth of the first cavity 20 must be greater than the thickness of the indium layer, ensuring that the bottom surface of the indium layer is always flush with the bottom surface of the middle frame 2.
[0049] Furthermore, such as Figure 3 and Figure 4 As shown, the bottom of the heat dissipation cover 1 is provided with an annular overflow groove 10 and an exhaust groove 11. The annular overflow groove 10 is located inside the first cavity 20 and surrounds the heat dissipation end face 13. One end of the exhaust groove 11 is connected to the annular overflow groove 10, and the other end passes through the side of the heat dissipation cover 1. After the heat dissipation cover and the middle layer frame 2 are encapsulated, an exhaust hole 12 is formed between the exhaust groove 11 and the middle layer frame 2. Since the indium layer and the chip 50 must be tightly bonded during the chip heat dissipation assembly encapsulation process to ensure good thermal conductivity of the chip 50, a certain pressure will be generated between them. At this time, the indium layer will be squeezed. During the squeezing process, the annular overflow groove 10 can provide a release space to prevent the excessive pressure between the indium layer and the chip 50 from damaging the chip 50. At the same time, it effectively prevents indium from overflowing from the gap between the chip 50 and the first cavity 20. The exhaust hole 12 can effectively discharge the air in the annular overflow groove 10.
[0050] In this embodiment, the heat dissipation cover 1 is a copper heat dissipation cover, a vacuum chamber heat dissipation plate, or a liquid cooling heat dissipation cover. The heat dissipation cover 1 with different structures can be adapted to chips 50 with different power for effective heat dissipation, thereby improving the applicability of the chip heat dissipation component.
[0051] Example 2
[0052] like Figure 5 and Figure 6 As shown, this utility model also provides a chip packaging structure, including a chip 50, a substrate 5 and a chip heat dissipation component as described in Embodiment 1. The chip 50 is electrically fixedly connected to the substrate 5, and the chip heat dissipation component is packaged on the substrate 5 and located above the chip 50. The side of the thermal interface layer 4 facing away from the heat dissipation end face 13 is tightly attached to the surface of the chip 50.
[0053] Furthermore, the chip heat dissipation component and the substrate 5 are glued together, or the chip heat dissipation component can be screwed onto the chip heat dissipation component and the substrate 5 can be threaded together, or the chip can be pressed together using a locking structure.
[0054] The chip packaging structure provided in this embodiment, because a thermally conductive interface layer 4 is pre-set in the first cavity 20, does not require the installation or placement of the thermally conductive interface layer 4 on the chip 50 during the packaging process of the chip heat dissipation assembly, chip 50, and substrate 5. This effectively prevents the thermally conductive interface layer 4 from shifting during the packaging process, ensuring that no "void" phenomenon is formed between the chip 50 and the heat dissipation end face 13, improving the heat dissipation efficiency of the chip 50, and simultaneously improving the packaging efficiency of the chip 50. On the other hand, it prevents the risk of the thermally conductive interface layer 4 falling off onto the circuit board and causing a short circuit.
[0055] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the present utility model without departing from the scope of the present utility model shall fall within the scope of the present utility model.
Claims
1. A chip heat dissipation component, characterized in that, This includes a heat dissipation cover for heat dissipation from the chip; A middle frame is encapsulated at the bottom of the heat dissipation cover plate, and a first cavity is formed between the middle frame and the heat dissipation cover plate. The top surface of the first cavity is a heat dissipation end face. The bottom frame is encapsulated at the bottom of the middle frame, and a second cavity for accommodating the chip is formed between the bottom frame and the middle frame. The area of the second cavity is larger than the area of the first cavity. A thermally conductive interface layer is disposed in the first cavity, with its top surface tightly attached to the heat dissipation end face and its bottom surface flush with the bottom surface of the middle frame.
2. The chip heat dissipation component according to claim 1, characterized in that, The side surfaces of the first cavity are inclined, and the cross-section of the first cavity is in the shape of an inverted trapezoid.
3. A chip heat dissipation component according to claim 2, characterized in that, The depths of the first cavity and the thermally conductive interface layer are equal.
4. A chip heat dissipation component according to claim 1, characterized in that, The bottom of the heat dissipation cover is provided with an annular overflow groove, which is located in the first cavity and surrounds the heat dissipation end face.
5. A chip heat dissipation component according to claim 4, characterized in that, The bottom of the heat dissipation cover is provided with an exhaust groove. One end of the exhaust groove is connected to the annular overflow groove, and the other end passes through the side of the heat dissipation cover. After the heat dissipation cover and the middle frame are encapsulated, an exhaust hole is formed between the exhaust groove and the middle frame.
6. A chip heat dissipation component according to claim 1, characterized in that, The heat dissipation end face is provided with a gold plating layer, and the thermally conductive interface layer is attached to the gold plating layer.
7. A chip heat dissipation component according to claim 1, characterized in that, The thermally conductive interface layer is an indium layer, and the thickness of the indium layer is 1mm to 3mm.
8. A chip heat dissipation component according to claim 1, characterized in that, The heat dissipation cover is a copper heat dissipation cover, a vacuum chamber heat dissipation plate, or a liquid-cooled heat dissipation cover.
9. A chip packaging structure, comprising a chip, a substrate, and a chip heat dissipation component as described in any one of claims 1-8, characterized in that, The chip is electrically fixedly connected to the substrate, the chip heat dissipation assembly is encapsulated on the substrate and located above the chip, and the side of the thermal interface layer facing away from the heat dissipation end face is tightly attached to the surface of the chip.
10. A chip packaging structure according to claim 9, characterized in that, The chip heat dissipation component and the substrate are encapsulated by adhesive, screw, or snap-fit.