A dual-pad heat-dissipation flip-chip packaging structure
Patent Information
- Application Number
- CN202522153927.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-11
- Publication Date
- 2026-09-29
- Estimated Expiration
- 2035-10-11
AI Technical Summary
[0015]一、显著提升散热效率，突破高功率芯片热管理瓶颈
Smart Images
Figure CN224818597U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip packaging structure, specifically a dual-pad heat dissipation flip chip packaging structure. Background Technology
[0002] With the rapid development of consumer electronics, artificial intelligence, cloud computing, and other fields, electronic devices are constantly evolving towards higher integration, higher power density, and miniaturization. The performance of core devices such as CPUs, GPUs, SOCs, and communication base station chips continues to improve, and their power dissipation per unit area has also increased significantly. The heat flux density of some high-end chips has exceeded 100W / cm². Against this backdrop, thermal management efficiency has become a key bottleneck restricting the performance, reliability, and lifespan of electronic devices. If the heat generated during chip operation cannot be dissipated in time, it will cause a sharp rise in the chip junction temperature, which may not only cause electrical performance degradation problems such as signal delay and noise interference, but also accelerate the aging of internal components and even lead to thermal runaway, causing permanent damage to the device.
[0003] In traditional chip packaging technology, wire bonding was the mainstream solution in the early days, which uses metal leads to achieve electrical connection between the chip and the substrate. However, this solution has obvious limitations: on the one hand, the metal leads are relatively long (usually hundreds of micrometers to several millimeters), resulting in long signal transmission paths and large RC delays, making it difficult to meet the performance requirements of high-frequency and high-speed chips; on the other hand, the heat dissipation path of wire bonding is singular, mainly relying on the chip to dissipate heat to the outside through the substrate, which has a limited heat dissipation area and high thermal resistance, and can only meet the needs of low-to-medium power devices with power dissipation of 5-10W, and cannot adapt to the heat dissipation requirements of high-power chips.
[0004] To address the shortcomings of wire bonding packaging, flip-chip packaging technology emerged. Flip-chip packaging uses a design where the active area of the chip faces downwards, directly interconnecting the chip and substrate using solder balls or conductive bumps. This significantly shortens the interconnect distance (typically only tens of micrometers), substantially reducing signal transmission delay and parasitic parameters, supporting high-frequency signal processing from 10-40GHz. Simultaneously, the package size is close to that of a bare die, meeting the demands of high-density integration. However, traditional flip-chip packaging still suffers from heat dissipation limitations: while solder balls increase the heat conduction path between the chip and substrate, it lacks a dedicated heat dissipation structure designed for the heat dissipation requirements of high-power chips. Heat dissipation mainly relies on the cooperation between the substrate and an external heat sink. When the chip power exceeds 20W, a single heat dissipation path is insufficient to quickly remove heat, and the chip junction temperature still exceeds the safe threshold (typically 85-125℃), limiting the performance release of high-power chips.
[0005] Furthermore, traditional flip-chip package pad designs focus on electrical connections, failing to differentiate between electrical and thermal pads. While some pads do offer some heat dissipation, their efficiency is limited due to material selection (e.g., using metals like aluminum and nickel with lower thermal conductivity than copper) and layout design (concentrated at the chip edge, not covering the core heat dissipation area). Simultaneously, regarding packaging protection, while traditional molding compounds provide physical protection and insulation, in some designs they completely cover the chip surface, hindering direct contact between the chip and external heat dissipation structures, further increasing thermal resistance. Therefore, we propose a dual-pad thermal flip-chip package structure. Utility Model Content
[0006] To address the shortcomings of existing technologies, this invention provides a dual-pad heat dissipation flip-chip package structure, which solves the aforementioned problems.
[0007] To achieve the above-mentioned objectives, this utility model provides the following technical solution: a dual-pad heat dissipation flip-chip package structure, including a substrate, a chip disposed on the surface of the substrate, a molding compound disposed on the outer side of the chip, a heat dissipation structure disposed on the surface of the chip, the active area of the chip facing downward, and connected to the substrate by solder balls, with I / O terminals distributed on the surface of the chip.
[0008] Preferably, the chip surface is provided with two sets of pads, one end of which is connected to a connecting line, and the other end of the connecting line is connected to a heat dissipation structure.
[0009] Preferably, the two sets of pads are respectively located at the two corners of the chip surface, and the solder balls are equidistantly located at the bottom of the chip.
[0010] Preferably, the heat dissipation structure includes thermally conductive adhesive and heat dissipation fins, the heat dissipation fins are disposed at the bottom of the thermally conductive adhesive, and one end of the connecting wire is connected to the thermally conductive adhesive.
[0011] Preferably, the heat dissipation fins consist of a horizontal rectangular plate and multiple sets of T-shaped plates integrally formed on the surface of the rectangular plate, and the surface of the T-shaped plates is flush with the surface of the plastic seal layer.
[0012] Preferably, the surface of the chip is provided with a barrier that surrounds the pads on the inside.
[0013] Preferably, the substrate is made of either glass fiber reinforced epoxy resin or aromatic benzocyclobutane thin film substrate.
[0014] Compared with the prior art, this utility model provides a dual-pad heat dissipation flip-chip package structure, which has the following advantages:
[0015] I. Significantly improves heat dissipation efficiency, breaking through the thermal management bottleneck of high-power chips.
[0016] This packaging structure significantly enhances heat dissipation capabilities through a dedicated thermal pad and a dual heat dissipation path design. On one hand, the independent thermal pad, made of a high thermal conductivity metal such as copper, directly contacts the chip's heat dissipation area, quickly absorbing the core heat generated during chip operation. On the other hand, heat is transferred through a dedicated path of "chip-thermal pad-connector-thermal adhesive-heat sink fins," combined with an auxiliary path of "chip-solder ball-substrate-external heat sink," forming a dual heat conduction channel. Compared to traditional flip-chip packaging that relies solely on substrate heat dissipation, this increases the heat dissipation area by over 30% and reduces thermal resistance by 25%-40%. Even when chip power exceeds 25W, the junction temperature can still be stably controlled below the safe threshold of 85℃, effectively preventing electrical performance degradation and device aging caused by high temperatures, ensuring stable full-load operation of high-power chips (such as high-end GPUs and communication base station chips).
[0017] II. Optimize electrical performance to meet the requirements of high-frequency and high-speed signal transmission.
[0018] This structure inherits the high-density interconnect advantages of flip-chip packaging while further reducing signal loss through structural design. The chip's active area faces downwards, coupled with equidistantly distributed solder balls, shortening the interconnect distance between the chip and the substrate to tens of micrometers. This significantly reduces RC delay and parasitic parameters along the signal transmission path, supporting high-frequency signal processing above 40GHz. Compared to traditional wire bonding packaging (which only supports 5-10GHz), the signal transmission rate is increased by more than four times. Furthermore, the thermal pads and electrical connection pads are functionally separated, preventing heat interference to the electrical pads during heat dissipation, reducing signal noise and crosstalk, and ensuring stable signal transmission quality even under high-power operation, meeting the high-speed data processing needs of fields such as artificial intelligence and cloud computing.
[0019] III. Enhance structural reliability and extend device lifespan
[0020] This packaging structure enhances overall reliability through multiple layers of protection and stable connection design. First, the enclosure surrounds the solder balls and pads, isolating them from external dust and moisture, preventing corrosion of critical connection components, avoiding solder ball oxidation and pad corrosion, and reducing the risk of connection failure. Second, the thermally conductive adhesive not only conducts heat but also firmly fixes the heat sink fins while providing insulation to prevent short circuits between the heat sink components and the chip circuitry, ensuring electrical safety. Third, the equidistantly distributed solder balls ensure uniform stress on the chip and substrate, reducing localized stress caused by temperature changes and vibrations, preventing chip cracking and substrate deformation, extending the lifespan of the packaging structure, and enabling the device to operate stably under complex conditions (such as high temperature and high humidity environments).
[0021] IV. Balancing miniaturization and compatibility to meet the needs of various application scenarios
[0022] This structure enhances performance without sacrificing miniaturization. The chip employs a flip-chip design, with a package size close to that of a bare die, reducing volume by 20%-30% compared to traditional wire bonding packages. This meets the miniaturization requirements of portable devices such as smartphones and laptops. Simultaneously, the substrate uses glass fiber reinforced epoxy resin or ABF substrates. These materials not only have excellent thermal conductivity but also good processing compatibility, allowing for compatibility with existing PCB manufacturing processes without requiring large-scale modifications to downstream production equipment, thus reducing application costs. Furthermore, the heat sink fins feature a T-shaped structure with a surface flush with the molding layer, maximizing heat dissipation area without increasing the overall package thickness. This allows for flexible adaptation to installation requirements in various scenarios such as servers, communication equipment, and automotive electronics, making it widely applicable. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of the structure of this utility model;
[0024] Figure 2 This is a schematic diagram of the heat dissipation fins of this utility model;
[0025] Figure 3 This is a schematic diagram of the welding ball of this utility model.
[0026] In the diagram: 1. Substrate; 2. Chip; 3. Enclosure; 4. Molding layer; 5. Solder pad; 6. Connector; 7. Thermal adhesive; 8. Heat sink fins; 9. Solder ball. Detailed Implementation
[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0028] Please see Figure 1-3 A dual-pad heat dissipation flip-chip package structure, the structure of which is as follows:
[0029] Substrate 1
[0030] Substrate 1 is the fundamental load-bearing and functional transmission core component of the entire packaging structure. It is made of a material with high stability and excellent thermal and electrical conductivity, specifically either glass fiber reinforced epoxy resin or aromatic benzocyclobutane film (ABF) substrate. Internally, substrate 1 is not a single planar structure but integrates a multi-layered circuit structure. These circuits, with precise wiring design, undertake two core functions: signal transmission and power distribution. They stably transmit the electrical signals output by chip 2 to external circuits and continuously provide stable power to chip 2 for operation. Simultaneously, substrate 1 provides a crucial heat conduction path for the thermal pads 5. When heat generated by chip 2 is transferred to substrate 1 through pads 5, substrate 1 can further conduct the heat to the external heat sink, forming an important part of the complete heat dissipation system and ensuring the overall thermal management efficiency of the packaging structure.
[0031] Chip 2
[0032] Chip 2 is the core functional component of the package structure and the main source of heat generation. Its structural design follows the core logic of flip-chip packaging, with the active area facing downwards. It is mechanically fixed and electrically connected to the substrate 1 via solder balls 9 at the bottom. This flip-chip design significantly shortens the interconnection distance between chip 2 and substrate 1, reducing RC delay during signal transmission and providing a foundation for high-density interconnection. The surface of chip 2 not only has I / O terminals for signal and power interaction but also two sets of dedicated heat dissipation pads 5. The I / O terminals cover the surface of chip 2 in a high-density layout, meeting the interconnection density requirements of highly integrated electronic devices. Simultaneously, a barrier 3 is installed on the surface of chip 2, surrounding the solder balls 9 and pads 5, forming protection for the internal critical connection structures. During operation, the heat generated by chip 2 is dissipated through two paths: part is transferred to the surface pads 5 via internal heat conduction, and the other part is conducted to the substrate 1 via the solder balls 9 at the bottom. This dual heat conduction path effectively prevents localized overheating of chip 2.
[0033] 3 fences
[0034] Enclosure 3 is a protective and isolation structure set on the surface of chip 2. Its core function is to completely surround the multiple sets of solder balls 9 and two sets of solder pads 5 on the surface of chip 2, forming an independent protective area. From a functional perspective, enclosure 3 can effectively isolate external dust, moisture and other impurities from corroding the solder balls 9 and solder pads 5, preventing these critical connecting components from oxidation, corrosion and other problems caused by external environmental influences, ensuring the electrical connection stability of solder balls 9 and the heat conduction efficiency of solder pads 5. At the same time, during the packaging process (such as the molding stage of molding layer 4), enclosure 3 can also play a positioning and limiting role, preventing the molding material from excessively covering the solder pads 5 or squeezing the solder balls 9 during the flow process, ensuring the positional accuracy of the internal structure, and further improving the reliability and service life of the packaging structure.
[0035] Encapsulation layer 4
[0036] The molding compound layer 4 is an overall protective structure covering the outside of the chip 2, typically made of epoxy resin-based molding compound material with excellent insulation properties, high temperature resistance, and mechanical strength. Its main function is to comprehensively encapsulate the chip 2, the enclosure 3, solder balls 9, and other internal core components, forming a physical protective barrier to resist the effects of external impacts, vibrations, and temperature changes on the internal structure, preventing damage to the chip 2 or loosening of connections due to external forces. Simultaneously, the molding compound layer 4 also has good insulation properties, preventing leakage or short circuits between the internal circuitry and the external environment, ensuring the electrical safety of the package structure. Furthermore, the surface of the molding compound layer 4 is flush with the surface of the T-shaped plate of the heat sink fins 8. This design ensures the flatness of the package structure's appearance, avoids surface protrusions affecting subsequent installation, and does not obstruct the contact between the heat sink fins 8 and the air, ensuring normal heat dissipation function.
[0037] Pad 5
[0038] The pads 5 are key components for heat dissipation and auxiliary connection on the surface of chip 2. Two sets are provided, located at the two corners of the chip 2 surface, and are made of a high thermal conductivity metal such as copper. Copper's high thermal conductivity allows it to quickly receive and transfer the heat generated by chip 2, effectively reducing thermal resistance. Functionally, the two sets of pads 5 are dedicated heat dissipation pads, directly contacting the heat dissipation area of chip 2, efficiently receiving the heat generated by chip 2 during operation. Simultaneously, one end of each pad 5 is connected to a connecting line 6, which transfers heat to the heat sink fins 8, forming a dedicated heat dissipation path of "chip 2 → pad 5 → connecting line 6 → heat sink fins 8". This path works in conjunction with the heat dissipation path of substrate 1, significantly improving overall heat dissipation efficiency.
[0039] Connector 6
[0040] Connector 6 serves as a heat conduction bridge connecting pad 5 and the heat dissipation structure. It is typically made of copper, aluminum, or other high thermal conductivity metal wires, with both ends firmly connected to pad 5 and thermally conductive adhesive 7 (e.g., through soldering or crimping). During heat dissipation, the core function of connector 6 is to stably and rapidly transfer the heat received by pad 5 to thermally conductive adhesive 7, and then from adhesive 7 to the heat sink fins 8, filling the gap between pad 5 and fins and preventing interruptions in heat conduction due to lack of direct contact. Furthermore, connector 6 must possess sufficient flexibility and mechanical strength to adapt to the internal spatial layout of the package structure and maintain connection stability under slight vibrations or temperature changes, ensuring a continuous and unobstructed heat dissipation path.
[0041] Thermal adhesive 7
[0042] The thermally conductive adhesive 7 is a heat conduction medium located between the bottom of the heat sink fins 8 and the connecting wires 6. It is mainly composed of a polymer matrix and high thermal conductivity fillers (such as alumina, boron nitride, metal powder, etc.), and has good thermal conductivity, insulation, and adhesion. Its functions are mainly reflected in three aspects: First, as a heat conduction medium, it efficiently conducts the heat transferred by the connecting wires 6 to the heat sink fins 8, solving the "contact thermal resistance" problem caused by poor contact between the connecting wires 6 and the heat sink fins 8, and improving heat conduction efficiency; second, as an adhesive, it firmly fixes the heat sink fins 8 to the designated position above the chip 2, ensuring the relative position stability between the heat dissipation structure and the chip 2; third, as an insulating layer, it prevents electrical short circuits between the heat sink fins 8 and the circuits or pads 5 on the surface of the chip 2, ensuring the electrical safety of the package structure.
[0043] Heat sink fins 8
[0044] The heat sink fins 8 are the core heat dissipation element of the entire package structure. Made of high thermal conductivity metals such as aluminum, copper, or aluminum alloy, their structure consists of a horizontal rectangular plate and multiple T-shaped plates integrally molded on the surface of the rectangular plate. The surfaces of the T-shaped plates are flush with the surface of the molding compound layer 4. The advantages of this design are: the horizontal rectangular plate, as the basic load-bearing component, is in direct contact with the thermally conductive adhesive 7, allowing it to receive heat transferred by the adhesive over a large area; while the multiple T-shaped plates significantly increase the contact area between the heat sink fins 8 and the air, rapidly dissipating heat to the surrounding environment through both convection and radiation. The T-shaped plate design avoids the problem of dust accumulation in traditional straight-fin fins and maximizes the heat dissipation area within a limited space. Furthermore, the flush design of the T-shaped plates with the molding compound layer 4 ensures uniform thickness of the overall package structure, does not affect subsequent installation, and allows the fins to be fully exposed to the air for unobstructed heat dissipation, further improving heat dissipation efficiency.
[0045] Solder ball 9
[0046] Solder balls 9 are the core components for achieving mechanical and electrical connections between chip 2 and substrate 1. They are typically made of low-melting-point, highly conductive metal materials such as tin-lead alloys or lead-free tin alloys (e.g., tin-silver-copper alloys), and are evenly distributed on the surface of chip 2 (on the side opposite to substrate 1). In the packaging process, solder balls 9 form a firm connection with the corresponding pads on substrate 1 through a reflow soldering process: after being heated to the melting point of solder balls 9, they melt and fuse with the pads on substrate 1, forming a stable mechanical fixing structure and electrical path after cooling. Functionally, solder balls 9 mainly play two roles: first, electrical connection, acting as a "conductive bridge" between chip 2 and substrate 1, transmitting the I / O signals and power requirements of chip 2 to the multilayer circuitry of substrate 1, and then from substrate 1 to the external circuitry, realizing signal interaction and power supply between the chip and the external environment; second, auxiliary heat dissipation, some heat can be conducted from chip 2 to substrate 1 through solder balls 9, and then from substrate 1 to the external heat sink, becoming an important supplementary path for heat dissipation of chip 2. Meanwhile, the equidistant distribution of solder balls 9 ensures uniform stress between chip 2 and substrate 1, avoiding loose connections or chip damage caused by local stress concentration, and improving the mechanical reliability of the packaging structure.
[0047] Example 1:
[0048] The chip includes a substrate 1, a chip 2 disposed on the surface of the substrate 1, a molding layer 4 disposed on the outer side of the chip 2, a heat dissipation structure disposed on the surface of the chip 2, the active area of the chip 2 facing downward, and connected to the substrate 1 through solder balls 9, with I / O terminals distributed on the chip surface to achieve high-density interconnection.
[0049] Furthermore, two sets of pads 5 are provided on the surface of chip 2. One end of the pads 5 is connected to a connecting line 6, and the other end of the connecting line 6 is connected to a heat dissipation structure.
[0050] Furthermore, two sets of pads 5 are respectively set at two corners on the surface of chip 2, and solder balls 9 are equidistantly set at the bottom of chip 2.
[0051] Furthermore, the heat dissipation structure includes thermally conductive adhesive 7 and heat dissipation fins 8. The heat dissipation fins 8 are disposed at the bottom of the thermally conductive adhesive 7, and one end of the connecting wire 6 is connected to the thermally conductive adhesive 7.
[0052] Furthermore, the heat dissipation fin 8 consists of a horizontal rectangular plate and multiple sets of T-shaped plates integrally formed on the surface of the rectangular plate, and the surface of the T-shaped plates is flush with the surface of the plastic sealing layer 4.
[0053] Furthermore, a barrier 3 is provided on the surface of chip 2, which surrounds the pad 5 on the inside.
[0054] Furthermore, substrate 1 is made of either glass fiber reinforced epoxy resin or aromatic benzocyclobutane thin film substrate, and has a multi-layer circuit structure inside to realize signal transmission and power distribution, while providing a heat conduction path for heat dissipation pads.
[0055] Working principle: The heat generated by chip 2 is first transferred to pad 5 through internal heat conduction, and then transferred from pad 5 to heat sink 8. At the same time, the heat is conducted through substrate 1 to external heat sink and finally dissipated into the environment. The dual pad design increases the heat dissipation area and heat conduction path, effectively reducing the junction temperature of substrate 1. The solder balls 9 on chip 2 and the pads on substrate 1 are electrically connected through processes such as reflow soldering to realize signal transmission and power supply between the chip and external circuits.
[0056] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A dual-pad heat dissipation flip-chip package structure, characterized in that, Includes a substrate (1), on the surface of the substrate (1) a chip (2) is disposed thereon, on the outer side of the chip (2) a plastic encapsulation layer (4) is disposed thereon, on the surface of the chip (2) a heat dissipation structure is disposed thereon, the active area of the chip (2) faces downward, and is connected to the substrate (1) by solder balls (9), and the I / O terminals are distributed on the surface of the chip.
2. The dual-pad heat dissipation flip-chip package structure according to claim 1, characterized in that: The surface of the chip (2) is provided with two sets of pads (5), one end of which is connected to a connecting line (6), and the other end of the connecting line (6) is connected to a heat dissipation structure.
3. The dual-pad heat dissipation flip-chip package structure according to claim 2, characterized in that: Two sets of pads (5) are respectively set at the two corners of the chip (2) surface, and the solder balls (9) are equidistantly set at the bottom of the chip (2).
4. The dual-pad heat dissipation flip-chip package structure according to claim 2, characterized in that: The heat dissipation structure includes thermally conductive adhesive (7) and heat dissipation fins (8). The heat dissipation fins (8) are disposed at the bottom of the thermally conductive adhesive (7), and one end of the connecting line (6) is connected to the thermally conductive adhesive (7).
5. The dual-pad heat dissipation flip-chip package structure according to claim 4, characterized in that: The heat dissipation fins (8) consist of a horizontal rectangular plate and multiple T-shaped plates integrally formed on the surface of the rectangular plate, and the surface of the T-shaped plates is flush with the surface of the plastic sealing layer (4).
6. The dual-pad heat dissipation flip-chip package structure according to claim 1, characterized in that: The surface of the chip (2) is provided with a barrier (3) that surrounds the pad (5) inside.
7. The dual-pad heat dissipation flip-chip package structure according to claim 1, characterized in that: The substrate (1) is made of either glass fiber reinforced epoxy resin or aromatic benzocyclobutane thin film substrate.