A package structure of symmetric stacked flash memory chips

Abstract

The utility model discloses a kind of packaging structure of symmetrical stacked flash memory chip, including multilayer symmetrical stacked flash memory chip wafer, each symmetrical stacked flash memory chip is electrically connected by bonding layer;Packaging substrate, the top surface of the packaging substrate is provided with multilayer symmetrical stacked flash memory chip wafer;And package, the package covers the multilayer symmetrical stacked flash memory chip wafer;Its characterized in that, still include multiple vertical heat conduction units, it is made of high thermal conductivity material, and vertically penetrates three layers in the multilayer symmetrical stacked flash memory chip wafer;By setting vertical heat conduction unit that vertically penetrates multilayer flash memory chip wafer, its two ends are directly thermal contact with top heat dissipation cover and bottom fin respectively, construct the axial heat dissipation path from chip stack inside to outside, reach the heat generated by core heat source directly, efficiently conduct to external environment, significantly reduce the effect of chip internal operating temperature.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a packaging structure for symmetrically stacked flash memory chips. Background Technology

[0002] Flash memory chips are non-volatile memory integrated circuits, meaning they can retain stored data for a long time even after power is off. They are the core data storage carrier of the modern digital economy and are widely used in various fields, from mobile devices to data centers. In traditional 3D stacked flash memory chip packaging solutions, heat dissipation mainly relies on the lateral thermal conduction of the packaging substrate and natural convection on the surface of the package. These heat dissipation methods have significant limitations: First, the heat conduction path from the center of the stack to the outside is too long, resulting in a high overall thermal resistance; second, multi-layer wafer stacking introduces a large number of material interfaces, and the contact thermal resistance between these interfaces further reduces heat dissipation efficiency; thirdly... The symmetrical stacked structure makes it easy for heat to accumulate in the central area, forming local hot spots that are difficult to eliminate. For flash memory chips, temperature sensitivity is particularly prominent. Excessive operating temperature will directly affect the charge retention characteristics of the memory cells, leading to shorter data retention time, increased read and write error rates, and even irreversible performance degradation. Especially during high-frequency read and write operations, the memory cell array and control logic circuit will generate a lot of heat. If it cannot be dissipated in time, it will seriously affect the reliability and lifespan of the chip. Existing improvement solutions mostly focus on optimizing packaging materials or increasing the external heat dissipation area, but these measures still cannot effectively solve the problem of heat accumulation inside the stack. Utility Model Content

[0003] The purpose of this invention is to provide a packaging structure for symmetrically stacked flash memory chips to solve the problem of heat accumulation inside the stack.

[0004] To achieve this objective, the present invention adopts the following technical solution: A packaging structure for a symmetrically stacked flash memory chip includes a multilayer symmetrically stacked flash memory chip wafer, wherein the symmetrically stacked flash memory chip wafers are electrically connected to each other through a bonding layer; a packaging substrate, wherein the top surface of the packaging substrate is provided with the multilayer symmetrically stacked flash memory chip wafer; and a package body, wherein the package body covers the multilayer symmetrically stacked flash memory chip wafer; characterized in that it further includes a plurality of vertical heat-conducting units, which are made of a high thermal conductivity material and vertically penetrate three layers in the multilayer symmetrically stacked flash memory chip wafer, wherein the two ends of the vertical heat-conducting units are in direct thermal contact with a top heat sink located at the top of the stack body and a bottom heat sink located at the bottom of the stack body, respectively, forming an axial heat dissipation path from the inside to the outside of the chip.

[0005] Preferably, the vertical heat-conducting units are non-uniformly distributed on the plane of the chip stack, wherein the distribution density in the central region A1 of the chip is greater than the distribution density in the edge region A2.

[0006] Preferably, the vertical heat-conducting unit is a solid heat-conducting column.

[0007] Preferably, the material of the solid heat-conducting column includes a metal or carbon-based composite material with a thermal conductivity of not less than 200 W / (m·K).

[0008] Preferably, the bonding layer comprises a high thermal conductivity filler, which includes one of boron nitride nanosheets and alumina nanoparticles, and the thermal conductivity of the bonding layer is greater than 1.5 W / (m·K).

[0009] Preferably, thermally conductive phase change material pads are provided between the top heat sink and the topmost flash memory chip wafer, and between the bottom heat sink and the bottommost flash memory chip wafer.

[0010] Preferably, the inner surface of the top heat dissipation cover is provided with a heat-conducting protrusion, and the heat-conducting protrusion is connected to the upper end face of the vertical heat-conducting unit through a high thermal conductivity interface material.

[0011] Preferably, the packaged substrate further includes a temperature sensing circuit disposed on the packaging substrate and a control unit electrically connected to the temperature sensing circuit, the control unit being configured to dynamically adjust the operating parameters of the flash memory chip according to the temperature.

[0012] Preferably, an insulating thermally conductive adhesive layer is provided between the cross-section of the vertical heat-conducting unit and the inner wall of the through-hole of the flash memory chip wafer.

[0013] Preferably, the outer surface of the package is provided with heat dissipation fins.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. The packaging structure of the symmetrical stacked flash memory chip in this design, by setting a vertical heat conduction unit that penetrates the multilayer flash memory chip wafer vertically, so that its two ends are in direct thermal contact with the top heat sink and the bottom heat sink respectively, constructs an axial heat dissipation path from the inside to the outside of the chip stack; compared with the existing technology, it has the effect of directly and efficiently conducting the heat generated by the core heat source to the external environment, and significantly reducing the internal operating temperature of the chip. 2. The packaging structure of the symmetrical stacked flash memory chip designed in this paper achieves non-uniform configuration of heat dissipation resources by making the distribution density of vertical heat conduction units on the chip plane greater in the central region than in the edge region. Compared with the prior art, it can achieve targeted heat dissipation enhancement in the central region of the chip with greater heat generation, thus optimizing heat dissipation efficiency and material cost. 3. The packaging structure of the symmetrical stacked flash memory chip in this design increases the contact area between the two and reduces the interface thermal resistance by setting a downwardly protruding thermally conductive boss on the inner surface of the top heat sink and connecting it with the upper end face of the vertical heat-conducting unit through a high thermal conductivity interface material. Compared with the prior art, it improves the heat conduction efficiency from the vertical heat-conducting unit to the top heat sink and enhances the overall heat dissipation path efficiency. 4. The packaging structure of the symmetrical stacked flash memory chip in this design uses thermally conductive phase change material pads placed between the top heat sink and the chip, and between the bottom heat sink and the chip. This material absorbs and stores a large amount of heat at the phase change temperature point. Compared with the prior art, it has the effect of buffering temperature fluctuations when the chip experiences a sudden power surge, and preventing the chip from being damaged by thermal shock. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this utility model. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this utility model can produce, should still fall within the scope of the technical content disclosed in this utility model.

[0017] Figure 1 This is an overall schematic diagram; Figure 2 This is a schematic diagram of the exploded structure; Figure 3 This is a schematic diagram of the microstructure of the bonding layer; Figure 4 This is a schematic diagram showing the non-uniform distribution of vertical heat-conducting units on the chip plane. Figure 5 This is a block diagram illustrating the working principle of a temperature sensing and control system.

[0018] Illustrations: 1. Flash memory chip wafer; 2. Bonding layer; 3. Packaging substrate; 4. Package body; 5. Vertical thermal conductive unit; 6. Heat sink cover; 7. Heat sink fin; 8. Material pad; 9. Thermally conductive boss; 10. High thermal conductivity interface material; 11. Temperature sensing circuit; 12. Insulating thermally conductive adhesive layer; 13. Heat sink fins. Detailed Implementation

[0019] To make the utility model's objectives, features, and advantages more apparent and understandable, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0020] In the description of this utility model, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0021] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] This utility model embodiment provides a packaging structure for symmetrically stacked flash memory chips.

[0023] Reference Figure 2 The system includes a multilayer symmetrically stacked flash memory chip wafer 1, with each symmetrically stacked flash memory chip wafer 1 electrically connected by a bonding layer 2; a packaging substrate 3, on the top surface of which the multilayer symmetrically stacked flash memory chip wafer 1 is disposed; and a package body 4, which covers the multilayer symmetrically stacked flash memory chip wafer 1; it also includes multiple vertical heat-conducting units 5, which are made of high thermal conductivity material and vertically penetrate three layers of the multilayer symmetrically stacked flash memory chip wafer 1. The two ends of the vertical heat-conducting units 5 are in direct thermal contact with the top heat sink 6 located at the top of the stack body and the bottom heat sink 7 located at the bottom of the stack body, respectively, forming an axial heat dissipation path from the inside of the chip to the outside. By setting multiple vertical heat-conducting units 5 that vertically penetrate at least three layers of the chip wafer, the unit uses a pure copper solid heat-conducting pillar with a thermal conductivity of 400 W / (m·K). Its two ends are in direct contact with the top heat sink 6 and the bottom heat sink 7, respectively. When the chip is working, the heat generated inside is collected by the vertical heat-conducting units 5 and conducted axially to the heat sink 6 and the heat sink 7, achieving the effect of establishing a direct heat dissipation path from the inside of the chip to the outside.

[0024] Reference Figure 3The vertical heat conduction units 5 are non-uniformly distributed on the plane of the chip stack. The distribution density in the central region A1 of the chip is greater than that in the edge region A2. By setting the non-uniformly distributed vertical heat conduction units 5, with a spacing of 200μm in the central region A1 and 300μm in the edge region A2, when the chip is working, the heat generated in different regions is collected by the heat conduction units of corresponding density, thus achieving the effect of optimizing the heat dissipation resource configuration.

[0025] Reference Figure 2 and Figure 4 Vertical heat-conducting unit 5 is a solid heat-conducting column.

[0026] Reference Figure 1 The solid heat-conducting column is made of metal or carbon-based composite material with a thermal conductivity of not less than 200 W / (m·K). By using the solid heat-conducting column as the vertical heat-conducting unit 5, the heat-conducting column is made of graphene-aluminum composite material with a thermal conductivity of 600 W / (m·K). When heat is conducted along the axial direction, the high thermal conductivity of the material promotes heat flow transfer, thereby further improving the axial heat conduction capability.

[0027] Reference Figure 2 and Figure 4 The bonding layer 2 contains a high thermal conductivity filler. Electrical connections are achieved through a microbump array. The tin-silver-copper microbumps of the bonding layer 2 engage with the slotted areas of the multilayer symmetrically stacked flash memory chip wafer 1, ensuring sufficient current path. The high thermal conductivity filler is in direct contact with the silicon material on the back side of the multilayer symmetrically stacked flash memory chip wafer 1, establishing an efficient heat conduction path from the wafer heat source to the bonding layer 2. The high thermal conductivity filler of the bonding layer 2 conducts heat laterally to the vertical heat conduction unit 5, forming a ring-shaped efficient heat conduction zone around the vertical heat conduction unit 5. The heat collected by the bonding layer 2 is transferred through two sides... The heat is conducted upwards through the stacked bonding layer 2 to the top heat sink 6, and downwards through the substrate to the bottom heat sink 7. The high thermal conductivity filler includes one of boron nitride nanosheets and alumina nanoparticles. The thermal conductivity of the bonding layer 2 is greater than 1.5 W / (m·K). By using the bonding layer 2 doped with boron nitride nanosheets, the bonding layer 2 forms a connection between the chip wafers. The thermal conductivity is 2.0 W / (m·K). When heat is transferred between chip layers, the high thermal conductivity bonding layer 2 promotes the lateral diffusion of heat, thereby preventing local heat accumulation.

[0028] Reference Figure 2Thermally conductive phase change material pads 8 are provided between the top heat sink 6 and the topmost flash memory chip wafer 1, and between the bottom heat sink 7 and the bottommost flash memory chip wafer 1. By providing paraffin-based thermally conductive phase change material pads 8 on the upper and lower surfaces of the chip, and by placing the pads between the heat sink 6 and the chip, and between the heat sink 7 and the chip, the phase change temperature is 75°C. When the temperature exceeds the phase change point, the material undergoes a phase change and absorbs heat, thereby achieving the effect of buffering temperature fluctuations and preventing thermal shock.

[0029] Reference Figure 2 The inner surface of the top heat sink cover 6 is provided with a heat-conducting protrusion 9. The heat-conducting protrusion 9 is connected to the upper end face of the vertical heat-conducting unit 5 through a high thermal conductivity interface material 10. By providing a heat-conducting protrusion 9 on the inner surface of the top heat sink cover 6, and welding the protrusion to the upper end face of the vertical heat-conducting unit 5 with tin-silver solder, when heat is transferred upward from the vertical heat-conducting unit 5, the increased contact area and welding connection reduce the interface thermal resistance, thereby achieving the effect of improving heat conduction efficiency.

[0030] Reference Figure 1 and Figure 5 It also includes a temperature sensing circuit 11 disposed on the packaging substrate 3, and a control unit electrically connected to the temperature sensing circuit 11. The control unit is configured to dynamically adjust the operating parameters of the flash memory chip according to the temperature. By integrating the temperature sensing circuit 11 on the packaging substrate 3, and connecting the circuit to an external control unit, when the chip temperature changes, the temperature sensing circuit 11 monitors the temperature data in real time, and the control unit adjusts the chip operating parameters according to a preset strategy, thereby achieving the effect of dynamically managing the thermal state of the chip.

[0031] Reference Figure 2 and Figure 4 An insulating thermally conductive adhesive layer 12 is provided between the cross-section of the vertical heat-conducting unit 5 and the inner wall of the through hole of the flash memory chip wafer 1. By filling the space between the vertical heat-conducting unit 5 and the inner wall of the chip through hole with an insulating thermally conductive adhesive layer 12, which is made of silicone-based material with a thermal conductivity of 1.2 W / (m·K), when heat is transferred at the interface, the insulating thermally conductive adhesive layer 12 provides electrical insulation while filling the micro-gaps, thereby reducing the interface thermal resistance and preventing short circuits.

[0032] Reference Figure 1 The outer surface of the package 4 is provided with heat dissipation fins 13. By providing heat dissipation fins 13 on the outer surface of the package 4, the fins are integrally formed with the package 4 and have a height of 1mm. When heat is conducted to the surface of the package 4, the increased surface area promotes heat convection and achieves the effect of enhancing the overall heat dissipation capacity.

[0033] The working principle of this invention is as follows: First, a vertically penetrating heat-conducting unit 5 is used to connect the top heat sink 6 and the bottom heat sink 7 at both ends, forming an axial heat dissipation channel. When the chip is working, the heat generated inside is quickly collected by the vertical heat-conducting unit 5 and conducted axially to the top heat sink 6 and the bottom heat sink 7, and finally dissipated to the external environment through convection and radiation. This design achieves efficient heat conduction from the core area inside the chip to the external environment, significantly improving heat dissipation efficiency. Second, a transverse auxiliary heat dissipation network is constructed by using a bonding layer 2 with high thermal conductivity filler and placing thermally conductive phase change material pads 8 on the upper and lower surfaces of the chip. The bonding layer 2 promotes lateral heat diffusion between layers while achieving electrical connection, preventing local overheating. The thermally conductive phase change material pad 8 undergoes a phase change to absorb heat when the temperature rises, acting as a temperature buffer. These structures work together to achieve uniform heat distribution and effective management. Finally, an intelligent thermal management system is constructed by integrating a temperature sensing circuit 11 on the packaging substrate 3 and connecting it to a control unit. When the temperature sensing circuit 11 detects a change in chip temperature, the control unit dynamically adjusts the chip's operating parameters according to a preset algorithm. This system realizes real-time monitoring and intelligent control of the chip's thermal state, improving the chip's thermal stability under different workloads.

[0034] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A packaging structure for symmetrically stacked flash memory chips, comprising multilayer symmetrically stacked flash memory chip wafers (1), wherein each symmetrically stacked flash memory chip wafer (1) is electrically connected to the others via a bonding layer (2); a packaging substrate (3), wherein the top surface of the packaging substrate (3) is provided with the multilayer symmetrically stacked flash memory chip wafers (1); and a package body (4), wherein the package body (4) covers the multilayer symmetrically stacked flash memory chip wafers (1); characterized in that, It also includes multiple vertical heat conduction units (5), which are made of high thermal conductivity materials and vertically penetrate three layers in the multilayer symmetrical stacked flash memory chip wafer (1). The two ends of the vertical heat conduction unit (5) are in direct thermal contact with the top heat sink (6) located at the top of the stack and the bottom heat sink (7) located at the bottom of the stack, respectively, forming an axial heat dissipation path from the inside of the chip to the outside.

2. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, The vertical heat-conducting units (5) are non-uniformly distributed on the plane of the chip stack, wherein the distribution density in the central region A1 of the chip is greater than the distribution density in the edge region A2.

3. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, The vertical heat-conducting unit (5) is a solid heat-conducting column.

4. The packaging structure of a symmetrically stacked flash memory chip according to claim 3, characterized in that, The solid heat-conducting column is made of metal or carbon-based composite material with a thermal conductivity of not less than 200 W / (m·K).

5. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, The bonding layer (2) contains a high thermal conductivity filler, which includes one of boron nitride nanosheets and alumina nanoparticles, and the thermal conductivity of the bonding layer (2) is greater than 1.5 W / (m·K).

6. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, Thermally conductive phase change material pads (8) are provided between the top heat sink (6) and the topmost flash memory chip wafer, and between the bottom heat sink (7) and the bottommost flash memory chip wafer.

7. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, The inner surface of the top heat dissipation cover (6) is provided with a heat-conducting protrusion (9), and the heat-conducting protrusion (9) is connected to the upper end face of the vertical heat-conducting unit (5) through a high thermal conductivity interface material (10).

8. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, It also includes a temperature sensing circuit (11) disposed on the packaging substrate (3) and a control unit electrically connected to the temperature sensing circuit (11), the control unit being configured to dynamically adjust the operating parameters of the flash memory chip according to the temperature.

9. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, An insulating thermally conductive adhesive layer (12) is provided between the cross-section of the vertical heat-conducting unit (5) and the inner wall of the through hole of the flash memory chip wafer (1).

10. The packaging structure of a symmetrically stacked flash memory chip according to claim 1, characterized in that, The outer surface of the package (4) is provided with heat dissipation fins (13).

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