Semiconductor element and semiconductor inductor structure

Abstract

A semiconductor device and a semiconductor inductor structure are disclosed. The semiconductor device includes a transistor including a source, a drain and a gate on a substrate, and an inductor structure on the substrate. The inductor structure includes a first spiral conductive structure and a second spiral conductive structure adjacent to the first spiral conductive structure to provide an inductance between the first spiral conductive structure and the second spiral conductive structure. One of the first spiral conductive structure and the second spiral conductive structure is electrically connected to at least one of the source, the drain and the gate of the transistor. At least a portion of the second spiral conductive structure is laterally interposed between adjacent portions of the first spiral conductive structure, which are substantially parallel to the portion of the second spiral conductive structure.

Description

Technical Field

[0001] This disclosure pertains to semiconductor devices. Background Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit elements and their components on them.

[0003] The semiconductor industry is continuously increasing the integration of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed.

[0004] For example, many circuits use inductors to filter signals in mixed-signal components and logic devices (such as embedded memory and RF components). However, existing inductor structures disadvantageously limit design flexibility and component density. Utility Model Content

[0005] Some embodiments described herein provide a semiconductor device comprising a transistor and an inductor structure. The transistor includes a source, a drain, and a gate on a substrate, and an inductor structure on the substrate. The inductor structure includes a first helical conductive structure and a second helical conductive structure adjacent to the first helical conductive structure to provide an inductance between the first and second helical conductive structures. At least one of the first and second helical conductive structures is electrically connected to one of the source, drain, or gate of the transistor. At least a portion of the second helical conductive structure is laterally interposed between adjacent portions of the first helical conductive structure, the adjacent portions of the first helical conductive structure being arranged substantially parallel to portions of the second helical conductive structure.

[0006] Some embodiments described herein provide a semiconductor inductor structure comprising: a first helical structure composed of a conductive material in an interconnect layer above a semiconductor substrate, the interconnect layer comprising the conductive material and the conductive material disposed in a dielectric material layer; a second helical structure composed of a conductive material in the interconnect layer above the semiconductor substrate, wherein portions of the second helical structure are arranged substantially parallel to adjacent portions of the first helical structure; one or more intervening portions of the dielectric material layer disposed between portions of the second helical structure and corresponding adjacent portions of the first helical structure; a first via in the interconnect layer between the first helical structure and a first conductive region on the semiconductor substrate; and a second via in the interconnect layer between the second helical structure and a second conductive region on the semiconductor substrate.

[0007] Some embodiments described herein provide a semiconductor element comprising: a transistor including a source, a drain, and a gate on a substrate; and an inductor structure located on the substrate, the inductor structure including a first helical conductive structure and a second helical conductive structure adjacent to the first helical conductive structure to provide inductance between the first helical conductive structure and the second helical conductive structure, wherein one of the first helical conductive structure and the second helical conductive structure is electrically connected to at least one of the source, drain, and gate of the transistor, wherein at least a portion of the second helical conductive structure is laterally inserted between adjacent portions of the first helical conductive structure, adjacent portions of the first helical conductive structure being arranged substantially parallel to portions of the second helical conductive structure, and wherein the first helical conductive structure and the second helical conductive structure are staggered. Attached Figure Description

[0008] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0009] Figure 1 This is a schematic diagram of an example circuit according to each embodiment;

[0010] Figure 2 To be applicable according to each embodiment Figure 1 A top view of the semiconductor inductor structure of the circuit;

[0011] Figure 3 for Figure 2 The semiconductor inductor structure along Figure 2 Sectional view of line 3-3;

[0012] Figure 4 and Figure 5 To be applicable according to each embodiment Figure 1A top view of the alternative semiconductor inductor structure for the circuit;

[0013] Figures 6 to 16 Cross-sectional views of various manufacturing stages of an exemplary semiconductor inductor structure according to various embodiments;

[0014] Figure 17 A flowchart of an exemplary process for manufacturing a semiconductor inductor structure according to various embodiments;

[0015] Figure 18 This is a top view of the alternative semiconductor inductor structure according to each embodiment;

[0016] Figure 19 This is a top view of an alternative semiconductor inductor structure according to various embodiments.

[0017] [Symbol Explanation]

[0018] 100: Circuit

[0019] 101: Endpoint

[0020] 102: Input Interface

[0021] 103: Endpoint

[0022] 104: Filtration device

[0023] 106: Electronic Circuits

[0024] 108: Endpoint

[0025] 110: Inductive components / inductors

[0026] 112: Capacitor Component

[0027] 1000, 1002, 1004: Spacers

[0028] 1100, 1102, 1104: Spacing Zones / Spacers

[0029] 1202, 1204: Vacuum areas

[0030] 1300: Metallic Materials

[0031] 1302, 1304: Areas

[0032] 1400: Inductor Structure

[0033] 1402: Conductive via

[0034] 1404: Conductive Structure

[0035] 1406: Conductive Structure

[0036] 1408: Lateral spacing distance

[0037] 1410: Metal interconnect layer

[0038] 1418: Horizontal width

[0039] 1700: Manufacturing Process

[0040] 1702, 1704, 1706, 1708, 1710: Steps

[0041] 1800: Area

[0042] 1802: Through hole

[0043] 1900: Inductor Structure

[0044] 1904: Conductive Structure

[0045] 1906: Conductive Structure

[0046] 200, 400, 500: Inductor Structure

[0047] 202:Substrate

[0048] 204, 206: Conductive structure

[0049] 205, 207: Connecting areas

[0050] 208: Spacing

[0051] 209: Intervention Part

[0052] 210: Common Points / Central Point

[0053] 212: Axis

[0054] 214: Inner End

[0055] 216: Inner End

[0056] 218: Horizontal width

[0057] 219: Pitch Dimension

[0058] 220: Insulating materials

[0059] 224: External

[0060] 226: External

[0061] 302: Insulating material

[0062] 304: Area

[0063] 306: Area

[0064] 310, 320, 330: Layers

[0065] 312: Conductive metallic materials

[0066] 314: Conductive materials

[0067] 315, 325, 335: Etching stop layer

[0068] 316: Intermetallic dielectric layer / IMD material layer

[0069] 322, 332: Metallic material layer

[0070] 324, 334: Conductive through-hole materials

[0071] 326, 336: IMD material layer

[0072] 3-3: Line

[0073] 404, 406: Conductive structure

[0074] 414, 416: Inner end

[0075] 424,426: External

[0076] 504, 506: Conductive structure

[0077] 514, 516: Inner end

[0078] 524,526: External terminals

[0079] 600:Substrate

[0080] 602, 604: Areas

[0081] 606: Dielectric material layer

[0082] 700: Intermetallic dielectric layer / IMD material layer

[0083] 701: Etching Stop Layer

[0084] 702: Masking material layer

[0085] 704: Masking material layer

[0086] 802, 804: Vacuum areas

[0087] 900: Interstitial material layer

[0088] Metal-1 layer: Metal-1 layer

[0089] VIA: Via Detailed Implementation

[0090] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting.

[0091] For ease of description, conventional techniques associated with the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various operations and processes described herein can be incorporated into a more comprehensive process or a process with additional functions not detailed herein. Specifically, various processes in semiconductor device manufacture are well-known; therefore, for the sake of brevity, many conventional processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon a full reading of this disclosure that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products.

[0092] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various elements, components, regions, layers, parts, and / or segments, these elements, components, regions, layers, parts, and / or segments should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, part, or segment from another element, component, region, layer, part, or segment. Therefore, the first element, component, region, layer, part, or segment discussed below may be referred to as the second element, component, region, layer, part, or segment without departing from the meaning of the terms in this disclosure.

[0093] Additionally, for ease of description, spatial relative terms such as “over,” “overlying,” “above,” “upper,” “top,” “under,” “underlying,” “below,” “lower,” and “bottom,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0094] Furthermore, references to numbers and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not, in itself, define the relationships between the various embodiments and / or configurations discussed.

[0095] It should be noted that the terms "an embodiment," "an exemplary embodiment," "example," and "exemplary" used in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, these terms do not necessarily refer to the same embodiment. In other words, when a particular feature, structure, or characteristic is associated with an embodiment, those skilled in the art may be able to influence that feature, structure, or characteristic in other embodiments, whether or not it is explicitly described.

[0096] In some embodiments herein, "material layer" refers to a layer comprising at least 50 wt.% of the identified material, such as at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of the identified material; and "material layer" similarly refers to a layer comprising at least 50 wt.% of the identified material, such as at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of the identified material. For example, in some embodiments, each aluminum layer and each layer of aluminum is a layer of at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% aluminum.

[0097] It should be understood that the words or terms used in this disclosure are for descriptive purposes only and not for limitation. Therefore, the terms or terms specified herein should be interpreted by those skilled in the art in light of this.

[0098] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the travel of a first feature over or above a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. In the description of this disclosure, unless otherwise stated, the same reference numerals in different figures refer to the same or similar components formed by the same or similar methods using the same or similar materials.

[0099] In these embodiments, additional operations may be provided before, between, and / or after the described stages. Some described stages may be replaced or omitted in different embodiments. Additional features may be added to the semiconductor device structure. Some features described below may be replaced or omitted in different embodiments. Although some embodiments perform operations in a specific order, these operations may also be performed in other logical orders.

[0100] The term "layer" as used here refers to a region, such as an area with arbitrary boundaries, which does not necessarily have a uniform thickness. For example, a layer can be a region with some variation in thickness.

[0101] Figure 1 An exemplary embodiment of circuit 100 suitable for implementation in an integrated circuit or other semiconductor device package is illustrated. Circuit 100 includes an input interface 102, which includes corresponding input endpoints 101 and 103, which typically represent pins, connectors, endpoints, ports, or other inputs associated with circuit 100, capable of being connected to or otherwise coupled to a circuit board, wiring, or other similar object to establish an electrical connection between circuit 100 and external devices, components, or systems, such as power sources (e.g., buses, batteries (or battery packs), and / or the like).

[0102] An input filtering device 104 is coupled between the input interface 102 and the electronic circuitry 106 associated with circuitry 100. In this respect, electronic circuitry 106 generally represents any type, configuration, or combination of active or passive electronic components or systems suitably configured to provide the required functionality of circuitry 100. For example, electronic circuitry 106 may include, but is not limited to, one or more transistors, diodes, memory modules, resistors, capacitors, inductors, sensors, amplifiers, receivers, transmitters, microelectromechanical systems (MEMS) elements, and / or the like. For example, electronic circuitry 106 may include transistors such as MOSFETs, CMOS transistors, BJTs, high-voltage transistors, high-frequency transistors, p-channel FETs, and / or n-channel FETs, suitably configured to provide the required functionality for circuitry 100.

[0103] The input filtering device 104 shown depicts an LC filter comprising an inductor 110 (or inductor) electrically connected in series between an input terminal 101 of the input interface 102 and another terminal 108 of the corresponding input to the electronic circuit 106, to provide series inductance between the respective terminals 101 and 108. The input filtering device 104 also includes a capacitor 112 (or capacitor) electrically connected between the corresponding input terminal 108 of the electronic circuit 106 and another input terminal 103 of the input interface 102, to provide capacitance between terminals 103 and 108 that is electrically connected in parallel with the electronic circuit 106. In this respect, the input filtering device 104 can be configured as a low-pass filter to maintain a substantially constant direct current (DC) voltage between the corresponding terminals 103 and 108 coupled to the electronic circuit 106. Nevertheless, it should be understood that the subject matter described herein is not limited to low-pass filters, and in other embodiments, the filtering device 104 may be configured as a band-pass filter, a high-pass filter, or other suitable filter structure, the precise implementation details of which are not closely related to the subject matter described herein. Furthermore, Figure 1 The depiction is not limiting; in fact, terminal 101 may be electrically connected to different embodiments of electronic circuit 106 to provide series inductance between different circuits, as appropriate.

[0104] Figure 2 and Figure 3 It is illustrated as suitable for use as Figure 1 An exemplary embodiment of the inductor structure 200 of the inductor 110 in circuit 100. In this regard, Figure 2 A top view of a portion of an exemplary semiconductor device is shown, which includes an inductor structure 200 fabricated on or covering a portion of a semiconductor substrate 202. Figure 3 A cross-sectional view of a portion of the inductor structure 200 along line 3-3 is shown. In this regard, Figure 3 An embodiment corresponding to a multilayer inductor structure 200 fabricated within multiple vertical layers 310, 320, and 330 is illustrated; however, it should be understood that, in practice, the inductor structure 200 may be a single-layer inductor structure within a single layer. Furthermore, it should be noted that, for illustrative purposes, the subject matter can be described in the context of multilayer inductor structures with substantially the same lateral geometry between different vertical layers, whereas in other embodiments, the lateral geometry of a portion of a multilayer inductor structure fabricated within a respective layer may differ from the lateral geometry of another portion of a multilayer inductor structure fabricated within the vertical layer below or above.

[0105] Please refer to Figure 2The inductor structure 200 includes a first external conductive structure 204, which is laterally spaced from a second internal conductive structure 206 by a lateral spacing 208. This lateral spacing 208 is occupied by an insertion portion 209 of an insulating material 220. Because the insertion portion 209 of the insulating material 220 occupies the lateral spacing 208 between the conductive structures 204 and 206, the insulating material 220 provides lateral isolation between the corresponding conductive structures 204 and 206. The lateral spacing 208 is less than a maximum threshold spacing distance to allow time-varying or alternating voltage differences between the corresponding conductive structures 204 and 206 to generate an effective current through the inductor structure 200 via electromagnetic induction. In some embodiments, the lateral spacing 208 is in the range of approximately 10 nanometers (nm) to approximately 25 nm. In practice, the lateral spacing 208 can be varied according to the needs of a specific application to achieve the required electrical performance and reliability.

[0106] As detailed below, in some embodiments, the corresponding conductive structures 204 and 206 are defined and fabricated in accordance with the definition of the lateral spacing 208 during the back-end process (BEOL) stage. This allows the corresponding lateral widths 218 of the corresponding conductive structures 204 and 206 to be similarly reduced to a range of approximately 10 nm to approximately 25 nm, roughly corresponding to the lateral spacing 208. For example, the ratio of the lateral spacing 208 to the lateral width 218 can be in the range of approximately 0.8 to approximately 1.5. This allows the pitch dimension 219 of the inductor structure 200 (i.e., the combination of the lateral width 218 and the spacing 208) to be reduced to a range of approximately 20 nm to approximately 50 nm, which in turn allows for an increase in the turns density of the inductor structure 200 by accommodating a greater number of turns per unit area. For example, in some embodiments, the turns density of the inductor structure 200 can be increased by approximately 100 times, thereby achieving a larger inductance per unit area (where the inductance is proportional to the square of the turns) and increasing design flexibility by using an inductor structure capable of achieving higher or wider ranges of potential inductance densities. In this regard, Figure 2 An embodiment is depicted in which the outer conductive structure 204 comprises 2.5 turns (e.g., two 360° rings plus one 180° ring) and the inner conductive structure 206 comprises 2 turns, while Figure 19 An embodiment of inductor structure 1900 is depicted, wherein for approximately the same area unit, outer conductive structure 1904 comprises 3.5 turns and inner conductive structure 1906 comprises 3 turns, wherein the inductance is proportional to the square of the number of turns. It should be noted that although the subject matter is described herein in the context that the respective lateral widths 218 of conductive structures 204 and 206 are approximately equal to each other, in practice, the lateral widths of conductive structures 204 and 206 may differ from each other.

[0107] like Figure 3 As illustrated, at least a connecting portion of the first conductive structure 204 covers and contacts a region 304 of the conductive material, or is formed thereon (the region 304 of the conductive material is formed in or on the semiconductor substrate 202), to provide an electrical connection between the first conductive structure 204 and the lower conductive region 304 of the semiconductor substrate 202. Similarly, at least a connecting portion of the second conductive structure 206 covers and contacts a second region 306 of the conductive material, or is formed thereon (the second region 306 of the conductive material is formed in or on the semiconductor substrate 202), to provide an electrical connection between the first conductive structure 204 and the second conductive region 306 of the semiconductor substrate 202. The respective conductive regions 304 and 306 are electrically isolated from each other by an insulating material 302 laterally disposed between the respective conductive regions 304 and 306. For example, the insulating material 302 may be an oxide layer, wherein the conductive regions 304 and 306 may be corresponding regions of a metallic material or other conductive material layer formed within or on the insulating material 302. In this regard, the first conductive region 304 may be a metal line or trace configured to provide an electrical connection between the first conductive structure 204 and a corresponding input terminal 101 of the circuit 100 fabricated on the semiconductor substrate 202, wherein the second conductive region 306 is served as a metal line or trace configured to provide an electrical connection between the second conductive structure 206 and different terminals 108 of the circuit 100, such that the inductor structure 200 provides a series inductance between corresponding terminals 101 and 108 of the circuit 100.

[0108] Figure 2An exemplary lateral geometry is depicted, wherein each conductive structure 204, conductive structure 206 has a generally helical shape and is laterally located within a corresponding layer on the semiconductor substrate 202. The helical conductive structures 204, helical conductive structures 206 are arranged in an interlocking or staggered configuration, such that a corresponding portion of another helical conductive structure 204, helical conductive structure 206 is laterally inserted between adjacent (or laterally adjacent) portions of the corresponding conductive structure 204, conductive structure 206. In this respect, the corresponding helical conductive structures 204, helical conductive structures 206 are substantially concentric with a common point 210, which may be located or otherwise oriented at or near the geometric center of the inductor structure 200. For example, the inner ends 214 and 216 of the corresponding spiral conductive structures 204 and 206 can be symmetrically arranged around the center point 210 of each spiral, and laterally offset by approximately equal distances from the center point 210 in opposite directions, such that the midpoints of the inner ends 214 and 216 are coaxially aligned along the axis 212, which passes through the center point 210 intersecting the midpoints of the inner ends 214 and 216.

[0109] Figure 2 The lateral geometry corresponds to a rectangular or square spiral shape, wherein the corresponding spiral conductive structures 204 and 206 radiate outward from the inner ends 214 and 216 through a series of linear segments. The length of these linear segments gradually increases and they meet or intersect at approximately 90° angles. The lateral offset distance of the parallel linear segments of the corresponding spiral conductive structures 204 and 206 is equal to twice the spacing distance 208 between the spiral conductive structures 204 and 206, plus the lateral width 218 of the intermediate parallel portion between the spiral conductive structures 204 and 206. In this regard, in some embodiments, the spiral conductive structures 204 and 206 may remain approximately symmetrical to each other over a cumulative length equal to the length of the inner conductive structure 206 (e.g., the length of the conductive structure 206 from the inner end 216 to the outer end 226). In addition to the length of the inner conductive structure 206, the outer conductive structure 204 may include three additional linear segments whose lengths gradually increase to reach the outer end 224 of the outer conductive structure 204. This outer end 224 is laterally aligned substantially parallel to the outer end 226 of the inner conductive structure 206, such that the axis aligned with the corresponding outer ends 224 and 226 is substantially perpendicular to the outer linear segments of the corresponding conductive structures 204 and 206. Therefore, the outer conductive structure 204 may be asymmetrical relative to the inner conductive structure 206 in order to substantially confine the inner conductive structure 206 within a corresponding layer on the semiconductor substrate 202.

[0110] See Figure 3 And continue to refer to Figure 2In one or more embodiments, the inductor structure 200 is configured as a multilayer inductor structure formed on or covering the semiconductor substrate 202 using one or more layers 310, 320, 330. For example, in Figure 3 In the illustrated embodiment, the inductor structure 200 may use three layers 310, 320, 330 formed on the semiconductor substrate 202, such as one or more metal interconnect layers formed during the BEOL process stage. In this regard, the outer spiral conductive structure 204 may be implemented as a corresponding spiral structure of the conductive metal material 312 of the first metal layer 310, which is patterned to provide a corresponding spiral structure within the intermetallic dielectric (IMD) material layer 316, and the inner spiral conductive structure 206 may be a corresponding spiral structure of the conductive metal material 312 within the IMD material 316. As shown in the figure, the corresponding portions of the conductive via material 314 formed in the corresponding connection regions 205 and 207 of the IMD material layer 316 and the etch stop layer 315 are used to electrically connect the corresponding structures 204 and 206 of the conductive metal material 312 to the corresponding conductive regions 304 and 306 on the lower substrate 202. The etch stop layer 315 is located at or near the outer ends 224 and 226 of the spiral conductive structures 204 and 206 covering the conductive regions 304 and 306. Similarly, the spiral conductive structures 204 and 206 can extend vertically through the additional metal layers 320 and 330 in a similar manner, by forming the corresponding spiral structures 204 and 206 in the corresponding metal material layers 322 and 332. These metal material layers are laterally separated from each other and are separated from the intervention portions of the corresponding IMD material layers 326 and 336 and the corresponding etch stop layers 325 and 335, and are perpendicularly connected to each other through the corresponding portions of the conductive via materials 324 and 334.

[0111] It should be noted that when the inductor structure 200 is used as... Figure 3 In the multilayer inductor structure shown, the geometry or configuration of the lateral inductor structures formed within each of the respective metal interconnect layers 310, 320, and 330 can differ from one another between layers. In this regard, the size, orientation, and / or shape of the lateral inductor structures formed in the lower metal interconnect layer 310 can differ from the lateral inductor structures formed in the covering metal interconnect layers 320 and 330. For example, Figure 4 and Figure 5 Alternative inductor structures 400 and 500 suitable for implementation within one or more of the metal interconnect layers 310, 320, and 330 are depicted. In this regard, Figure 4The diagram illustrates a spiral inductor structure 400 having an octagonal or octagonal lateral geometry, its outer periphery composed of a series of generally linear segments that meet or intersect at approximately 135° angles, but whose length gradually increases from the innermost segment to the outermost segment, such that the octagonal spiral conductive structures 404 and 406 radiate outwards in an octagonal shape from the inner ends 414 and 416 to the outer ends 424 and 426. In another embodiment, Figure 5 The illustration depicts a hexagonal inductor structure 500 with a hexagonal lateral geometry. Its outer periphery consists of a series of linear segments that meet or intersect at approximately 120° angles, with their lengths gradually increasing from the innermost to the outermost segment. This results in hexagonal hexagonal conductive structures 504 and 506 radiating outwards in a hexagonal pattern from their inner ends 514 and 516 to their outer ends 524 and 526. It should be noted that the different shapes of inductor structures 200, 400, and 500 provide design flexibility, and the subject matter described herein is not necessarily limited to specific shapes of inductor structures.

[0112] It should be understood that the subject matter described herein is not necessarily limited to having rectangular (e.g., inductor structure 200), pentagonal, hexagonal (e.g., inductor structure 500), octagonal (e.g., inductor structure 400), or other geometric arrangements, and can be implemented in an equivalent manner using any type of rectangular, elliptical, spiral, or other suitable helical geometry. Furthermore, the subject matter described herein is not necessarily limited to any particular combination or configuration of inductor structures. For example, in some embodiments, a multilayer inductor structure may comprise a combination of one or more rectangular helical lateral inductor structures 200, one or more hexagonal helical lateral inductor structures 500, and / or one or more octagonal helical lateral inductor structures 400, while in other embodiments, a multilayer inductor structure may comprise substantially the same helical lateral inductor structure for each respective layer of the multilayer inductor structure.

[0113] In addition to changing the lateral geometry or configuration of the helical inductor structures within the corresponding lateral layers, the total inductance (or inductance per unit area) associated with the corresponding helical inductor structure can be increased or decreased by changing the number of turns per unit area. Furthermore, the lateral spacing 208 between the individual helical conductive structures 204 and 206, and / or the lateral width 218 of each helical conductive structure 204 and 206, can be varied within the respective lateral layers to achieve a corresponding increase or decrease in the total inductance (or inductance per unit area). In this regard, reducing the lateral spacing 208 can increase the inductance density associated with a particular helical inductor structure by increasing electromagnetic interference or coupling between the helical conductive structures 204 and 206, thereby increasing the inductance while simultaneously reducing the total lateral area required for the corresponding lateral inductor structure. Therefore, the subject matter described herein is not limited to any particular size or other geometric configuration of the helical inductor structure, as circuit designers can change the lateral geometry and pitch dimensions of the helical inductor structure to achieve the desired inductance (or desired inductance density) for a particular application within the available area on a given substrate for fabrication.

[0114] Figures 6 to 16 A cross-sectional view illustrates one or more methods for fabricating an inductor structure 1400 suitable as a spiral inductor structure (e.g., one of structures 200, 400, 500) within a metal interconnect layer 1410, wherein, according to an embodiment, a self-aligned double patterning process is used during integrated circuit fabrication. Various steps in semiconductor device fabrication are well-known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned or omitted entirely without providing well-known process details. In this regard, in some embodiments, the inductor structure 1400 is fabricated in one or more BEOL process stages after transistors or other electronic circuitry (e.g., electronic circuitry 106) has been fabricated on a semiconductor substrate. For example, the inductor structure 1400 may be formed during the fabrication of one or more metal interconnect layers, for example, as part of a self-aligned double patterning process stage.

[0115] Figure 6The illustration depicts a stage in the integrated circuit manufacturing process following the fabrication of a semiconductor substrate 600, which includes corresponding regions 602 and 604 of conductive metal material fabricated within a dielectric material layer 606, such as silicon oxide or another oxide material suitable for use as an intermetallic dielectric, providing lateral electrical isolation between the respective metal regions 602 and 604. The conductive regions 602 and 604 typically correspond to wiring, traces, or other electrical connections to / from the respective endpoints of the inductor structure 1400 (e.g., endpoints 101 and 108 of inductor 110), which are fabricated within a metal interconnect layer containing the intermetallic dielectric material 606. For example, one of regions 602 and 604 may be electrically connected to the source, drain, or gate electrode of one or more transistors fabricated on or within the underlying semiconductor material of the substrate, while the other regions 602 and 604 may be electrically connected to the input and / or output terminals of the circuit 100 fabricated on the substrate, or to the source, drain, or gate electrode of different transistors fabricated on or within the underlying semiconductor material of the substrate, such that the inductor structure fabricated on the substrate effectively provides a series inductance between the metal regions 602 and 604.

[0116] like Figure 7 As illustrated, the integrated circuit manufacturing process continues to form an etch stop layer 701 covering the semiconductor substrate and an inter-metal dielectric (IMD) material layer 700 covering the semiconductor substrate. For example, the IMD material 700 can be implemented as silicon oxide or another suitable dielectric material, uniformly deposited on or covering the upper surface of the semiconductor substrate 600, with a thickness in the range of about 40 nanometers to about 70 nanometers. After forming the IMD material layer 700, the integrated circuit manufacturing process continues to form a hard mask material layer 702 covering the IMD material layer 700, for example, by uniformly depositing or covering the upper surface of the IMD material layer 700 with a silicon nitride material layer, with a thickness in the range of about 100 angstroms to about 500 angstroms. The manufacturing process then continues by forming another masking material layer 704 covering the hard masking material layer 702, for example, by uniformly depositing or covering the upper surface of the hard masking material layer 702 with a thickness ranging from about 300 angstroms to about 700 angstroms. The etch stop layer 701 has different etch selectivity than the IMD material 700 to provide a mechanism for stopping the etching process when contacts, vias, or other structures are formed within the IMD material 700. The etch stop layer 701 may comprise or be aluminum nitride, silicon carbonitride, silicon carbide, carbon nitride, etc., or combinations thereof. The etch stop layer 701 may be deposited using a plasma-assisted chemical vapor deposition process, a high-density plasma chemical vapor deposition process, an atomic layer deposition process, or other suitable deposition processes.

[0117] Please refer to Figure 8 The manufacturing process continues by patterning and anisotropically (or oriented) etching the mask material layer 704 using appropriate lithography and etching techniques as part of a self-aligned dual patterning process to define a void region 802, a void region 804 within the mask material 704 for a first region of conductive metal material, which is physically different from one or more other regions of conductive metal material within the corresponding metal interconnect layer. To fabricate the inductor structure, a masking material 704 is patterned and etched to define open regions 802 and 804 within the masking material 704. These open regions 802 and 804 cover corresponding metal regions 602 and 604 of one of the spiral conductive structures (e.g., outer conductive structures 204, 404, and 504) and the insertion portion of the IMD material 700 (e.g., insertion portion 209). The remaining portion of the masking material 704 defines the corresponding lateral position and configuration of another spiral conductive structure (e.g., inner conductive structures 206, 406, and 506). In this regard, the empty regions 802 and 804 are used to define the lateral boundaries and corresponding lateral positions of the subsequently formed spacers, which define the corresponding lateral spacing distance 1408 and lateral width 1418 of the outer spiral conductive structure 1404 of the final inductor structure 1400, while the remaining portion of the IMD material 700 defines the corresponding lateral position and lateral width of the inner spiral conductive structure 1406, as described in more detail below.

[0118] like Figure 9 As shown, as part of a self-aligned dual patterning process, after forming a void region 802 within a mask material layer 704, the manufacturing process continues by forming a gap material layer 900 covering the semiconductor substrate. For example, the gap material layer 900 can be formed by uniformly depositing an oxide material layer on and covering the upper surface of the hard mask material 702 to a thickness ranging from about 60 to about 200 nm. Figure 10As shown, after forming the gap material layer 900, the manufacturing process continues by anisotropically (or orientedly) etching the gap material layer 900 to remove the gap material 900 from the flat surface, thereby forming sets of spacers 1000, 1002, and 1004 that are self-aligned relative to the inner sidewalls of the empty regions 802 and 804. In this regard, the use of self-aligned spacers 1000, 1002, and 1004 for subsequent masking reduces the corresponding lateral width 1418 of the conductive structures 1404 and 1406, and / or reduces the lateral spacing distance 1408 by using conductive structures 1404 and 1406 with smaller spacing dimensions and higher aspect ratios than those formed solely by the mask material layer 704 and / or the hard mask material 702. Therefore, in some embodiments, the gap material layer 900 may be formed to a thickness corresponding to the desired lateral spacing distance 1408 between the helical conductive structures 1404 and 1406 and / or the desired lateral width 1418 of the helical conductive structures 1404 and 1406. In other embodiments, the thickness of the gap material layer 900 may be limited by other circuitry or interconnects fabricated on the semiconductor substrate, in which case the lateral spacing distance 1408 and / or lateral width 1418 are controlled by the definition of the empty regions 802 and 804. In practice, the gap material layer 900 and the underlying masking material 704 are anisotropically etched to a distance or depth greater than or equal to the thickness of the gap material 900 to remove a portion of the gap material 900 from the generally flat surface of the semiconductor substrate, thereby creating spacers 1000, 1002, and 1004 that define the helical conductive structures 1404 and 1406 and the lateral spacing distance 1408.

[0119] Please refer to Figure 11 As part of a self-aligned dual patterning process, after removing a portion of the spacer material 900 from a large to a flat surface to define spacers 1000, 1002, and 1004, a suitable lithography and etching technique is used to remove the remaining portion of the mask material 704. This defines the corresponding lateral position and lateral width (or boundary) of another region of conductive metal material to be fabricated within the corresponding metal interconnect layer, which is physically distinguished from other regions using open areas 802 and 804. In this regard, the remaining portion of the mask material 704 can be removed simultaneously to define other regions of wiring, traces, or metal material within the corresponding interconnect layer on other areas of the semiconductor substrate 600, forming... Figure 11 The depiction shows the appearance of the semiconductor substrate.

[0120] Please refer to Figure 12After the spacers 1000, 1002, and 1004 are formed, the manufacturing process continues by anisotropically etching the hard mask material 702 using the spacers 1000, 1002, and 1004 as etching masks, in order to define the corresponding self-aligned spacer regions 1100, 1102, and 1104 of the hard mask material 702 located below the spacers 1000, 1002, and 1004.

[0121] like Figure 13 As illustrated, after forming the spacer regions 1100, 1102, 1104 of the hard mask material 702, the manufacturing process continues by anisotropically etching the IMD material layer 700 using the hard mask spacers 1100, 1102, 1104 as etching masks, to form empty regions 1202, 1204 within the IMD material layer 700 corresponding to the conductive structures 1404, 1406 of the inductor structure 1400. In this regard, the IMD material layer 700 can be anisotropically etched to a depth greater than or equal to the thickness of the remaining gap material 900 of the spacers 1000, 1002, 1004, to remove the gap material 900 from the upper surface of the hard mask spacers 1100, 1102, 1104 while forming the empty regions 1202, 1204. After forming the empty regions 1202, 1204, the process can be continued as follows: Figure 14 The remaining portion of the hard masking material 702 is removed from the upper surface of the semiconductor substrate 600 using the conventional method shown.

[0122] Please refer to Figure 15 And continue to refer to Figures 13 to 14In some embodiments, the inductor structure 1400 is first formed as part of a Metal-1 layer via a final process stage, wherein the IMD material layer 700 is etched to a depth less than the thickness of the IMD material layer 700, such that portions of the IMD material 700 are vertically held between the bottom surfaces of the empty regions 1202, 1204 and the underlying metal regions 602, 604. For example, in some embodiments, the IMD material 700 is etched to form the empty regions 1202, 1204, which have a depth in the range of about 20 nanometers to about 35 nanometers (and corresponding height or vertical dimension of the conductive structures 1404, 1406). After forming the empty regions 1202, 1204 within the IMD material layer 700 and removing the hard mask spacers 1100, 1102, 1104, the manufacturing process continues by forming corresponding regions 1302, 1304 of the metal material 1300 for the corresponding conductive structures 1404, 1406 of the inductor structure 200 in the empty regions 1202, 1204. For example, before planarizing the upper surface of the semiconductor substrate, a metal material layer 1300 with a thickness greater than or equal to the depth of the empty regions 1202, 1204 (e.g., flush filling or slightly overfilling) can be uniformly deposited on the upper surface of the semiconductor substrate or on the upper surface covering the semiconductor substrate to form Figure 15 The pattern shown.

[0123] Please refer to Figure 16 After the metal material layer 1300 is formed, as part of the Metal-1 layer, the fabrication of the corresponding layer of the inductor structure 1400 can be accomplished by forming conductive vias 1402 in the corresponding regions 1302 and 1304 of the metal material 1300 through the final process stage. The conductive vias 1402 provide electrical connections between the corresponding metal regions 1302 and 1304 of the corresponding conductive structures 1404 and 1406 of the inductor structure 1400 and the underlying metal interconnect regions 602 and 604. In this regard, the conductive vias 1402 can be fabricated through the corresponding metal material layer 1300 by conventional methods not closely related to this disclosure, for example, by patterning and etching the corresponding empty regions within the corresponding metal regions 1302 and 1304, and then forming a conductive via material within the voids (e.g., depositing or otherwise forming a metal material layer on or overlaying the semiconductor substrate) before planarizing the upper surface of the semiconductor substrate, to form a structure such as... Figure 16 The semiconductor substrate shown is a sample.

[0124] Figure 17An exemplary embodiment of manufacturing process 1700 is illustrated, suitable for fabricating a helical conductive structure with reduced pitch dimensions within a metal interconnect layer, as part of one or more BEOL process stages for greater turn density and greater inductance density. Manufacturing process 1700 begins at 1702, as... Figure 17 As shown, an intermetallic dielectric material layer is formed on a semiconductor substrate or overlay semiconductor substrate.

[0125] Manufacturing process 1700 begins with 1704, using the aforementioned self-aligned double patterning process (e.g., Figure 8 to 1704). Figure 12 Spacers are formed to cover the IMD material layer. The spacers define the pitch dimension of the inductor structure and the corresponding lateral width and spacing distance to form a desired lateral spiral geometry, such as any of the spiral configurations depicted in any of Figures 2, 4 and 5.

[0126] In 1706, manufacturing process 1700 continues by forming voids within the IMD layer corresponding to the desired spiral conductive structure, such as... Figure 13 As shown. In step 1708, metal or other suitable conductive material will be formed within the voids in the IMD layer to form a spiral conductive structure, such as... Figure 15 As shown.

[0127] In 1710, manufacturing process 1700 continues by forming conductive vias that provide electrical connections to / from the helical conductive structure of the inductor. For example, such as Figure 16 As shown, in some embodiments, the conductive via 1402 can be formed within a spiral conductive structure and penetrate the IMD material layer 700 to contact the lower regions 602, 604 on the semiconductor substrate. For example, in Figure 1 As described above, each of regions 602 and 604 typically corresponds to a corresponding terminal 101 or 108 of the inductor structure 1400, which can be electrically connected to other electronic circuits 106 or corresponding input or output terminals. For example, in some embodiments, each of regions 602 and 604 can be electrically connected to different circuits, such that the inductor structure 1400 provides series inductance between different circuits.

[0128] In other embodiments, vias may be formed in the capping layer to establish an upper layer electrically connected to the semiconductor substrate. For example, Figure 18An embodiment is illustrated in which, in addition to vias 1802 connecting the helical inductor structure 1400 to or near the outer ends of the helical conductive structures 1404, 1406 in the lower layer regions 602, 604, an additional set of vias 1802 is provided. The vias 1802 are disposed at or near the inner ends of the helical conductive structures 1404, 1406 within a covering metal interconnect layer, the inner ends providing a corresponding region 1800 electrically connected to a metal or other conductive material within the covering metal interconnect layer, which provides the desired electrical connection to the inductor structure 1400.

[0129] Based on the topics described herein, spacers can be used as part of a self-aligned dual patterning process to reduce the lateral spacing between helical conductive structures, thereby increasing the number of turns per unit area and correspondingly increasing the inductance density using helical inductor structures.

[0130] On the other hand, a semiconductor device is provided, comprising a transistor and an inductor structure. The transistor includes a source, a drain, and a gate on a substrate, and an inductor structure on the substrate. The inductor structure includes a first helical conductive structure and a second helical conductive structure adjacent to the first helical conductive structure to provide inductance between the first helical conductive structure and the second helical conductive structure, wherein one of the first helical conductive structure and the second helical conductive structure is electrically connected to at least one of the source, drain, or gate of the transistor.

[0131] In another aspect of the semiconductor element, at least a portion of the second helical structure is laterally interposed between adjacent portions of the first helical conductive structure, the adjacent portions of the first helical conductive structure being substantially parallel to portions of the second helical conductive structure.

[0132] On another aspect of the semiconductor element, the first helical conductive structure and the second helical conductive structure have an alternating configuration.

[0133] On the other hand, the first spiral conductive structure and the second spiral conductive structure are centered on a common point.

[0134] On the other hand, the inner ends of the first spiral conductive structure and the inner ends of the second spiral conductive structure are symmetrically distributed in opposite directions at a common point.

[0135] In another aspect of the semiconductor element, the inner ends of the first spiral conductive structure and the inner ends of the second spiral conductive structure are coaxially arranged along an axis that passes through a common point that intersects with the inner ends of both the first and second spiral conductive structures.

[0136] On another aspect of the semiconductor device, the inductor structure comprises a multilayer structure fabricated from a first metal interconnect layer and a second metal interconnect layer.

[0137] On another side of the semiconductor device, the first metal interconnect layer includes a first helical conductive structure of the first metal material of the first metal interconnect layer and a second helical conductive structure of the first metal material of the first metal interconnect layer, wherein the first intermetallic dielectric material of the first metal interconnect layer is separated by a lateral distance.

[0138] On another side of the semiconductor device, the second metal interconnect layer includes a third helical conductive structure of the second metal material of the second metal interconnect layer and a fourth helical conductive structure of the second metal material of the second metal interconnect layer, wherein the second intermetallic dielectric material of the second metal interconnect layer is separated by a second lateral distance, wherein the third helical conductive structure is electrically connected to the first helical conductive structure, and the fourth helical conductive structure is electrically connected to the second helical conductive structure.

[0139] On another aspect of the semiconductor device, the first geometry of the first helical conductive structure differs from the third geometry of the third helical conductive structure.

[0140] On another aspect of the semiconductor element, at least a portion of the first helical conductive structure is symmetrical to the second helical conductive structure.

[0141] In another aspect, a manufacturing method is provided. The manufacturing method includes forming a transistor comprising a source, a drain, and a gate on a substrate; forming an interconnect layer on the substrate, the interconnect layer being configured as the source, the drain, and the gate providing electrical connection; the interconnect layer comprising a region of metal material disposed within a dielectric material layer; wherein the interconnect layer includes an inductor structure comprising a first helical region of metal material and a second helical region of metal material adjacent to the first helical region to provide inductance between the first helical region and the second helical region; and forming a plurality of vias within the interconnect layer on the substrate, wherein a first via of the plurality of vias electrically connects the first helical region to a first region on the substrate below the first via, and a second via of the plurality of vias electrically connects the second helical region to a second region on the substrate below the second via.

[0142] In another aspect of the manufacturing method, at least one of the first region and the second region is configured to provide an electrical connection with at least one of the source, drain and gate of the transistor.

[0143] In another aspect of the manufacturing method, an interconnect layer is formed, comprising forming a dielectric material layer on a substrate, forming one or more spacers covering the dielectric material layer to define a first spiral void region and a second spiral void region in the dielectric material layer, etching the dielectric material layer using the one or more spacers to form the first spiral void region and the second spiral void region in the dielectric material layer, and forming a first spiral region and a second spiral region of metallic material in the first spiral void region and the second spiral void region in the dielectric material layer.

[0144] In another aspect of the manufacturing method, one or more spacers are formed, comprising forming a spacer material layer having a thickness corresponding to the lateral distance associated with the insertion portion of the dielectric material layer between a first spiral region and a second spiral region of the metallic material.

[0145] In another aspect of the manufacturing method, an interconnect layer is formed, which includes at least a portion forming a second spiral region, the second spiral region being arranged substantially parallel to adjacent portions of the first spiral region, wherein a corresponding intervening portion of the dielectric material layer is inserted between a portion of the second spiral region and a corresponding adjacent portion of the first spiral region.

[0146] In another aspect of the manufacturing method, an interconnect layer is formed, which includes a first spiral region and a second spiral region that are concentric with a common point as the center.

[0147] On the other hand, the semiconductor inductor structure includes a first helical structure of conductive material within an interconnect layer, comprising conductive material disposed within a dielectric material layer covering a semiconductor substrate, and a second helical structure of conductive material within an interconnect layer covering the semiconductor substrate, wherein a portion of the second helical structure is arranged substantially parallel to an adjacent portion of the first helical structure, and one or more intervening portions of the dielectric material layer are disposed between a portion of the second helical structure and a corresponding adjacent portion of the first helical structure, a first via within an interconnect layer between the first helical structure and a first conductive region on the semiconductor substrate, and a second via within an interconnect layer between the second helical structure and a second conductive region on the semiconductor substrate.

[0148] On the other hand, the semiconductor inductor structure further includes a second interconnect layer covering the interconnect layer, wherein the second interconnect layer includes a third via covering the first inner end of the first helical structure, a fourth via covering the second inner end of the second helical structure, and a conductive material located between the third and fourth vias in the interconnect layer to provide an electrical connection between the first and second helical structures in the second interconnect layer.

[0149] On the other hand, the semiconductor inductor structure further includes a second interconnect layer covering the interconnect layer, wherein the second interconnect layer includes a third helical structure of conductive material within the second interconnect layer, a fourth helical structure of conductive material within the second interconnect layer, a third via in the second interconnect layer between the first helical structure and the third helical structure, and a fourth via in the second interconnect layer between the second helical structure and the fourth helical structure.

[0150] On the other hand, the lateral geometry of the third spiral structure is different from that of the first spiral structure, and the lateral geometry of the fourth spiral structure is different from that of the second spiral structure.

[0151] On the other hand, the third helical structure shares a common transverse geometry with the first helical structure, while the fourth helical structure shares a common transverse geometry with the second helical structure.

[0152] In another aspect of the semiconductor inductor structure, the inner ends of the first spiral structure and the inner ends of the second spiral structure are symmetrically distributed in opposite directions at a common point.

[0153] In another aspect of the semiconductor inductor structure, at least a portion of the first helical structure is symmetrical to the second helical structure in an alternating configuration and is spaced apart by one or more intervening portions of the dielectric material layer.

[0154] On the other hand, a semiconductor element is provided, comprising: a transistor including a source, a drain, and a gate on a substrate; and an inductor structure located on the substrate, the inductor structure including a first helical conductive structure and a second helical conductive structure adjacent to the first helical conductive structure to provide inductance between the first helical conductive structure and the second helical conductive structure, wherein one of the first helical conductive structure and the second helical conductive structure is electrically connected to at least one of the source, drain, and gate of the transistor, wherein at least a portion of the second helical conductive structure is laterally inserted between adjacent portions of the first helical conductive structure, the adjacent portions of the first helical conductive structure are arranged substantially parallel to portions of the second helical conductive structure, and wherein the first helical conductive structure and the second helical conductive structure are staggered.

[0155] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, Include: A transistor includes a source, a drain, and a gate on a substrate; and An inductor structure is located on the substrate. The inductor structure includes a first helical conductive structure and a second helical conductive structure adjacent to the first helical conductive structure to provide an inductance between the first helical conductive structure and the second helical conductive structure. One of the first helical conductive structure and the second helical conductive structure is electrically connected to at least one of the source, drain and gate of the transistor. At least a portion of the second helical conductive structure is laterally inserted between adjacent portions of the first helical conductive structure, and the adjacent portions of the first helical conductive structure are arranged substantially parallel to the portion of the second helical conductive structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The first spiral conductive structure and the second spiral conductive structure are concentric with a common point as the center.

3. The semiconductor device as described in claim 2, characterized in that, The inner ends of the first spiral conductive structure and the inner ends of the second spiral conductive structure are symmetrically distributed in the opposite direction of the common point.

4. The semiconductor device as claimed in claim 1, characterized in that, The inductor structure comprises a multilayer structure fabricated in a first metal interconnect layer and a second metal interconnect layer.

5. The semiconductor device as claimed in claim 4, characterized in that, in: The first metal interconnect layer includes a first spiral conductive structure composed of a first metal material of the first metal interconnect layer and a second spiral conductive structure composed of the first metal material of the first metal interconnect layer, wherein the first spiral conductive structure and the second spiral conductive structure are separated by a lateral distance by a first intermetallic dielectric material of the first metal interconnect layer; The second metal interconnect layer comprises a third helical conductive structure composed of a second metal material of the second metal interconnect layer and a fourth helical conductive structure composed of the second metal material of the second metal interconnect layer. The third helical conductive structure and the fourth helical conductive structure are separated by a second intermetallic dielectric material of the second metal interconnect layer by a second lateral distance. The third helical conductive structure is electrically connected to the first helical conductive structure, and the fourth helical conductive structure is electrically connected to the second helical conductive structure. as well as The first geometry of the first helical conductive structure is different from the third geometry of the third helical conductive structure.

6. A semiconductor inductor structure, characterized in that, Include: A first helical structure composed of a conductive material is located in an interconnect layer above a semiconductor substrate, the interconnect layer containing the conductive material, and the conductive material is disposed in a dielectric material layer; A second helical structure composed of the conductive material is located in the interconnect layer above the semiconductor substrate, wherein a portion of the second helical structure is arranged substantially parallel to the adjacent portion of the first helical structure; One or more insertion portions of the dielectric material layer are disposed between the portion of the second spiral structure and a corresponding adjacent portion of the first spiral structure; A first via in the interconnect layer is located between the first spiral structure and a first conductive region on the semiconductor substrate; as well as A second via in the interconnect layer is located between the second spiral structure and a second conductive region on the semiconductor substrate.

7. The semiconductor inductor structure as described in claim 6, characterized in that, It further includes a second interconnect layer overlying the interconnect layer, wherein the second interconnect layer comprises: The second interconnect layer contains a third helical structure composed of the conductive material; The second interconnect layer contains a fourth helical structure composed of the conductive material; A third via within the second interconnect layer between the first helical structure and the third helical structure; and A fourth via within the second interconnect layer between the second helical structure and the fourth helical structure.

8. The semiconductor inductor structure as described in claim 7, characterized in that, The transverse geometry of the third spiral structure is different from that of the first spiral structure.

9. The semiconductor inductor structure as described in claim 7, characterized in that, The third spiral structure shares a common transverse geometry with the first spiral structure.

10. A semiconductor element, characterized in that, Include: A transistor includes a source, a drain, and a gate on a substrate; and An inductor structure is located on the substrate. The inductor structure includes a first helical conductive structure and a second helical conductive structure adjacent to the first helical conductive structure to provide an inductance between the first helical conductive structure and the second helical conductive structure. One of the first helical conductive structure and the second helical conductive structure is electrically connected to at least one of the source, drain and gate of the transistor. At least a portion of the second helical conductive structure is laterally inserted between adjacent portions of the first helical conductive structure. The adjacent portions of the first helical conductive structure are arranged substantially parallel to the portion of the second helical conductive structure, and the first helical conductive structure and the second helical conductive structure have an interleaved configuration.

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