Chip plating structure, power module, motor controller, electric control assembly and vehicle

Abstract

The chip plating structure provided by the embodiment of the present application comprises a connecting layer, wherein the connecting layer is provided with a bonding force enhancing part, and the bonding force enhancing part comprises a plurality of grooves. In this way, when the chip plating structure and the packaging layer are subjected to a packaging process, the surface roughness of the connecting layer can be increased through the bonding force enhancing part on the connecting layer, so as to enhance the bonding force between the connecting layer and the packaging layer, make the connection between the connecting layer and the packaging layer more reliable, reduce the risk that the connecting layer is prone to delamination from the packaging layer in the packaging process, and improve the reliability and stability of the chip structure.

Description

Technical Field

[0001] This application belongs to the field of electronic device technology, specifically relating to a chip plating structure, a power module, a motor controller, an electronic control assembly, and a vehicle. Background Technology

[0002] The vehicle's electronic control assembly typically includes a power module, and the chip within the power module is its main structure. The chip's plating structure and encapsulation layer have a significant impact on the chip's reliability.

[0003] In the prior art, the chip coating structure includes a bonding layer and a passivation layer connected to the substrate layer. However, the surface roughness of the bonding layer is usually low, which affects the bonding force between the bonding layer and the packaging layer and easily causes delamination during the packaging process, affecting the reliability of the chip structure. Utility Model Content

[0004] In view of the above problems, this utility model is proposed to provide a chip plating structure, power module, motor controller, electronic control assembly and vehicle that overcomes or at least partially solves the above problems.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows:

[0006] In a first aspect, embodiments of this application propose a chip plating structure, the chip plating structure comprising: a bonding layer;

[0007] The connecting layer is provided with a bonding strength enhancement section;

[0008] The bonding strength enhancement portion includes at least one groove.

[0009] Optionally, there may be multiple grooves, which are spaced apart on the surface of the connecting layer.

[0010] Optionally, at least some of the grooves are distributed in an array on the surface of the connecting layer.

[0011] Optionally, the groove is elongated and extends along the width direction of the connecting layer, and multiple grooves are spaced apart along the length direction of the connecting layer.

[0012] Optionally, the length of the groove is any value between 5 and 200 μm;

[0013] And / or, the width of the groove is any value between 5 and 200 μm;

[0014] And / or, the depth of the groove is any value between 0 and 20 μm;

[0015] Optionally, the number of grooves is multiple, and the spacing between two adjacent grooves is any value between 5 and 200 μm.

[0016] Optionally, the chip plating structure includes a passivation layer, which is connected to the connection layer;

[0017] The bottom of the passivation layer is flush with the bottom of the connecting layer, and the height of the connecting layer is less than the height of the passivation layer.

[0018] Optionally, the chip plating structure includes a substrate layer, and the interconnect layer and the passivation layer are respectively connected to the upper surface of the substrate layer.

[0019] Secondly, embodiments of this application propose a power module, which includes the chip plating structure.

[0020] Thirdly, embodiments of this application propose a motor controller, which includes the power module or the chip plating structure.

[0021] Fourthly, embodiments of this application propose an electronic control assembly, which includes the motor controller, or the power module, or the chip plating structure.

[0022] Fifthly, embodiments of this application propose a vehicle, the vehicle including the electronic control assembly, or the motor controller, or the power module, or the chip plating structure.

[0023] In this embodiment, the chip plating structure includes: a bonding layer; the bonding layer has an adhesion enhancement portion; the adhesion enhancement portion includes multiple grooves. Thus, during the packaging process between the chip plating structure and the packaging layer, the adhesion enhancement portion on the bonding layer increases the surface roughness of the bonding layer, thereby enhancing the adhesion between the bonding layer and the packaging layer. This results in a more reliable connection between the bonding layer and the packaging layer, reducing the risk of delamination between the bonding layer and the packaging layer during the packaging process, and improving the reliability and stability of the chip structure.

[0024] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0026] Figure 1 This is a schematic diagram of a chip plating structure according to an embodiment of this application;

[0027] Figure 2 This is another schematic diagram of a chip plating structure described in the embodiments of this application.

[0028] Reference numerals: 10-Connecting layer; 11-Groove; 20-Passivation layer; 30-Substrate layer. Detailed Implementation

[0029] The embodiments of this utility model will now be described in detail. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0030] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0031] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0032] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0033] Reference Figures 1 to 2 The diagram shows a schematic of a chip plating structure according to an embodiment of this application. The chip plating structure is used to connect the packaging layer. The chip plating structure may specifically include: a connecting layer 10; the connecting layer 10 is provided with a bonding force enhancement portion; the bonding force enhancement portion includes at least one groove 11.

[0034] In this embodiment, during the encapsulation process of the chip plating structure and the encapsulation layer, the surface roughness of the connecting layer 10 can be increased by forming a bonding force enhancement portion through at least one groove 11 on the connecting layer 10, and the contact area between the connecting layer 10 and the encapsulation layer can be increased, thereby enhancing the bonding force between the connecting layer 10 and the encapsulation layer. This makes the connection between the connecting layer 10 and the encapsulation layer more reliable, reducing the risk that the thermal stress generated under heating during the encapsulation process is greater than the bonding force between the connecting layer 10 and the encapsulation layer, which could easily lead to delamination between the connecting layer 10 and the encapsulation layer. It also reduces the risk of moisture penetration caused by delamination affecting the electrical performance of the chip, thereby improving the reliability and stability of the chip structure.

[0035] For example, in this embodiment, the connection layer 10 of the chip plating structure can be a copper layer, which serves as the metal pads on the chip surface for connecting external circuits and the chip's internal circuits. The encapsulation layer is used to encapsulate the chip plating structure. For example, the encapsulation layer can be a resin material, and the bonding force between the copper and resin is enhanced by providing a groove structure on the connection layer 10 of the copper layer. Furthermore, the material of the encapsulation layer can also be epoxy resin, polyurethane resin, polyimide resin, polycarbonate resin, polystyrene resin, silicone resin, or polypropylene resin, etc. This embodiment does not limit the specific material of the encapsulation layer.

[0036] In this embodiment, for example, a mask etching process can be used to etch multiple grooves 11 on the surface of the bonding layer 10 to form a bonding reinforcement portion. Alternatively, laser processing or chemical etching can be used to fabricate the multiple groove 11 structure on the bonding layer 10. This embodiment does not limit the specific method of forming the multiple grooves 11.

[0037] For example, in the embodiments of this application, the number of grooves 11 can be one or more, such as ten, twenty or fifty, etc., which can be set according to actual needs based on the size of the connecting layer 10 and the bonding force requirements. The specific number of grooves 11 set in the embodiments of this application is not limited.

[0038] Optionally, in this embodiment, there are multiple grooves 11, which are spaced apart on the surface of the connecting layer 10. Specifically, the grooves 11 are disposed on the upper surface of the connecting layer 10, which is the side of the connecting layer 10 facing away from the substrate layer 30. The upper surface of the connecting layer 10 is used to connect with the encapsulation layer. The structure of multiple spaced grooves 11 enhances the roughness of the upper surface of the connecting layer 10, facilitating the bonding between the upper surface of the connecting layer 10 and the encapsulation layer to achieve encapsulation.

[0039] In this embodiment, optionally, at least some of the grooves 11 are arrayed on the surface of the interconnect layer 10. Specifically, the grooves 11 are disposed on the upper surface of the interconnect layer 10, so that multiple grooves 11 are dot-distributed on the surface of the interconnect layer 10, making the multiple grooves 11 arranged relatively closely, which can make maximum use of the space on the upper surface of the interconnect layer 10, optimize the layout of the entire bonding force enhancement part, make it more compact and efficient, and make the stress distribution of the interconnect layer 10 more uniform, thereby improving the stability and reliability of the overall chip structure.

[0040] In this embodiment of the application, for example, some grooves 11 can be arranged in an array on the surface of the connecting layer 10, or all grooves 11 can be arranged in an array on the surface of the connecting layer 10. The arrangement can be set according to actual needs. This embodiment of the application does not limit the specific distribution of multiple grooves 11.

[0041] For example, in this embodiment, a plurality of grooves 11 are spaced apart along the width direction of the connecting layer 10, and also spaced apart along the length direction of the connecting layer 10. The spacing between two adjacent grooves 11 along the width direction can be the same as or different from the spacing between two adjacent grooves 11 along the length direction; the number of grooves in this application is not limited in this respect. Furthermore, the plurality of grooves 11 can be evenly distributed, symmetrically distributed, or distributed in a radiating pattern, etc.; the specific distribution method of the plurality of grooves 11 in this embodiment is not limited.

[0042] In this embodiment, the shape of the groove 11 may include at least one of a rectangle, a circle, an ellipse, or a trapezoid. For example, multiple grooves 11 may all be rectangular, circular, elliptical, or trapezoidal. Furthermore, some of the grooves 11 may be rectangular, some may be circular, some may be elliptical, some may be trapezoidal, etc., and any combination is possible. This embodiment does not limit the specific shape of the groove 11.

[0043] Optionally, in this embodiment, the groove 11 is elongated, extending along the width direction of the connecting layer 10, and multiple grooves 11 are spaced apart along the length direction of the connecting layer 10. This forms multiple elongated grooves 11 extending along the width direction on the surface of the connecting layer 10, further increasing the contact area between the connecting layer 10 and the encapsulation layer, improving the encapsulation bonding force, simplifying the processing method, and improving processing efficiency. Furthermore, the grooves 11 can also extend along the length direction of the connecting layer 10, with multiple grooves 11 spaced apart along the width direction of the connecting layer 10. The specific extension direction of the elongated grooves 11 is not limited in this embodiment.

[0044] In this embodiment, optionally, the length of the groove 11 is any value from 5 to 200 μm; and / or, the width of the groove 11 is any value from 5 to 200 μm; and / or, the depth of the groove 11 is any value from 0 to 20 μm. This ensures that the groove 11 has a suitable length, avoiding a short groove 11 which would result in a small contact area for the bonding reinforcement portion, affecting the encapsulation effect between the bonding reinforcement portion and the encapsulation layer. For example, the length of the groove 11 can be 5 μm, 50 μm, 100 μm, or 200 μm, etc., and the lengths of the various grooves 11 can be the same or different. This embodiment does not limit the specific setting of the length of the groove 11. Furthermore, the groove 11 has a suitable width, avoiding a shallow groove 11 which would result in a small contact area for the bonding reinforcement portion, affecting the encapsulation effect between the bonding reinforcement portion and the encapsulation layer. For example, the width of the groove 11 can be 5μm, 50μm, 100μm, or 200μm, etc. The width of each groove 11 can be the same or different. The specific setting method of the width of the groove 11 in this embodiment is not limited. Furthermore, the groove 11 is designed to have a suitable depth to avoid a short groove depth resulting in a small contact area for the bonding reinforcement portion, which would affect the encapsulation effect between the bonding reinforcement portion and the encapsulation layer. For example, the depth of the groove 11 can be 1μm, 5μm, 15μm, or 20μm, etc. The depth of each groove 11 can be the same or different. The specific setting method of the depth of the groove 11 in this embodiment is not limited.

[0045] Optionally, in this embodiment, the number of grooves 11 is multiple, and the spacing between two adjacent grooves 11 is any value between 5 and 200 μm. This provides a suitable spacing between adjacent grooves 11, thereby optimizing stress distribution, reducing stress concentration points, improving the bonding strength between the connecting layer 10 and the encapsulation layer, effectively reducing localized damage to the connecting layer 10 caused by stress concentration, and enhancing the rigidity and structural stability of the connecting layer 10. For example, the spacing between two adjacent grooves 11 can be 5 μm, 50 μm, 100 μm, or 200 μm, etc. The spacing between any two sets of adjacent grooves 11 can be the same or different. This embodiment does not limit the specific arrangement of two adjacent grooves 11.

[0046] Optionally, in this embodiment, the chip plating structure includes a passivation layer 20 connected to the connection layer 10; the bottom of the passivation layer 20 is flush with the bottom of the connection layer 10, and the height of the connection layer 10 is less than the height of the passivation layer 20. In related technologies, the height of the connection layer 10 is usually equal to or greater than the height of the passivation layer 20. In the packaging process of the chip plating structure, the edge of the connection layer 10 is prone to overhang, that is, part of the structure at the edge of the connection layer 10 tends to protrude from the passivation layer 20 and be exposed to the upper surface of the passivation layer 20. The gap that is easily formed between the protruding part of the connection layer 10 and the passivation layer 20 makes it difficult for the material of the packaging layer to fill the gap, which affects the packaging effect of the chip structure and even the electrical performance of the chip structure. In this embodiment, the height of the connecting layer 10 is set to be less than the height of the passivation layer 20, thereby greatly reducing the risk of overhang at the edge of the connecting layer 10 during the encapsulation process. This also reduces the risk of the resin material of the encapsulation layer filling voids and further causing thermal stress concentration, which could lead to reliability failure. As a result, the encapsulation layer can completely cover the connecting layer 10 and the passivation layer 20, resulting in a better encapsulation effect.

[0047] In this embodiment, optionally, the height of the interconnect layer 10 is any value between 8 and 20 μm. This gives the interconnect layer 10 a suitable height, resulting in lower resistance and less energy loss in the internal circuitry of the chip structure during operation. It also allows the chip to carry a larger current and has relatively stable conductivity, ensuring good signal integrity during signal transmission and minimizing distortion in analog signal amplification and filtering processes. For example, the height of the interconnect layer 10 can be 8 μm, 10 μm, 15 μm, or 20 μm, etc., and can be set according to actual needs. This embodiment does not limit the specific height value of the interconnect layer 10. And / or, the height of the passivation layer 20 is any value between 8 and 20 μm. This gives the passivation layer 20 a suitable height, resulting in good mechanical strength and toughness, providing sufficient protection for the internal structure of the chip. It prevents the chip structure from being subjected to external mechanical impacts or scratches during packaging, testing, and use, and effectively prevents corrosion of the chip surface by moisture, acids, alkalis, and other chemicals, extending the chip's lifespan. Furthermore, it effectively isolates oxygen, preventing oxidation and resulting in low resistance and good electrical and electrical insulation properties in the chip. For example, the height of the passivation layer 20 can be 8μm, 10μm, 15μm, or 20μm, etc., and can be set according to actual needs. The height of the connection layer 10 can be set to be less than the height of the passivation layer 20. In this embodiment, the specific height value of the passivation layer 20 is not limited.

[0048] For example, in the embodiments of this application, the material of the passivation layer 20 can be PI (Polyimide). In addition, the passivation layer 20 can also be made of other materials, such as PBO (Polybenzoxazole) or BCB (Benzocyclobutene), etc. The specific material of the passivation layer 20 is not limited in the embodiments of this application.

[0049] Optionally, in this embodiment, the chip plating structure includes a substrate layer 30, a connection layer 10, and a passivation layer 20, respectively connected to the surface of the substrate layer 30. Specifically, the upper surface of the substrate layer 30 is the side of the substrate layer 30 closest to the connection layer 10 and the passivation layer 20. In this way, the substrate layer 30 provides structural support and positioning for the connection layer 10 and the passivation layer 20, resulting in better connection stability and reliability for the connection layer 10 and the passivation layer 20. For example, the substrate layer 30 can be an aluminum layer, used as a metal pad on the chip surface for connecting external circuits and the chip's internal circuits.

[0050] In summary, the chip plating structure described in the embodiments of this application can include at least the following advantages:

[0051] In this embodiment, the chip plating structure includes: a bonding layer; the bonding layer has an adhesion enhancement portion; the adhesion enhancement portion includes multiple grooves. Thus, during the packaging process between the chip plating structure and the packaging layer, the adhesion enhancement portion on the bonding layer increases the surface roughness of the bonding layer, thereby enhancing the adhesion between the bonding layer and the packaging layer. This results in a more reliable connection between the bonding layer and the packaging layer, reducing the risk of delamination between the bonding layer and the packaging layer during the packaging process, and improving the reliability and stability of the chip structure.

[0052] This application also proposes a power module, which includes the chip plating structure.

[0053] The power module described in this application embodiment may include at least the following advantages:

[0054] In this embodiment, the power module includes the chip plating structure, which includes an interconnect layer; the interconnect layer has an adhesion enhancement portion; and the adhesion enhancement portion includes multiple grooves. Thus, during the packaging process between the chip plating structure and the packaging layer, the adhesion enhancement portion on the interconnect layer increases the surface roughness of the interconnect layer, thereby enhancing the adhesion between the interconnect layer and the packaging layer. This results in a more reliable connection between the interconnect layer and the packaging layer, reducing the risk of delamination between the interconnect layer and the packaging layer during the packaging process, and improving the reliability and stability of the chip structure.

[0055] This application also proposes a motor controller, which includes the power module or the chip plating structure.

[0056] The motor controller described in this application embodiment may include at least the following advantages:

[0057] In this embodiment, the motor controller includes the power module, or the chip plating structure, wherein the power module includes the chip plating structure, and the chip plating structure includes: a connection layer; the connection layer is provided with an adhesion enhancement portion; the adhesion enhancement portion includes multiple grooves. Thus, during the packaging process between the chip plating structure and the packaging layer, the surface roughness of the connection layer can be increased by the adhesion enhancement portion on the connection layer, thereby enhancing the adhesion between the connection layer and the packaging layer. This makes the connection between the connection layer and the packaging layer more reliable, reducing the risk of delamination between the connection layer and the packaging layer during the packaging process, and improving the reliability and stability of the chip structure.

[0058] This application provides an electronic control assembly, which includes the motor controller, or the power module, or the chip plating structure.

[0059] The electronic control assembly described in this application embodiment may include at least the following advantages:

[0060] In this embodiment, the electronic control assembly includes the motor controller, or the power module, or the chip plating structure. The motor controller includes the power module, or the chip plating structure includes the chip plating structure. The chip plating structure includes a bonding layer; the bonding layer has an adhesion enhancement portion; the adhesion enhancement portion includes multiple grooves. Thus, during the packaging process between the chip plating structure and the packaging layer, the surface roughness of the bonding layer can be increased by the adhesion enhancement portion on the bonding layer, thereby enhancing the adhesion between the bonding layer and the packaging layer. This makes the connection between the bonding layer and the packaging layer more reliable, reducing the risk of delamination between the bonding layer and the packaging layer during the packaging process, and improving the reliability and stability of the chip structure.

[0061] This application provides a vehicle that includes the electronic control assembly, or the motor controller, or the power module, or the chip plating structure.

[0062] For example, in the embodiments of this application, the vehicle may include pure electric vehicles, hybrid vehicles, range-extended vehicles, fuel vehicles, etc. The type of vehicle may also include small cars, medium-sized cars, sedans, trucks, trailers, CDVs (Car Derived Vans), MPVs (multi-Purpose Vehicles), SUVs (Sport Utility Vehicles), etc. The specific type of vehicle is not limited in the embodiments of this application.

[0063] The vehicle described in this application embodiment may include at least the following advantages:

[0064] In this embodiment, the vehicle includes the electronic control assembly, or the motor controller, or the power module, or the chip plating structure. The electronic control assembly includes the motor controller, or the power module, or the chip plating structure. The motor controller includes the power module, or the chip plating structure. The power module includes the chip plating structure. The chip plating structure includes a bonding layer; the bonding layer has an adhesion enhancement portion; the adhesion enhancement portion includes multiple grooves. Thus, during the packaging process between the chip plating structure and the packaging layer, the surface roughness of the bonding layer can be increased by the adhesion enhancement portion on the bonding layer, thereby enhancing the adhesion between the bonding layer and the packaging layer. This makes the connection between the bonding layer and the packaging layer more reliable, reducing the risk of delamination between the bonding layer and the packaging layer during the packaging process, and improving the reliability and stability of the chip structure.

[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0066] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip plating structure, characterized in that, The chip plating structure includes: a connection layer (10); The connecting layer (10) is provided with a bonding strength enhancement part; The bonding strength enhancement part includes at least one groove (11). The chip plating structure includes a passivation layer (20), which is connected to the connection layer (10); the height of the connection layer (10) is less than the height of the passivation layer (20).

2. The chip plating structure according to claim 1, characterized in that, The number of grooves (11) is multiple, and the multiple grooves (11) are spaced apart on the surface of the connecting layer (10).

3. The chip plating structure according to claim 2, characterized in that, At least some of the grooves (11) are distributed in an array on the surface of the connecting layer (10).

4. The chip plating structure according to any one of claims 1-3, characterized in that, The groove (11) is elongated and extends along the width direction of the connecting layer (10). Multiple grooves (11) are spaced apart along the length direction of the connecting layer (10).

5. The chip plating structure according to any one of claims 1-4, characterized in that, The length of the groove (11) is any value between 5 and 200 μm; And / or, the width of the groove (11) is any value between 5 and 200 μm; And / or, the depth of the groove (11) is any value between 0 and 20 μm.

6. The chip plating structure according to any one of claims 1-5, characterized in that, The number of grooves (11) is multiple, and the distance between two adjacent grooves (11) is any value between 5 and 200 μm.

7. The chip plating structure according to any one of claims 1-6, characterized in that, The bottom of the passivation layer (20) is flush with the bottom of the connecting layer (10).

8. The chip plating structure according to claim 7, characterized in that, The chip plating structure includes a substrate layer (30), and the connecting layer (10) and the passivation layer (20) are respectively connected to the surface of the substrate layer (30).

9. A power module, characterized in that, The power module includes the chip plating structure as described in any one of claims 1-8.

10. A motor controller, characterized in that, The motor controller includes the power module of claim 9, or the chip plating structure of any one of claims 1-8.

11. An electronic control assembly, characterized in that, The electronic control assembly includes the motor controller of claim 10, or the power module of claim 9, or the chip plating structure of any one of claims 1-8.

12. A vehicle, characterized in that, The vehicle includes the electronic control assembly of claim 11, or the motor controller of claim 10, or the power module of claim 9, or the chip plating structure of any one of claims 1-8.

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