A semiconductor structure

Abstract

The utility model discloses a kind of semiconductor structures, belong to semiconductor field, the semiconductor structure at least includes: bearing wafer;Device wafer is set on the bearing wafer, and the device wafer includes oppositely arranged first surface and second surface, side wall and first corner, the second surface and the surface bonding of bearing wafer, the side wall is around and is set between the first surface and the second surface, the first corner connects the side wall and the first surface;Oxidation layer, at least cover the first corner.By the semiconductor structure provided in the utility model, wafer corner can be protected from being excessively ground, improve the flatness of wafer, to improve the quality of process technology and product yield.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor technology, and specifically relates to a semiconductor structure. Background Technology

[0002] In the fabrication of device wafers, after the device layer is fabricated on the substrate, the substrate needs to be thinned. This process not only ensures the wafer thickness meets subsequent packaging requirements but also optimizes the wafer's optical performance. After thinning, the flatness of the substrate layer is crucial, significantly impacting the quality of processes such as photolithography and etching, and ultimately determining product yield. However, during substrate thinning, the grinding rate at substrate corners is faster than at the center, easily leading to over-grinding of the corners. This creates height differences on the substrate surface, compromising the flatness of the substrate and consequently affecting the quality of subsequent processes. Utility Model Content

[0003] The purpose of this invention is to provide a semiconductor structure that can protect the wafer corners from excessive grinding, improve the flatness of the wafer, and thus improve the quality of the manufacturing process and the product yield.

[0004] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0005] This utility model provides a semiconductor structure, including:

[0006] Carrying wafer;

[0007] A device wafer is disposed on the carrier wafer, and the device wafer includes a first surface and a second surface disposed opposite to each other, a sidewall and a first corner, the second surface is bonded to the surface of the carrier wafer, the sidewall is disposed around the first surface and the second surface, and the first corner connects the sidewall and the first surface;

[0008] An oxide layer, at least covering the first corner.

[0009] In one embodiment of the present invention, the oxide layer includes at least a first oxide layer, which covers the first corner.

[0010] In one embodiment of the present invention, the oxide layer further includes a second oxide layer, which covers the sidewall.

[0011] In one embodiment of the present invention, the oxide layer further includes a third oxide layer, which covers the exposed surface of the carrier wafer.

[0012] In one embodiment of the present invention, the first oxide layer, the second oxide layer and the third oxide layer are disposed consecutively.

[0013] In one embodiment of this utility model, the thickness of the first oxide layer is greater than the thickness of the third oxide layer.

[0014] In one embodiment of the present invention, the thickness of the second oxide layer is reduced in the direction from the first surface to the second surface.

[0015] In one embodiment of this utility model, the thickness of the first oxide layer is The thickness of the second oxide layer is The thickness of the third oxide layer is

[0016] In one embodiment of the present invention, the sidewall is perpendicular to the first surface and the second surface.

[0017] In one embodiment of this utility model, the size of the carrier wafer is larger than the size of the device wafer.

[0018] In summary, this utility model provides a semiconductor structure. By improving the semiconductor structure, the unexpected technical effect of this application is that it can protect the corners of the wafer from excessive grinding, improve the flatness of the wafer, thereby improving the quality of the semiconductor manufacturing process and increasing product yield. Moreover, the semiconductor structure provided by this utility model can reduce defects at the corners of the device wafer and protect the quality of the device wafer. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a wafer that carries a device wafer.

[0021] Figure 2 This is a schematic diagram of the oxide layer.

[0022] Figure 3 This is a schematic diagram of a semiconductor structure.

[0023] Figure 4 This is a schematic diagram of etching a semiconductor structure.

[0024] Figure 5 This is a schematic diagram of the first planarization of the semiconductor structure.

[0025] Figure 6 This is a schematic diagram of the second planarization of the semiconductor structure.

[0026] Label Explanation:

[0027] 100, carrier wafer; 200, device wafer; 201, first surface; 202, second surface; 203, sidewall; 204, first corner; 205, second corner; 300, oxide layer; 301, first oxide layer; 302, second oxide layer; 303, third oxide layer; 304, fourth oxide layer. Detailed Implementation

[0028] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0029] It should be understood that this invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this invention to those skilled in the art.

[0030] The technical solution of this utility model will be further described in detail below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0031] Please see Figures 2 to 3As shown, this utility model provides a semiconductor structure, including, for example, a carrier wafer 100, a device wafer 200, and an oxide layer 300. The device wafer 200 is placed on the carrier wafer 100 and includes a first surface 201 and a second surface 202, a sidewall 203, and a first corner 204, all disposed opposite to each other. The second surface 202 is surface-bonded to the carrier wafer 100. The sidewall 203 is disposed around the first surface 201 and the second surface 202. The first corner 204 connects the sidewall 203 and the first surface 201. The oxide layer 300 at least covers the first corner 204. In the semiconductor structure provided by this utility model, by providing the oxide layer 300 to protect the first corner 204, the first corner 204 can be protected from excessive grinding during the planarization of the device wafer 200, improving the flatness of the device wafer 200 surface. This, in turn, improves the quality of subsequent semiconductor manufacturing processes performed on the device wafer 200 surface, and increases product yield.

[0032] Please see Figure 1 As shown, in one embodiment of this utility model, the carrier wafer 100 can be silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, or other III / V compound semiconductors, etc., and can also be a stacked structure composed of these semiconductors, or silicon on insulator, silicon on insulator, silicon germanium on insulator, and germanium on insulator, etc.

[0033] Please see Figure 1As shown, in one embodiment of this invention, a device wafer 200 is disposed on a carrier wafer 100. The size of the device wafer 200 is, for example, smaller than the size of the carrier wafer 100. The device wafer 200 and the carrier wafer 100 are disposed together, for example, by bonding methods such as direct bonding, chemical bonding, or physical bonding, so that the carrier wafer 100 can provide sufficient physical support for the device wafer 200 and prevent the device wafer 200 from cracking. Specifically, the device wafer 200 may include a substrate layer (not shown) and a device layer (not shown), etc., with the device layer disposed on the substrate layer and, for example, bonded to the carrier wafer 100. The substrate layer can be any material suitable for forming semiconductor devices, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials. It also includes stacked structures composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, and germanium-on-insulator, etc. The device layer includes, but is not limited to, one or more of photodiode arrays or metal layers. In this embodiment, silicon is used as an example of a substrate layer material to illustrate the semiconductor structure.

[0034] Please see Figure 1 As shown, in one embodiment of this utility model, the device wafer 200 includes a first surface 201, a second surface 202, a sidewall 203, a first corner 204, and a second corner 205. Specifically, the first surface 201 is the surface of the substrate layer, the second surface 202 is the surface of the device layer, and is bonded to the surface supporting the wafer 100. The sidewall 203 is arranged around the first surface 201 and the second surface 202. The first corner 204 connects the sidewall 203 and the first surface 201, and the second corner 205 connects the sidewall 203 and the second surface 202. The sidewall 203 is perpendicular to the first surface 201 and the second surface 202.

[0035] Please see Figures 1 to 2As shown, in one embodiment of this invention, an oxide layer 300 is formed by depositing an oxide material on the first surface 201, sidewall 203, first corner 204, and the exposed surface of the support wafer 100, for example, using a method such as plasma-enhanced chemical vapor deposition (PECVD). The oxide material includes, for example, silicon oxide. Specifically, during the PECVD process, a gas source diffuses and deposits on the device wafer 200 and the support wafer 100 in a direction perpendicular to the first surface 201. The oxide layer 300 deposited on the first corner 204 is defined as the first oxide layer 301, the oxide layer 300 deposited on the sidewall 203 is defined as the second oxide layer 302, the oxide layer 300 deposited on the exposed surface of the support wafer 100 is defined as the third oxide layer 303, and the oxide layer 300 deposited on the first surface 201 is defined as the fourth oxide layer 304. The gas source includes, for example, a silicon source and an oxygen source. The silicon source includes, for example, at least one of silane, tetraethyloxysilane, or dichlorosilane. The oxygen source includes, for example, at least one of nitrous oxide, oxygen, or ozone. The first oxide layer 301, the second oxide layer 302, the third oxide layer 303, and the fourth oxide layer 304 are continuously disposed. Further, during the PECVD process, since the contact surface between the first surface 201 and the gas source is 180°, the contact surface between the exposed surface of the wafer 100 and the gas source is 180°, and the contact surface between the first corner 204 and the gas source is 270°, the thickness of the first oxide layer 301 is greater than the thickness of the third oxide layer 303 and the thickness of the fourth oxide layer 304, and the thickness of the third oxide layer 303 and the thickness of the fourth oxide layer 304 are equal. Since the sidewall 203 is parallel to the gas source direction of PECVD, the thickness of the second oxide layer 302 decreases in the direction from the first surface 201 to the second surface 202. The thickness of the first oxide layer 301 is, for example, The thickness of the second oxide layer 302 is, for example, The thicknesses of the third oxide layer 303 and the fourth oxide layer 304 are, for example,

[0036] Please see Figures 2 to 3As shown, in one embodiment of this invention, etching solution is vertically sprayed only onto the fourth oxide layer 304 along a direction perpendicular to the second surface 202 to etch and remove the fourth oxide layer 304. However, during the vertical spraying process, a small amount of etching solution inevitably sprays onto the first oxide layer 301, the second oxide layer 302, and the third oxide layer 303, causing the first oxide layer 301, the second oxide layer 302, and the third oxide layer 303 to thin simultaneously, thereby obtaining a semiconductor structure. The etching solution is, for example, a diluted hydrofluoric acid solution, and the concentration of hydrofluoric acid in the etching solution is, for example, 0.1wt%-5wt%. The thickness of the first oxide layer 301 is, for example, [missing information]. The thickness of the second oxide layer is, for example, The thickness of the third oxide layer 303 is, for example, In the semiconductor structure, by setting the first oxide layer 301 as a protective layer, the first corner 204 can be protected from excessive grinding during the planarization of the device wafer 200, thereby improving the flatness of the device wafer 200. To explain the function of the first oxide layer 301 in detail, the planarization process of the semiconductor structure provided in this application is explained below.

[0037] Please see Figures 3 to 4 As shown, in one embodiment of this utility model, after obtaining the semiconductor structure provided in this application, an etching solution is sprayed a second time only on the sidewall 203 and the exposed surface of the supporting wafer 100 to etch and remove the second oxide layer 302 and the third oxide layer 303. However, during the second etching solution spraying process, a small amount of etching solution will inevitably be sprayed onto the first oxide layer 301, causing the first oxide layer 301 to be slightly thinned. The thickness of the first oxide layer 301 after thinning is, for example, [missing information]. Specifically, the nozzle is directed toward the sidewall 203, maintaining an angle between the nozzle and the sidewall 203, for example, between 45° and 90°. Etching solution is then sprayed onto the sidewall 203, and the nozzle is moved horizontally toward the exposed surface of the supporting wafer 100, spraying etching solution onto the surface of the supporting wafer 100. The etching solution is, for example, a diluted hydrofluoric acid solution, with a concentration of hydrofluoric acid in the etching solution, for example, between 0.1 wt% and 5 wt%. The flow rate of the etching solution during the second spraying is, for example, reduced by 15% to 25% compared to the first spraying.

[0038] Please see Figures 4 to 5As shown, in one embodiment of this utility model, after removing the second oxide layer 302 and the third oxide layer 303, the device wafer 200 is planarized for the first time by chemical mechanical polishing, for example, grinding the first oxide layer 301, the first surface 201, and the first corner 204 until the first oxide layer 301 is completely removed. Due to material limitations of the substrate layer of the device wafer 200 and the first oxide layer 301, the grinding rate of the first surface 201 is greater than that of the first oxide layer 301. The selectivity ratio of the polishing slurry for the first oxide layer 301 and the first surface 201 is, for example, 1:(100-300). Therefore, the first oxide layer 301 can protect the first corner 204, reducing the grinding rate of the first corner 204, resulting in the first surface 201 being lower than the apex of the first corner 204 after planarization and removal of the first oxide layer 301.

[0039] Please see Figures 5 to 6 As shown, in one embodiment of this utility model, after the first planarization, the device wafer 200 is planarized a second time, for example, by chemical mechanical polishing. Simultaneously, the first surface 201 and the first corner 204 are polished. Because the pressure applied by the polishing head and the polishing fluid tend to concentrate at the first corner 204, the polishing rate of the first corner 204 is greater than that of the first surface 201. However, the apex of the first corner 204 is itself higher than the first surface 201. The first corner 204, protruding from the first surface 201, can compensate for the difference in polishing rate between the first corner 204 and the first surface 201, thereby ensuring that the first corner 204 is not over-polished. Therefore, in the semiconductor structure provided in this application, the first oxide layer 301 can protect the first corner 204 from over-polishing, resulting in a device wafer 200 with high flatness, thereby improving the quality of subsequent process technology on the device wafer 200 and increasing product yield.

[0040] In summary, this utility model provides a semiconductor structure that, by setting an oxide layer on the corners of the device wafer, achieves the unexpected technical effect of protecting the corners from excessive grinding, improving the flatness of the device wafer, and thus improving the quality of subsequent manufacturing processes and increasing product yield. Furthermore, the semiconductor structure provided by this utility model can reduce defects at the corners of the device wafer, protecting the quality of the device wafer.

[0041] The embodiments of this utility model disclosed above are merely illustrative of the present utility model. The embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, characterized in that, At least including: Carrying wafer; A device wafer is disposed on the carrier wafer, and the device wafer includes a first surface and a second surface disposed opposite to each other, a sidewall and a first corner, the second surface is bonded to the surface of the carrier wafer, the sidewall is disposed around the first surface and the second surface, and the first corner connects the sidewall and the first surface; An oxide layer, at least covering the first corner.

2. The semiconductor structure according to claim 1, characterized in that, The oxide layer includes at least a first oxide layer that covers the first corner.

3. The semiconductor structure according to claim 2, characterized in that, The oxide layer further includes a second oxide layer that covers the sidewall.

4. The semiconductor structure according to claim 3, characterized in that, The oxide layer further includes a third oxide layer that covers the exposed surface of the carrier wafer.

5. The semiconductor structure according to claim 4, characterized in that, The first oxide layer, the second oxide layer, and the third oxide layer are disposed consecutively.

6. The semiconductor structure according to claim 4, characterized in that, The thickness of the first oxide layer is greater than the thickness of the third oxide layer.

7. The semiconductor structure according to claim 4, characterized in that, The thickness of the second oxide layer decreases in the direction from the first surface to the second surface.

8. The semiconductor structure according to claim 4, characterized in that, The thickness of the first oxide layer is The thickness of the second oxide layer is The thickness of the third oxide layer is 9. The semiconductor structure according to claim 1, characterized in that, The sidewall is perpendicular to the first surface and the second surface.

10. The semiconductor structure according to claim 1, characterized in that, The size of the carrier wafer is larger than the size of the device wafer.

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