A high-reliability MEMS capacitive pressure sensor sensitive chip
Patent Information
- Application Number
- CN202522405152.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-10-09
- Estimated Expiration
- 2035-11-13
AI Technical Summary
该方案微纳加工工艺难度大且工序复杂繁多,需昂贵仪器设备多,难以保证成品率
(1)本实用新型的敏感芯片方案采用超低电阻率(≤ 0.005 Ω·cm)的SOI晶圆,其器件层和衬底层分别作为敏感电容两电极板,用金属-硅欧姆接触实现电极线引出,避免了电极引线贯穿真空腔封装键合界面,增加敏感芯片的真空封装可靠性;
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Figure CN224839197U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electrical component technology, specifically to a highly reliable MEMS capacitive pressure sensor sensitive chip. Background Technology
[0002] Micro-Electro-Mechanical Systems (MEMS) capacitive pressure sensors are widely used in aerospace deep-air meteorological exploration (lunar exploration, Mars exploration, etc.), petrochemicals, environmental protection, medical applications, instrument pneumatic control, and industrial process monitoring and control. The basic mechanism of a MEMS capacitive pressure sensor is as follows: the micro-pressure-sensitive thin film of the sensing chip deforms under the measured pressure, thus changing the distance between the electrode plates and causing a change in capacitance. The sensor detects the capacitance to sense the measured pressure. The electrode plates require a vacuum-sealed reference cavity to deform under the measured pressure.
[0003] The vacuum level, long-term vacuum maintenance capability, and encapsulation stress of the vacuum reference cavity significantly impact the overall accuracy, temperature drift, and long-term stability of MEMS capacitive pressure sensors. Extracting the electrical signal from the vacuum reference cavity is a core technical challenge for the sensitive chip of MEMS capacitive pressure sensors. Micro-leakage caused by electrode leads penetrating the vacuum-sealed cavity, leakage under high / low temperature / mechanical conditions, and internal stress caused by differences in thermal expansion coefficients pose significant challenges and hidden dangers to sealing reliability, directly affecting the performance of the sensitive chip and the sensor. Furthermore, the micro-nano fabrication of the micro-pressure sensitive film is also crucial, as it decisively influences the resolution, stability, and other performance indicators of the micro-pressure sensor.
[0004] The micro / nano fabrication methods for the vacuum reference cavity of MEMS capacitive pressure sensor chips mainly include: direct bonding technology (silicon direct bonding, silicon glass anodic bonding, etc.) and intermediate layer bonding technology (metal hot pressing, BCB, glass paste, etc.). Electrode lead-out methods mainly include: thin metal electrode lead patterns directly passing through the bonding layer, and using ultra-low resistivity substrate materials directly as electrodes. The micro / nano fabrication methods for micro-pressure sensitive films mainly include: self-stopping etching of the SOI (Silicon on Insulator) device layer, and precise grinding, thinning, and polishing.
[0005] The absolute pressure micro-pressure sensor developed by Kang Ryeol Lee et al. (Kang Ryeol Lee, Kunnyun Kim. Fabrication of Capacitive Absolute Pressure Sensor Using Si-Au Eutectic Bonding in SOI Wafer. International MEMS Conference, 2006) employs the following method: Gold-silicon eutectic bonding is used to bond the SOI device layer to a pitted silicon wafer to form a vacuum-sealed reference cavity. Then, the substrate layer is removed to create a capacitor electrode film, which is then anoly bonded to a glass substrate with etched capacitor gaps, gas-conducting pits, and the capacitor electrode film. This method presents challenges due to the high-temperature outgassing phenomenon caused by metal co-solution in the gold-silicon eutectic bonding, leading to significant thermal mismatch. It also presents challenges in terms of packaging vacuum level, long-term reliability, and the impact of interface stress on chip performance. Furthermore, the capacitor gaps are connected to the measured gas pressure environment, reducing reliability, and requiring high dust protection. The capacitive absolute pressure sensor developed by ISSYS and the University of Michigan (Sonbol Massoud-Ansari, Yafan Zhang. An Ultra-Sensitive, High-Vacuum Absolute Capacitive Pressure Sensor. The 14th IEEE International Conference on MEMS, 2001) employs a sensitive thin-film micro / nano fabrication technology based on DWP (Dissolved Wafer Process), simultaneously achieving vacuum sealing and electrode wire lead-out using a polycrystalline silicon growth method. This approach involves complex micro / nano fabrication processes, requires expensive equipment, and struggles to guarantee a high yield. Summary of the Invention
[0006] This invention aims to solve the reliability problem of sensitive chips by providing a highly reliable MEMS capacitive pressure sensor sensitive chip, which includes a bonded SOI wafer and a bonded encapsulation cover glass; the SOI wafer includes a bonded wafer device layer, a wafer support layer, a wafer substrate layer, and a substrate through-hole structure connected to the wafer substrate layer. This invention utilizes an SOI wafer with ultra-low resistivity (≤ 0.005 Ω·cm). The device layer and substrate layer serve as the two electrode plates of the sensitive capacitor, respectively. Electrode leads are established using metal-silicon ohmic contacts, avoiding electrode leads penetrating the vacuum cavity packaging bonding interface and increasing the vacuum packaging reliability of the sensitive chip. The through-hole structure design of the SOI substrate layer of the sensitive chip balances the effective capacitor plate area with the corrosion release of the intermediate oxide layer. The device layer is a circular pressure-sensitive thin film, which significantly reduces parasitic capacitance while ensuring effective sensitivity to changes in gas pressure. The thickness of the intermediate oxide layer is the spacing between the sensitive capacitor electrode plates. The thickness of the sensitive film and the spacing between the capacitor electrode plates can be precisely controlled by the wafer, ensuring excellent sensor performance, consistency, and yield. The vacuum reference cavity of the sensitive chip is achieved through a single anodic bonding of the SOI wafer and glass, ensuring stability, reliability, and low thermal mismatch. A getter film is applied to the glass cover, which, upon activation, achieves a high vacuum degree and exhibits excellent long-term vacuum maintenance capability.
[0007] This invention provides a highly reliable MEMS capacitive pressure sensor sensing chip, comprising an SOI wafer and a bonded encapsulation cover glass bonded together from top to bottom; SOI wafers include, from top to bottom, a wafer device layer, a wafer support layer, a wafer substrate layer, and a substrate via structure that is connected through the wafer substrate layer. A bonding and encapsulation cover glass is connected to the bottom of the wafer substrate layer. The wafer device layer and the wafer substrate layer are the upper electrode plate and lower electrode plate of the pressure sensor sensitive chip, respectively. The wafer device layer includes a circular sheet structure, and the wafer support layer is a thin sheet structure with a circular through hole in the middle. The diameter of the through hole in the wafer support layer is smaller than the outer diameter of the circular part of the wafer device layer. The number of through hole structures in the substrate layer is at least two, and they are all located within the through hole range of the wafer support layer in the vertical direction.
[0008] In the preferred embodiment of the high-reliability MEMS capacitive pressure sensor sensing chip described in this invention, the top of the wafer device layer is a horizontal plane.
[0009] In the preferred embodiment of the high-reliability MEMS capacitive pressure sensor sensing chip described in this utility model, both the wafer device layer and the wafer substrate layer are made of single-crystal silicon and the resistivity of both is not greater than 0.005Ω•cm. The thickness of the wafer device layer is 1~1000μm, and the thickness of the wafer substrate layer is 100~800μm.
[0010] In a preferred embodiment of the high-reliability MEMS capacitive pressure sensor chip described in this invention, the wafer support layer is made of silicon dioxide and has a thickness of 300nm to 100μm.
[0011] The high-reliability MEMS capacitive pressure sensor sensing chip of this utility model, as a preferred embodiment, further includes a circular cover glass pit connected to the top of the bonding and encapsulating cover glass and a getter film connected to the bottom of the circular cover glass pit. The getter film has a circular sheet structure, with a height less than the depth of the circular cover glass groove and a diameter less than the diameter of the circular cover glass groove.
[0012] In a preferred embodiment of the high-reliability MEMS capacitive pressure sensor chip described in this invention, the diameter of the circular cover glass pit is the same as the diameter of the circular through-hole in the wafer support layer.
[0013] The high-reliability MEMS capacitive pressure sensor sensing chip of this utility model, as a preferred embodiment, further includes a wafer device layer ohmic contact connected to the upper surface of the wafer device layer and a wafer substrate layer ohmic contact connected to the upper surface of the wafer substrate layer. SOI wafers consist of a circular sheet structure and a convex corner structure connected to one side of the circular sheet structure. The ohmic contact of the wafer device layer is connected to the convex corner structure, and the outer edge of the convex corner structure is located on or inside the outer edge of the wafer substrate layer. Both the wafer device layer ohmic contact and the wafer substrate layer ohmic contact are metal electrodes. The wafer substrate layer ohmic contact is located below the wafer device layer ohmic contact and forms an ohmic contact through the wafer device layer. A notch is provided on the wafer support layer to avoid ohmic contact with the wafer substrate layer.
[0014] In a preferred embodiment of the high-reliability MEMS capacitive pressure sensor chip described in this utility model, both the ohmic contacts of the wafer device layer and the ohmic contacts of the wafer substrate layer are square. The notch in the wafer support layer is a square notch.
[0015] In a preferred embodiment of the high-reliability MEMS capacitive pressure sensor chip described in this invention, the outer edges of the wafer support layer, the wafer substrate layer, and the bonding and encapsulation cover glass are all square.
[0016] In a preferred embodiment of the high-reliability MEMS capacitive pressure sensor chip described in this utility model, the length and width of the wafer substrate layer and the bonding and packaging cover glass are the same. The length and width of the wafer support layer are both less than or equal to the diameter of the wafer device layer and the length and width of the wafer substrate layer.
[0017] This invention provides a highly reliable MEMS capacitive pressure sensor chip, comprising an SOI wafer and a bonding and encapsulation cover glass. The SOI wafer includes a wafer device layer, a wafer support layer, and a wafer substrate layer. The wafer device layer has a circular convex corner structure and is horizontally positioned at the top. The wafer support layer is fixedly mounted on the lower surface of the wafer device layer. The wafer substrate layer is fixedly mounted on the lower surface of the wafer support layer. The bonding and encapsulation cover glass is fixedly mounted on the lower surface of the wafer substrate layer. Compared with traditional MEMS capacitive pressure sensor chips, this invention avoids electrode leads penetrating the vacuum cavity encapsulation bonding interface through its structural design, enhancing the vacuum encapsulation reliability and long-term maintenance capability of the sensor chip. Furthermore, the required micro / nano processes are simple, reducing the internal stress introduced by multi-layer stacking manufacturing. The sensor's performance indicators, consistency, and yield can be well guaranteed.
[0018] This utility model has the following advantages: (1) The sensitive chip solution of this utility model uses an SOI wafer with ultra-low resistivity (≤ 0.005 Ω·cm). Its device layer and substrate layer are respectively used as the two electrode plates of the sensitive capacitor. The electrode lines are led out by metal-silicon ohmic contact, which avoids the electrode lines from penetrating the vacuum cavity packaging bonding interface and increases the vacuum packaging reliability of the sensitive chip. (2) The design of the through-hole structure of the SOI substrate layer of the sensitive chip of this utility model takes into account the trade-off between the effective capacitor plate area and the corrosion release of the intermediate oxide layer. The device layer is a circular pressure sensitive film, which can significantly reduce parasitic capacitance while ensuring effective sensitivity to changes in gas pressure. The thickness of the intermediate oxide layer is the spacing between the sensitive capacitor plates. The thickness of the sensitive film and the spacing between the capacitor plates can be controlled very precisely by the wafer. The performance indicators, consistency and yield of the sensor can be well guaranteed. (3) The vacuum reference cavity of the sensitive chip of this utility model is realized by one-time anodic bonding of SOI wafer and glass, which is stable and reliable with small thermal mismatch. A getter film is made on the glass cover plate, which can obtain a high vacuum degree after activation and has excellent long-term vacuum maintenance capability. (4) The pressure-sensitive capacitor gap of the present invention is encapsulated in a vacuum environment, and the capacitor medium is sealed and fixed in a vacuum and is not affected by the outside world. The sensor chip has good reliability and stability. (5) The sensitive chip of this invention, through structural optimization and the novel SOI structure, avoids the electrode leads penetrating the vacuum cavity packaging bonding interface without damaging the sealed cavity, thus enhancing the vacuum packaging reliability and long-term maintenance capability of the sensitive chip; at the same time, the SOI structure can precisely control the gap between the two electrode plates, ensuring the performance indicators, consistency, and yield of the sensor. Compared with the traditional MEMS process, this invention requires simple micro-nano process steps, has strong compatibility with processing equipment and processes, and a clear and definite processing route. Attached Figure Description
[0019] Figure 1 An exploded view of the sensing chip of a highly reliable MEMS capacitive pressure sensor; Figure 2 A cross-sectional view of the structure of a high-reliability MEMS capacitive pressure sensor sensing chip; Figure 3 This is a diagram of the SOI wafer structure of a highly reliable MEMS capacitive pressure sensor chip.
[0020] Figure label: 100. SOI wafer; 101. Wafer device layer; 102. Wafer support layer; 103. Wafer substrate layer; 104. Substrate layer via structure; 201. Bonding and encapsulation cover glass; 202. Circular cover glass pit; 301. Getter film; 401. Wafer device layer ohmic contact; 402. Wafer substrate layer ohmic contact. Detailed Implementation
[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Example 1
[0022] like Figures 1-3 As shown, a high-reliability MEMS capacitive pressure sensor chip includes an SOI wafer 100 and a bonding and encapsulation cover glass 201. The SOI wafer includes a wafer device layer 101, a wafer support layer 102, and a wafer substrate layer 103. The wafer device layer 101 has a circular convex corner structure and is horizontally located at the top. The wafer support layer 102 is fixedly mounted on the lower surface of the wafer device layer 101. The wafer substrate layer 103 is fixedly mounted on the lower surface of the wafer support layer 102. The bonding and encapsulation cover glass 201 is fixedly mounted on the lower surface of the SOI wafer substrate layer 103.
[0023] like Figure 2The figure shows a cross-sectional view of the sensitive chip structure. As can be seen from the figure, the wafer support layer 102 is a square thin sheet structure with a circular through hole in the middle. A cylindrical substrate through hole structure 104 is processed along the vertical direction of the wafer substrate layer 103. The wafer substrate through hole structure 104 is located within the circular through hole area of the wafer support layer 102 in the vertical direction.
[0024] The wafer support layer 102 is made of silicon dioxide. The thickness of the wafer support layer 102 is related to the intrinsic value of the sensitive barometric capacitive. Depending on the design, it can be in the nm to μm range, or between 300 nm and 6 μm.
[0025] The thickness of the wafer substrate layer 103 is 100~800μm.
[0026] A cuboid-structured wafer substrate ohmic contact 402 is fixedly mounted on the upper surface of the wafer substrate layer 103.
[0027] A cuboid-structured wafer device layer ohmic contact 401 is fixedly mounted on the upper surface of the wafer device layer 101.
[0028] Both the wafer device layer ohmic contact 401 and the wafer substrate layer ohmic contact 402 are electrodes, typically made of aluminum (Al). The wafer device layer ohmic contact 401 is on the wafer device layer 101, and the wafer substrate layer ohmic contact 402 is on the wafer substrate layer 103. Both the wafer device layer 101 and the wafer substrate layer 103 are made of single-crystal silicon with a resistivity of no more than 0.005 Ω•cm, and can be connected through Al electrodes to form ohmic contacts.
[0029] The wafer device layer 101 and the wafer substrate layer 103 serve as the two electrode plates of the capacitor. When the gas pressure changes, the distance between the two electrode plates changes. The change in capacitance can be measured through the electrodes, thereby reflecting the change in gas pressure. This avoids the electrode leads penetrating the vacuum cavity packaging bonding interface, enhancing the vacuum packaging reliability and long-term maintenance capability of the sensitive chip.
[0030] A circular cover glass recess 202 is provided on the upper surface of the bonding and encapsulation cover glass 201; the size of the circular cover glass recess 202 is consistent with the size of the circular through hole of the wafer support layer 102.
[0031] A getter film 301 is fixedly installed on the bottom surface of the circular cover glass groove 202.
[0032] The getter film 301 has a circular sheet structure, and the height of the getter film 301 is less than the depth of the circular cover glass groove 202.
[0033] The wafer device layer 101 and the wafer substrate layer 103 are made of single-crystal silicon, and the resistivity of both the wafer device layer 101 and the wafer substrate layer 103 is not greater than 0.005 Ω•cm.
[0034] Key areas for optimization in sensitive chip structure design: ① Optimization of the relationship between the thickness of the wafer device layer 101 and the diameter of the sensitive film and the range of the barometric pressure sensor. In this embodiment, the thickness of the wafer device layer 101 is 17 μm, the diameter of the sensitive film is about 3.6 mm, and the range of the sensor is 0 to 1.5 kPa. ② The thickness of the wafer support layer 102 of SOI wafer 100 is related to the intrinsic value of the sensitive gas pressure capacitor. In this embodiment, 6μm is selected and the intrinsic value of the sensitive capacitor is about 8pF. ③ The opening diameter and hole spacing of the substrate through-hole structure 104 are related to the wet etching release device layer as a sensitive thin film. In this embodiment, the diameter of the substrate through-hole structure 104 is 40μm and the hole spacing is 100μm. ④ The process control of wet etching side-drilling to release the device layer is optimized. In this embodiment, it is controlled to be about 40-50μm. This etching side-drilling will slightly increase the diameter of the sensitive film, and the design is optimized to compensate for this.
[0035] ⑤ When the load on the sensitive chip exceeds the range to a certain extent, the two plates come into contact together, and the output capacitance is close to zero.
[0036] The bonding method for the pressure sensor sensitive chip is as follows: the wafer device layer 101, the wafer support layer 102, the wafer substrate layer 103, and the bonding and packaging cover glass 201 are anoly bonded in one step.
[0037] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.
Claims
1. A highly reliable MEMS capacitive pressure sensor sensing chip, characterized in that: Includes SOI wafers (100) and bonded packaging cover glass (201) bonded from top to bottom; The SOI wafer (100) includes a wafer device layer (101), a wafer support layer (102), a wafer substrate layer (103), and a substrate through-hole structure (104) that are bonded together from top to bottom. The bonding and encapsulation cover glass (201) is connected to the bottom of the wafer substrate layer (103). The wafer device layer (101) and the wafer substrate layer (103) are the upper electrode plate and the lower electrode plate of the pressure sensor sensitive chip, respectively. The wafer device layer (101) includes a circular sheet structure. The wafer support layer (102) is a thin sheet structure with a circular through hole in the middle. The diameter of the through hole in the wafer support layer (102) is smaller than the outer diameter of the circular part of the wafer device layer (101). The number of through hole structures (104) in the substrate layer is at least two and they are all located within the through hole range of the wafer support layer (102) in the vertical direction.
2. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 1, characterized in that: The top of the wafer device layer (101) is a horizontal plane.
3. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 1, characterized in that: The wafer device layer (101) and the wafer substrate layer (103) are both made of single-crystal silicon and have a resistivity of no more than 0.005 Ω•cm. The thickness of the wafer device layer (101) is 1~1000μm, and the thickness of the wafer substrate layer (103) is 100~800μm.
4. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 1, characterized in that: The wafer support layer (102) is made of silicon dioxide and has a thickness of 300nm to 100μm.
5. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 1, characterized in that: It also includes a circular cover glass recess (202) connected to the top of the bonding and encapsulating cover glass (201) and a getter film (301) connected to the bottom of the circular cover glass recess (202). The getter film (301) is a circular sheet structure, with a height less than the groove depth of the circular cover glass groove (202) and a diameter less than the diameter of the circular cover glass groove (202).
6. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 5, characterized in that: The diameter of the circular cover glass pit (202) is the same as the diameter of the circular through hole of the wafer support layer (102).
7. A high-reliability MEMS capacitive pressure sensor sensing chip according to any one of claims 1 to 6, characterized in that: It also includes a wafer device layer ohmic contact (401) connected to the upper surface of the wafer device layer (101) and a wafer substrate layer ohmic contact (402) connected to the upper surface of the wafer substrate layer (103). The SOI wafer (100) is composed of the circular sheet structure and the convex corner structure connected to one side of the circular sheet structure. The wafer device layer ohmic contact (401) is connected to the convex corner structure. The outer edge of the convex corner structure is located on or inside the outer edge of the wafer substrate layer (103). Both the wafer device layer ohmic contact (401) and the wafer substrate layer ohmic contact (402) are metal electrodes. The wafer substrate layer ohmic contact (402) is located below the wafer device layer ohmic contact (401) and forms an ohmic contact through the wafer device layer (101). The wafer support layer (102) has a notch to avoid the ohmic contact (402) of the wafer substrate layer.
8. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 7, characterized in that: Both the wafer device layer ohmic contact (401) and the wafer substrate layer ohmic contact (402) are square; The notch in the wafer support layer (102) is a square notch.
9. The high-reliability MEMS capacitive pressure sensor sensing chip according to claim 1, characterized in that: The outer edges of the wafer support layer (102), the wafer substrate layer (103), and the bonding and encapsulation cover glass (201) are all square.
10. A high-reliability MEMS capacitive pressure sensor sensing chip according to claim 9, characterized in that: The wafer substrate layer (103) and the bonding and encapsulation cover glass (201) have the same length and width; The length and width of the wafer support layer (102) are both less than or equal to the diameter of the wafer device layer (101) and the length and width of the wafer substrate layer (103).