A carrier for chip testing, a chip testing device

Abstract

The application discloses a bearing for chip testing, a chip testing device, and the bearing is applied to the chip testing device. One side surface of the bearing is used for bearing a chip to be tested. A plurality of through grooves penetrating from top to bottom are arranged on the bearing. An optical fiber assembly is arranged on the side away from the chip to be tested. Optical fiber signals emitted by the optical fiber assembly can be coupled with waveguide light ports on the chip to be tested through the through grooves. The chip testing device comprises the bearing, a needle card module, and an alignment coupling mechanism. The needle card module is arranged above the bearing and comprises a test needle card used for connecting with contact points of the chip to be tested. The alignment coupling mechanism is arranged below the bearing and is used for driving the bearing to move in multiple dimensions. The bearing makes it possible to realize high-precision optical and electrical cooperative testing. The upper part of the bearing is used for electrical operation, and the lower part is used for optical operation, so that the space utilization is maximized.

Description

Technical Field

[0001] This application relates to the technical field of silicon photonics chip testing, and in particular to a carrier and a chip testing device for chip testing. Background Technology

[0002] In the field of silicon photonics chip testing, especially for the increasingly important CPO (Co-Packaged Optics) chips, existing technologies can usually only perform single optical or electrical tests, and cannot simultaneously meet the stringent requirements of optical path coupling and electrical probe connection, i.e., to achieve high-precision optical and electrical co-testing. Therefore, it is urgent to solve the above problems. Utility Model Content

[0003] In view of the above-mentioned problems in the prior art, the purpose of this application is to solve the defect that photoelectric testing cannot be performed simultaneously when the carrier carries the chip in the prior art.

[0004] To address the aforementioned issues, this application provides a carrier for chip testing, which is applied in a chip testing device. One side surface of the carrier is used to support the chip under test. The carrier has multiple through slots that extend vertically and are arranged in a sequential array. An optical fiber assembly is provided on the side away from the chip under test. The optical fiber signal emitted by the optical fiber assembly can be aligned and coupled with the waveguide port on the chip under test through the through slots.

[0005] Preferably, along the transmission direction of the optical fiber signal, the through slot sequentially includes a clearance portion and a transmission portion, the inner diameter of the clearance portion being larger than the inner diameter of the transmission portion, and the clearance portion being used for adjusting the attitude of the optical fiber assembly.

[0006] Preferably, the carrier includes: An adsorption layer is disposed on the bearing surface of the carrier and is used to adsorb the chip under test; A cooling layer is disposed close to the adsorption layer. The cooling layer includes a circulation channel disposed on the plate between adjacent through slots. The circulation channel is used to introduce a cooling medium to cool the chip under test. A heating layer is disposed on the side of the cooling layer opposite to the adsorption layer, and is used to heat the chip under test.

[0007] Preferably, the through slot is strip-shaped and extends laterally along the transmission direction perpendicular to the optical fiber signal, and multiple through slots are arranged in parallel in sequence. The circulation channel is disposed on the plate between adjacent through slots, and the direction of the circulation channel is parallel to the extension direction of the through slots.

[0008] Preferably, the carrier further includes: A cooling medium inlet is provided at one end of the plurality of circulating channels to distribute the cooling medium into each of the circulating channels; A cooling medium outlet is located at the other end of the plurality of circulating channels to discharge the cooling medium after it has been collected from the carrier.

[0009] Preferably, the plate body between adjacent through slots includes a plurality of circulation channels, all of which are disposed close to the adsorption layer and arranged sequentially at intervals.

[0010] Preferably, the heating layer is a ceramic heater or a polyimide film heater.

[0011] A chip testing apparatus, comprising: The carrier described in any of the above items is used to carry the chip under test; A pin card module is disposed above the carrier, and the pin card module includes a test pin card, which is used to dock with the contact point of the chip under test; An alignment coupling mechanism is disposed below the carrier component and is used to drive the carrier component to move in multiple dimensions.

[0012] Preferably, the alignment coupling mechanism includes: A motion platform, wherein the support member is disposed on the motion platform, the motion platform is used to drive the support member to move, and an accommodating space is formed between the motion platform and the support member; A six-axis fiber optic alignment module is disposed in the accommodating space to drive the fiber optic assembly to move, so that the fiber optic assembly can be aligned with the waveguide port of the chip under test after passing through the slot.

[0013] Preferably, the chip testing apparatus further includes a vision mechanism, the vision mechanism comprising: The upper vision component is disposed on the side of the pin card module facing the carrier, and is used to collect the contact point position information of the chip under test; A lower vision component is disposed on the side of the carrier facing the needle card module, and is used to collect the needle tip position information of the test needle card.

[0014] Based on the above technical solutions, the carrier and chip testing apparatus for chip testing described in this application have the following beneficial effects: The space above the carrier can be used to arrange electrical testing equipment, such as probe cards, allowing the probe cards to access the contact points of the chip under test (DUT) from above without obstruction for electrical signal input / output and testing. The space below the carrier can be used to arrange fiber optic components, such as fiber optic arrays, to achieve precise alignment between the fiber optic array and the waveguide port in the DUT. This solves the problem in traditional solutions where optical and electrical testing of the DUT cannot be performed simultaneously. Therefore, this application enables high-precision optical and electrical co-testing through the structural design of the carrier and physical isolation. At the same time, the upper part of the carrier is used for electrical operations, and the lower part is used for optical operations, making effective use of vertical space and maximizing space utilization. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0016] Figure 1 This is a schematic diagram of the overall structure of the carrier provided in the embodiments of this application.

[0017] Figure 2 This is a cross-sectional view of the carrier provided in the embodiment of this application in the first direction.

[0018] Figure 3 This is a cross-sectional view of the carrier provided in the embodiment of this application in the second direction.

[0019] Figure 4 yes Figure 3 A magnified view of section A in the image.

[0020] Figure 5 This is a schematic diagram of the overall structure of the chip testing device provided in the embodiments of this application.

[0021] Figure 6 This is a schematic diagram of the structure of the carrier and the alignment coupling mechanism provided in the embodiments of this application.

[0022] Figure 7 This is a top-view structural diagram of the pin card module provided in the embodiment of this application.

[0023] The reference numerals in the attached drawings are as follows: 100, carrier; 11, adsorption layer; 12, cooling layer; 121, circulation channel; 122, cooling medium inlet; 123, cooling medium outlet; 13, heating layer; 14, through groove; 141, clearance part; 142, penetrating part; 200. Chip under test; 300. Chip testing device; 31. Needle card module; 311. Test needle card; 312. Upper vision component; 32. Alignment coupling mechanism; 321. Motion platform; 322. Six-axis fiber optic alignment module; 323. Lower vision component; P. Transmission direction of fiber optic signal. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "left," "right," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0026] like Figures 1-4 As shown, this application embodiment provides a carrier 100 for chip testing, which is applied in a chip testing device 300. One side surface of the carrier 100 is used to support the chip under test 200. The carrier 100 is provided with a plurality of vertically penetrating slots 14, which are arranged in a sequential array. An optical fiber assembly is provided on the side away from the chip under test 200. The optical fiber signal emitted by the optical fiber assembly can be aligned and coupled with the waveguide optical port on the chip under test 200 through the slots 14.

[0027] It should be noted that the chip under test 200 can be a silicon photonic chip, and the upper surface of the silicon photonic chip is provided with pad positions for alignment and connection with electrical probes to realize the testing of the electrical performance of the silicon photonic chip; the lower surface of the silicon photonic chip is provided with a waveguide optical port, and the optical fiber signal emitted by the optical fiber assembly is aligned and coupled with the waveguide optical port of the silicon photonic chip to realize the testing of the optical performance of the silicon photonic chip.

[0028] It is understood that the fiber optic assembly is positioned on the side of the carrier 100 away from the chip under test 200, that is, in this embodiment, the fiber optic assembly is located below the carrier 100. The fiber optic signal emitted by the fiber optic assembly can be aligned and coupled with the waveguide port of the chip under test 200 through the through slot 14. The through slot 14 provides interference-free clearance for the transmission of the fiber optic signal, ensuring that the fiber optic signal emitted by the fiber optic assembly can be accurately aligned and coupled with the waveguide port of the chip under test 200.

[0029] Furthermore, placing the fiber optic assembly on the back side of the chip under test 200 avoids interference between the fiber optic assembly and the electrical probes or test circuits on the front side of the chip under test 200, which is especially suitable for scenarios where CPO chips need to be tested simultaneously with optical and electrical components.

[0030] In this embodiment of the application, the chip under test 200 refers to the CPO chip or silicon photonics chip that needs to be tested.

[0031] Therefore, in this embodiment, the space above the carrier 100 can be used to arrange electrical testing equipment, such as probe cards, so that the probe cards can contact the contact points of the chip under test 200 from above without obstruction, for input / output and testing of electrical signals; the space below the carrier 100 can be used to arrange optical fiber components, such as optical fiber arrays, to achieve precise alignment between the optical fiber array and the waveguide optical port in the chip under test 200, thereby solving the problem that the traditional solution cannot perform optical and electrical testing on the chip under test 200 at the same time. Therefore, this application, through the structural design of the carrier 100, makes high-precision optical and electrical collaborative testing possible through physical isolation. At the same time, the space above the carrier 100 is used for electrical operation, and the space below is used for optical operation, so that the vertical space is effectively utilized and the space utilization is maximized.

[0032] In this embodiment, the width of the through slot 14 is generally greater than the outer diameter of the optical fiber assembly. Preferably, the width of the through slot 14 is between 4-8 mm. In actual use, a carrier 100 with a corresponding slot width can be matched according to the different specifications and sizes of the chip under test 200. This design can both avoid affecting the alignment and coupling of the optical fiber signal with the waveguide port and avoid the carrier 100 having insufficient support for the chip under test 200 due to an excessively large slot width of the through slot 14.

[0033] like Figure 4As shown, along the transmission direction P of the optical fiber signal, the through slot 14 includes a clearance portion 141 and a transmission portion 142 in sequence. The inner diameter of the clearance portion 141 is larger than the inner diameter of the transmission portion 142, that is, the clearance portion 141 forms a clearance space, which facilitates the optical fiber assembly to further adjust its posture within the clearance space to meet the optical coupling requirements.

[0034] It is understandable that the space of the clearance section 141 is larger than the space of the penetration section 142, providing physical space and degrees of freedom for the alignment of the optical fiber assembly and the chip under test 200. That is, in the process of the optical fiber signal penetrating from below the carrier 100 and finally coupling with the waveguide port of the chip under test 200, a fine alignment adjustment needs to be made in the clearance section 141.

[0035] Understandably, the penetration portion 142 provides precise positioning and guidance for the optical fiber assembly. That is, when the optical fiber tip of the optical fiber assembly moves upward from the relief portion 141 to prepare for alignment and coupling with the waveguide optical port of the chip under test 200, the small inner diameter of the penetration portion 142 not only allows the optical fiber signal to pass through the carrier 100, but also ensures that the carrier 100 provides stable support for the chip under test 200.

[0036] Therefore, the use of a larger inner diameter clearance portion 141 solves the physical constraint problem of high-precision multi-axis alignment in a confined space, thereby achieving precise alignment between the fiber optic assembly and the waveguide port of the chip under test 200. Furthermore, the smaller inner diameter of the penetration portion 142 not only provides space for the fiber optic signal to pass through but also enhances the stability of the support of the carrier 100 for the chip under test 200, ensuring the stability of the chip performance test.

[0037] like Figure 4 As shown, the carrier 100 includes: The adsorption layer 11 is disposed on the bearing surface of the carrier 100 and is used to adsorb the chip 200 to be tested. Cooling layer 12 is disposed close to adsorption layer 11. Cooling layer 12 includes circulation channel 121. Circulation channel 121 is disposed on the plate between adjacent through slots 14. Circulation channel 121 is used to introduce cooling medium for cooling chip 200 under test. The heating layer 13 is disposed on the side of the cooling layer 12 away from the adsorption layer 11 and is used to heat the chip 200 to be tested.

[0038] It is understandable that the carrier 100 consists of an adsorption layer 11, a cooling layer 12, and a heating layer 13 from top to bottom.

[0039] In this embodiment, the adsorption layer 11 uses vacuum adsorption to fix the chip under test 200. Vacuum adsorption can make the chip under test 200 completely adhere to the surface of the carrier 100, ensuring good contact between the chip under test 200 and the carrier 100, laying the foundation for subsequent temperature control.

[0040] It is understandable that the circulation channel 121 is provided on the solid portion that avoids the through slot 14.

[0041] In a possible embodiment, the circulation channel 121 can be a serpentine or parallel channel to ensure uniform cooling. Furthermore, by providing the circulation channel 121 on the solid portion between adjacent through slots 14, the circulation channel 121 can be distributed throughout the solid portion of the support 100 like a "mesh" or "ribs".

[0042] Furthermore, when the cooling medium flows through these densely distributed circulation channels 121, it can quickly and evenly remove the heat generated by the chip under test 200, avoiding local hot spots and thus ensuring the uniformity of the heating temperature of the chip under test 200.

[0043] Understandably, the cooling medium can be either coolant or cooling gas, and the specific choice can be adjusted based on cooling requirements.

[0044] Understandably, with the heating layer 13 located at the bottom, heat is conducted upwards through the entire carrier 100 to the chip under test 200. Compared to placing the heating layer 13 at the top, this design provides more uniform heating. Simultaneously, the circulation channels 121 cover the entire carrier surface, ensuring uniform cooling.

[0045] Understandably, the "cooling layer 12" and the "heating layer 13" together constitute an active temperature control system. The cooling layer 12 carries away heat by introducing a cooling medium through the "circulation channel 121," while the heating layer 13 provides heat. Many chips require performance testing at specific temperatures. The coordinated operation of the heating layer 13 and the cooling layer 12 can precisely control the chip under test 200 at the target test temperature, simulating its working environment in actual equipment, thereby verifying reliability. Therefore, this integrated cooling and heating design allows the carrier component 100 to both cool and heat up, thus achieving precise and dynamic temperature control of the chip under test 200.

[0046] Furthermore, the design of the through slot 14 disrupts the integrity of the support member 100 structure, making it extremely difficult to continuously arrange cooling / heating channels. Therefore, in the conventional approach, the integrated temperature control function might be abandoned. However, in this application, by setting the circulation channel 121 on the plate between adjacent through slots 14, the obstacle is cleverly bypassed, and the temperature control function is realized in the hollow structure.

[0047] Preferably, the heating layer 13 is a ceramic heater or a polyimide film heater (PI film heater).

[0048] In a preferred embodiment, the through slot 14 is strip-shaped and extends laterally along the transmission direction P perpendicular to the optical fiber signal. Multiple through slots 14 are arranged in parallel in sequence. The circulation channel 121 is disposed on the plate between adjacent through slots 14, and the direction of the circulation channel 121 is parallel to the extension direction of the through slot 14.

[0049] Understandably, the circulating channel 121 with the above-described structure can cool the chip 200 under test over a large area and uniformly, avoiding local hot spots and creating the most efficient heat dissipation path and the most uniform temperature field.

[0050] In a possible embodiment, the through slot 14 can be oval, providing greater leeway for the orientation adjustment of the fiber optic assembly.

[0051] like Figure 2 As shown, the carrier 100 also includes: A cooling medium inlet 122 is provided at one end of a plurality of circulation channels 121 to distribute the cooling medium to each circulation channel 121; Cooling medium outlet 123 is located at the other end of multiple circulation channels 121 for discharging cooling medium from the carrier 100 after it has been collected.

[0052] It is understandable that this application adopts a parallel layout of "one inlet and multiple outlets, multiple inlets and one outlet". After the cooling medium enters from a single "cooling medium inlet 122", it is diverted to all the parallel circulating channels 121, flows through the entire carrier 100, and then flows out from the "cooling medium outlet 123" at the other end.

[0053] Therefore, this parallel cooling scheme ensures that each circulating channel 121 can obtain almost the same cooling medium flow rate, avoiding the problem in the series layout (channels connected end to end) where the medium temperature is higher and the cooling effect is worse as it goes downstream. The uniform flow rate directly ensures the uniformity of temperature distribution on the entire carrier 100 plane, which is crucial for the accuracy and consistency of the test data of the chip under test 200, and can also prevent the leakage of cooling medium. Furthermore, all circulating channels 121 operate simultaneously, which means that the heat dissipation area of ​​the entire support component 100 is fully utilized. Compared with a complex serpentine single channel, this multi-channel parallel design greatly reduces the total length of the flow path and the flow resistance, allowing the cooling medium to flow through the heat dissipation area at a faster flow rate and with lower pressure loss, thereby significantly improving the overall heat exchange efficiency.

[0054] Furthermore, in a possible embodiment, a temperature sensor can be set only at the "cooling medium outlet 123" to effectively monitor the average thermal load of the entire carrier 100. This temperature signal can be used as feedback to send to an external temperature control unit, and the temperature of the chip under test 200 can be precisely controlled by dynamically adjusting the flow rate or temperature of the cooling medium.

[0055] In a preferred embodiment, the plate body between adjacent through slots 14 includes multiple circulation channels 121, which are all disposed close to the adsorption layer 11 and arranged in sequence at intervals.

[0056] Understandably, within the same lateral space, the total area of ​​multiple circulation channels 121 is much larger than the area of ​​a single circulation channel 121. According to the basic principles of heat conduction, the heat exchange area is directly proportional to the heat dissipation efficiency. Therefore, this design significantly increases the contact area between the cooling medium and the support component 100, thereby greatly improving the heat dissipation capacity per unit area.

[0057] Furthermore, when the chip under test 200 is working, especially in the area where the electrical probe contacts, it generates a very concentrated amount of heat. Therefore, by closely arranging multiple circulation channels 121 below these areas and close to the heat source, the concentrated heat can be quickly dissipated, preventing local overheating and protecting the chip under test 200 from thermal damage, thereby ensuring the test accuracy.

[0058] On the other hand, the role of silicon photonics chip testing is to verify the optoelectronic functions and performance of the chip through precise measurement, screen out products with defects in manufacturing to ensure product yield, and thus ensure the product quality and reliability of cutting-edge technologies such as CPO chips.

[0059] like Figures 5-7 As shown in the figure, this application embodiment also provides a chip testing apparatus 300, which includes: The carrier 100 of any of the above is used to carry the chip under test 200; The pin card module 31 is disposed above the carrier 100. The pin card module 31 includes a test pin card 311, which is used to dock with the contact point of the chip under test 200. The alignment coupling mechanism 32 is located below the support member 100 and is used to drive the support member 100 to move in multiple dimensions.

[0060] Understandably, the test pin card 311 on the pin card module 31 is used to make an electrical connection with the contact points on the chip under test 200 so as to perform electrical tests.

[0061] like Figure 6 As shown, the alignment coupling mechanism 32 includes: The motion platform 321 has a support member 100 mounted on it. The motion platform 321 is used to move the support member 100. An accommodating space is formed between the motion platform 321 and the support member 100. A six-axis fiber optic alignment module 322 is set in the accommodating space to drive the fiber optic assembly to move, so that the fiber optic assembly can be aligned with the waveguide port of the chip under test 200 through the through slot 14.

[0062] Understandably, the motion platform 321 drives the entire carrier 100, the chip under test 200, and the six-axis fiber optic alignment module 322 to move over a wide range and in multiple dimensions, so that the contact points of the chip under test 200 are moved to the target position. This allows for the rapid and accurate movement of the electrical contact points on the chip under test 200 to the position where the test pin card 311 in the upper pin card module 31 can be precisely aligned, thus completing the physical connection for electrical testing. After the electrical connection is established, the six-axis fiber optic alignment module 322 begins to work. Based on the position already positioned by the motion platform 321, it drives the fiber optic assembly to move to a position below the waveguide port of the chip under test 200. Finally, the fiber optic assembly drives the fiber tip to perform micron-level, multi-degree-of-freedom (e.g., pitch, yaw, rotation) fine adjustments, i.e., it drives the fiber tip to perform a helical motion to achieve the maximum optical power position coupling between the fiber optic signal and the waveguide port on the chip under test 200.

[0063] In this embodiment, the motion platform 321 can drive the carrier 100 and the chip under test 200 on it to move on the X-axis, Y-axis, and Z-axis and rotate along its own axis, and can synchronously drive the six-axis fiber alignment module 322 to move on the Y-axis and Z-axis and rotate along its own axis.

[0064] As can be seen, this application achieves the alignment of electrical test points by using a decoupling method, where the motion platform 321 can move the chip under test 200 to its pad position and align it with the test pin card 311. The six-axis fiber optic alignment module 322 drives the fiber optic assembly to align and couple with the optical port position of the chip under test 200, thus balancing the efficiency of large-range movement with the precision of micron-level adjustment.

[0065] Furthermore, the six-axis fiber alignment module 322 is placed in a space between the motion platform 321 and the carrier 100. This vertically stacked "sandwich" structure integrates two functionally independent motion units into a compact whole, which not only maximizes the use of space, but also ensures that all movements and adjustments of the six-axis fiber alignment module 322 will not interfere with the pin card module 31 located above the carrier 100 because the six-axis fiber alignment module 322 is completely housed in the space below the carrier 100. This provides a highly operable physical platform for optical and electrical collaborative testing, ensuring that electrical and optical operations do not interfere with each other.

[0066] In a preferred embodiment, the chip testing apparatus 300 further includes a vision mechanism, which includes: The upper vision component 312 is located on the side of the pin card module 31 facing the carrier 100, and is used to collect the contact point position information of the chip under test 200. The lower vision component 323 is disposed on the side of the carrier 100 facing the needle card module 31, and is used to collect the needle tip position information of the test needle card 311.

[0067] Understandably, the upper vision component 312, looking from top to bottom, can identify the chip under test 200 and accurately obtain the coordinate positions of all electrical contact points on it. The lower vision component 323, looking from bottom to top, can identify the test pin card 311 and accurately obtain the coordinate positions of each probe tip on it.

[0068] Therefore, the vision mechanism can obtain the real position of the chip under test 200 and the test pin card 311 in real time and directly, fundamentally eliminating accumulated errors and achieving micron-level high-precision alignment.

[0069] Furthermore, the chip testing device 300 also includes a control system electrically connected to the vision mechanism. This control system compares the contact point position information acquired by the upper vision component 312 with the tip position information acquired by the lower vision component 323 to calculate the precise displacement deviation. This deviation value is then used to drive the lower alignment coupling mechanism 32, moving the carrier 100 (and the chip under test 200) until the test tip aligns with the contact point, thus achieving fully automatic, unattended, high-precision electrical alignment. Therefore, after electrical alignment is completed by the vision mechanism, the precise position of the chip under test 200 in the device coordinate system is uniquely determined, and this position information serves as the reference for subsequent optical alignment.

[0070] Therefore, the entire workflow of the chip testing device 300 can be summarized as follows: First, the upper vision component 312 identifies the contact point position information of the chip under test 200, and the lower vision component 323 identifies the tip position information of the test pin card 311. Secondly, based on visual information, the control system controls the motion platform 321 to move the carrier 100 and the chip under test 200 on it horizontally, so that the contact point of the chip under test 200 is precisely aligned with the tip of the test pin card 311. Meanwhile, the control system obtains the waveguide position according to the map (design drawing) of the chip under test 200, and controls the six-axis fiber alignment module 322 to drive the fiber optic assembly to move to the position of the through slot 14 of the carrier 100 and move it in a spiral motion, thereby driving the fiber optic assembly to adjust its attitude to be aligned and coupled with the corresponding waveguide optical port. Finally, the motion platform 321 drives the carrier 100 to rise and fall (Z-axis movement), so that the tip of the test pin card 311 is inserted into the contact point of the chip under test 200, completing the electrical connection; at the same time, the optical fiber assembly has achieved optical coupling with the waveguide optical port of the chip under test 200, thereby simultaneously completing the optical and electrical coordinated testing of the CPO chip under test 200.

[0071] The foregoing description has fully disclosed the specific embodiments of this application. It should be noted that any modifications made by those skilled in the art to the specific embodiments of this application do not depart from the scope of the claims. Accordingly, the scope of the claims of this application is not limited to the foregoing specific embodiments.

Claims

1. A carrier for chip testing, characterized in that, It is used in chip testing equipment. One side surface of the carrier is used to support the chip under test. The carrier is provided with multiple through slots that run vertically through each other. The multiple through slots are arranged in an array in sequence. An optical fiber assembly is provided on the side away from the chip under test. The optical fiber signal emitted by the optical fiber assembly can be aligned and coupled with the waveguide optical port on the chip under test through the through slots.

2. The carrier according to claim 1, characterized in that, Along the transmission direction of the optical fiber signal, the through slot sequentially includes a clearance section and a transmission section. The inner diameter of the clearance section is larger than the inner diameter of the transmission section. The clearance section is used to allow the optical fiber assembly to adjust its attitude.

3. The carrier according to claim 1, characterized in that, The carrier includes: An adsorption layer is disposed on the bearing surface of the carrier and is used to adsorb the chip under test; A cooling layer is disposed close to the adsorption layer. The cooling layer includes a circulation channel disposed on the plate between adjacent through slots. The circulation channel is used to introduce a cooling medium to cool the chip under test. A heating layer is disposed on the side of the cooling layer opposite to the adsorption layer, and is used to heat the chip under test.

4. The carrier according to claim 3, characterized in that, The through slot is strip-shaped and extends laterally along the transmission direction perpendicular to the optical fiber signal. Multiple through slots are arranged in parallel in sequence. The circulation channel is disposed on the plate between adjacent through slots, and the direction of the circulation channel is parallel to the extension direction of the through slots.

5. The carrier according to claim 4, characterized in that, The carrier also includes: A cooling medium inlet is provided at one end of the plurality of circulating channels to distribute the cooling medium into each of the circulating channels; A cooling medium outlet is located at the other end of the plurality of circulating channels to discharge the cooling medium after it has been collected from the carrier.

6. The carrier according to claim 4, characterized in that, The plate body between adjacent through slots includes multiple circulation channels, which are all located close to the adsorption layer and arranged sequentially at intervals.

7. The carrier according to claim 3, characterized in that, The heating layer is a ceramic heater or a polyimide film heater.

8. A chip testing device, characterized in that, It includes: The carrier according to any one of claims 1-7 is used to carry the chip under test; A pin card module is disposed above the carrier, and the pin card module includes a test pin card, which is used to dock with the contact point of the chip under test; An alignment coupling mechanism is disposed below the carrier component and is used to drive the carrier component to move in multiple dimensions.

9. The chip testing apparatus according to claim 8, characterized in that, The alignment coupling mechanism includes: A motion platform, wherein the support member is disposed on the motion platform, the motion platform is used to drive the support member to move, and an accommodating space is formed between the motion platform and the support member; A six-axis fiber optic alignment module is disposed in the accommodating space to drive the fiber optic assembly to move, so that the fiber optic assembly can be aligned with the waveguide port of the chip under test after passing through the slot.

10. The chip testing apparatus according to claim 8, characterized in that, The chip testing apparatus further includes a vision mechanism, which comprises: The upper vision component is disposed on the side of the pin card module facing the carrier, and is used to collect the contact point position information of the chip under test; A lower vision component is disposed on the side of the carrier facing the needle card module, and is used to collect the needle tip position information of the test needle card.

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