High-side high-voltage current high-speed sampling circuit
Patent Information
- Application Number
- CN202621367792.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-01
- Publication Date
- 2026-10-09
- Estimated Expiration
- 2036-09-01
AI Technical Summary
[0006]本实用新型的目的在于提供高侧高压电流高速采样电路，以解决背景技术中提出的传统高侧电流采样电路中，因误差放大电路输出节点的寄生电容过大，导致电路的环路主极点频率减小、带宽严重受限的问题
本实用新型通过电压钳位模块构建了低压电源轨（采用5V电源轨），避免了在误差放大电路中使用高压LDMOS管，从而显著减少了运放输出节点由高压管漏端带来的PN结寄生电容。本实用新型使用单独的小尺寸PMOS管（MFB）将运放输出节点与大尺寸的电流镜像管进行隔离，使得运放输出节点的电容贡献主要转变为该小尺寸管极小的栅源寄生电容，有效避免了电流镜大尺寸管带来的负载寄生电容过大问题。实现高速、高带宽采样：通过上述电压域和负载端双重电容隔离机制，本实用新型显著降低了节点OUT_G处的等效输出电容，有效提高了电路的环路主极点频率和单位增益带宽，最终实现了高速、高带宽的高侧电流采样电路设计需求。
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Figure CN224840324U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit technology, specifically a high-side high-voltage current high-speed sampling circuit. Background Technology
[0002] High-side current sampling circuits are widely used in switching power supply systems, high-side switching systems, and high-speed, high-precision current detection systems for robot motors. High-side current sampling modules typically require high speed and high bandwidth to ensure faster sampling of the high-side current signal.
[0003] In a typical high-side current sampling circuit, such as Figure 1 and Figure 2 As shown, its working principle is that when there is a voltage difference between the CSP (positive input terminal) node and the CSN (negative input terminal) node, due to the virtual short characteristic of the op-amp, INP = INN (where INP corresponds to the CSP node and INN corresponds to the CSN node). At this time, the feedback current IFB passes through the first resistor R1, and is mirrored by current mirror transistors Mcm1 and Mcm2, and then converted into voltage signals VSNS1 and VSNS2 through resistors. When the current mirror transistors Mcm1 and Mcm2 have the same size, the following relationship can be listed: VSNS1=(1 / 2 IFB) R3; CSN-ISS R² = CSP - (ISS + IFB) R1; CSP-CSN=IL RCS; R1=R2; This leads to the derivation that: VSNS1 = 1 / 2 (R3 / R2) IL RCS; where ISS is the bias current value, IL is the sampling current value, RCS is the sampling resistor value, IFB is the feedback current value, R1 is the first resistor, R2 is the second resistor, and R3 is the third resistor.
[0004] From the above structure, its transfer function can be derived as follows: LOOPGAIN(s) = gm_Mcm1 R1 GM (ROUT / / (1 / (S COUT)))=gm_Mcm1 R1 GM (ROUT / (1+S ROUT COUT)); In the formula, GM is the equivalent input transconductance of the error amplifier circuit and R1, gm_Mcm1 is the equivalent transconductance of MOSFET Mcm1, ROUT is the output impedance of the op-amp, and COUT is the equivalent output capacitance of the op-amp (i.e., the sum of the parasitic capacitances of the output node OUT_G). The pole locations and loop bandwidth of this circuit are as follows: Wp=1 / (ROUT COUT); GBW (gm_Mcm1 R1 GM) / (2 π COUT).
[0005] Where Wp is the pole location and GBW is the loop bandwidth. To meet the requirements of high speed and high bandwidth, it is necessary to increase the equivalent transconductance GM of the error amplifier circuit and simultaneously reduce the equivalent output capacitance COUT. However, existing technologies have the following significant drawbacks: In existing technologies, since the input voltage VIN is usually high voltage, the error amplifier circuit needs to use a high-voltage operational amplifier. The high-voltage operational amplifiers used in traditional solutions usually introduce high-voltage MOSFETs (such as nLDMOS and pLDMOS), whose drain terminals contain high-voltage withstand structures, resulting in significant PN junction capacitance. At the same time, in traditional structures, the main current mirror is directly connected to the operational amplifier output. Due to the high accuracy requirements of current sampling, a large-size MOSFET is often required to reduce the image mismatch of the current mirror. Therefore, the operational amplifier output node OUT_G is connected to both the high-voltage MOSFET and the large-size current mirror MOSFET, resulting in excessively large parasitic capacitance at the output node. This reduces the loop pole frequency, limits the loop bandwidth, and restricts the current sampling speed, making it difficult to meet the design requirements of high speed and high bandwidth. Utility Model Content
[0006] The purpose of this invention is to provide a high-speed sampling circuit for high-side high-voltage current, in order to solve the problem in the traditional high-side current sampling circuit mentioned in the background art, where the parasitic capacitance of the output node of the error amplifier circuit is too large, resulting in a decrease in the loop main pole frequency and a severe limitation in bandwidth.
[0007] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: The high-side high-voltage current high-speed sampling circuit includes: a voltage clamping module, an error amplifier circuit, an isolation module, and a current mirror module; The voltage clamping module includes a first diode, a second diode, and a first high-voltage PMOS transistor. The cathode of the first diode is connected to the power supply VIN, and its anode is connected to the gate of the first high-voltage PMOS transistor. The drain of the first high-voltage PMOS transistor is grounded, and its source is connected to the anode of the second diode and the ground terminal of the error amplifier circuit, so as to construct a low-voltage power rail between the power supply VIN and the error amplifier circuit. The isolation module includes a small-sized PMOS transistor. The gate of the small-sized PMOS transistor is connected to the output terminal of the error amplifier circuit, its source is connected to the current mirror module, and its drain is grounded through a high-voltage device. The small-sized PMOS transistor isolates the parasitic capacitance between the output terminal of the error amplifier circuit and the current mirror module.
[0008] According to the above technical solution, it also includes a sampling resistor, a first resistor, and a second resistor; the upper end of the sampling resistor is connected to the upper end of the first resistor, the power supply VIN, the negative terminal of the first diode, and the negative terminal of the second diode, and the lower end of the sampling resistor is connected to the upper end of the second resistor; the lower ends of the first resistor and the lower ends of the second resistor are respectively connected to the two input terminals of the error amplifier circuit.
[0009] According to the above technical solution, the current mirror module includes a first current mirror PMOS transistor and a second current mirror PMOS transistor; the source of the small-sized PMOS transistor is connected to the gate of the first current mirror PMOS transistor and the gate of the second current mirror PMOS transistor; the source of the first current mirror PMOS transistor and the source of the second current mirror PMOS transistor are both connected to the lower end of the first resistor.
[0010] According to the above technical solution, the high-voltage device includes a second high-voltage PMOS transistor and a third high-voltage PMOS transistor; the source of the first high-voltage PMOS transistor is connected to the gate of the second high-voltage PMOS transistor and the gate of the third high-voltage PMOS transistor; the drain of the small-size PMOS transistor is connected to the source of the second high-voltage PMOS transistor, and the drain of the second high-voltage PMOS transistor is grounded through a third resistor; the drain of the second current mirror PMOS transistor is connected to the source of the third high-voltage PMOS transistor, and the drain of the third high-voltage PMOS transistor is grounded through a fourth resistor.
[0011] According to the above technical solution, the input stage of the error amplifier circuit includes a first PNP transistor and a second PNP transistor. The bases of both the first and second PNP transistors are connected to a bias voltage. The emitter of the first PNP transistor is connected to the lower end of the first resistor, and the emitter of the second PNP transistor is connected to the lower end of the second resistor.
[0012] According to the above technical solution, the error amplifier circuit further includes a first PMOS transistor and a second PMOS transistor. The gates of both the first PMOS transistor and the second PMOS transistor are connected to a common gate bias voltage. The source of the first PMOS transistor is connected to the collector of the first PNP transistor, and the source of the second PMOS transistor is connected to the collector of the second PNP transistor.
[0013] According to the above technical solution, the error amplifier circuit further includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are both connected to a common gate bias voltage; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gates of the third NMOS transistor and the fourth NMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor.
[0014] According to the above technical solution, the source of the third NMOS transistor and the source of the fourth NMOS transistor serve as the ground terminal of the error amplifier circuit, and are jointly connected to the source of the first high-voltage PMOS transistor and the positive terminal of the second diode.
[0015] According to the above technical solution, the common connection point between the drain of the second PMOS transistor and the drain of the second NMOS transistor serves as the output terminal of the error amplifier circuit and is connected to the gate of the small-sized PMOS transistor.
[0016] According to the above technical solution, the transistor type in the isolation module is replaced with an NMOS transistor according to the system configuration; and / or, the first high-voltage PMOS transistor in the voltage clamping module is replaced with a high-voltage NMOS transistor.
[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention constructs a low-voltage power rail (using a 5V power rail) through a voltage clamping module, avoiding the use of a high-voltage LDMOS transistor in the error amplifier circuit, thereby significantly reducing the parasitic capacitance of the PN junction at the op-amp output node caused by the drain of the high-voltage transistor. This invention uses a separate small-size PMOS transistor (MFB) to isolate the op-amp output node from the large-size current mirror transistor, so that the capacitance contribution of the op-amp output node is mainly transformed into the extremely small gate-source parasitic capacitance of the small-size transistor, effectively avoiding the problem of excessive load parasitic capacitance caused by the large-size current mirror transistor. Achieving high-speed, high-bandwidth sampling: Through the above-mentioned dual-capacitance isolation mechanism at the voltage domain and load end, this invention significantly reduces the equivalent output capacitance at node OUT_G, effectively improving the loop main pole frequency and unity-gain bandwidth of the circuit, ultimately achieving the design requirements of a high-speed, high-bandwidth high-side current sampling circuit. Attached Figure Description
[0018] Figure 1 This is one of the typical high-side current sampling circuits; Figure 2 This is a typical high-side current sampling circuit. Figure 3 This is a circuit diagram of the sampling circuit of this utility model; Figure 4 This is another embodiment of the sampling circuit of this utility model; Figure 5 This is another embodiment of the sampling circuit of this utility model. Detailed Implementation
[0019] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0020] Wherein, DIO1 is the first diode, DIO2 is the second diode, RCS is the sampling resistor, R1 is the first resistor, R2 is the second resistor, R3 is the third resistor, R4 is the fourth resistor, MFB is the small-size PMOS transistor, Mcm1 is the first current mirror PMOS transistor, Mcm2 is the second current mirror PMOS transistor, HVMOS1 is the first high-voltage PMOS transistor, HVMOS2 is the second high-voltage PMOS transistor, HVMOS3 is the third high-voltage PMOS transistor, Q1 is the first PNP transistor, Q2 is the second PNP transistor, MP1 is the first PMOS transistor, MP2 is the second PMOS transistor, MN1 is the first NMOS transistor, MN2 is the second NMOS transistor, MN3 is the third NMOS transistor, MN4 is the fourth NMOS transistor, and IS is the current bias.
[0021] Example 1: In one specific implementation, such as Figure 3As shown, this utility model provides a high-side current sampling circuit. The circuit includes: the anode of a first diode is connected to the gate of a first high-voltage PMOS transistor and a current bias, the current bias being used to generate a voltage of VIN-5.5V across the first diode, and the other end of the current bias is grounded; its cathode is connected to the power supply VIN, the cathode of a second diode, the upper end of a sampling resistor, and the upper end of a first resistor. The anode of the second diode is connected to the source of the first high-voltage PMOS transistor, the source of a third NMOS transistor, the source of a fourth NMOS transistor, the gate of the second high-voltage PMOS transistor, and the gate of the third high-voltage PMOS transistor. Further, the lower end of the sampling resistor is connected to the upper end of a second resistor. The lower end of the first resistor is connected to the emitter of a first PNP transistor, the source of a first current-mirror PMOS transistor, and the source of a second current-mirror PMOS transistor. The lower end of the second resistor is connected to the emitter of a second PNP transistor. The upper end of the third resistor is connected to the drain of the second high-voltage PMOS transistor, and its lower end is grounded; the upper end of the fourth resistor is connected to the drain of the third high-voltage PMOS transistor, and its lower end is grounded.
[0022] In one specific implementation, regarding the connection relationship between the isolation module and the current mirror module: the gate of the small-sized PMOS transistor is connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor; its source is connected to the gate and drain of the first current mirror PMOS transistor and the gate of the second current mirror PMOS transistor; and its drain is connected to the source of the second high-voltage PMOS transistor. The source of the first current mirror PMOS transistor is connected to the lower end of the first resistor, the emitter of the first PNP transistor, and the source of the second current mirror PMOS transistor. The drain of the second current mirror PMOS transistor is connected to the source of the third high-voltage PMOS transistor.
[0023] Specifically, the small-size PMOS transistor is a PMOS transistor with a length of 0.5um and a width of 2um.
[0024] Furthermore, regarding the connection relationships of the high-voltage protection structure: the drain of the first high-voltage PMOS transistor is grounded. The gate of the second high-voltage PMOS transistor is connected to the positive terminal of the second diode, the source of the third NMOS transistor, the source of the fourth NMOS transistor, the source of the first high-voltage PMOS transistor, and the gate of the third high-voltage PMOS transistor. Its source is connected to the drain of the small-size PMOS transistor, and its drain is connected to the upper end of the third resistor. The source of the third high-voltage PMOS transistor is connected to the drain of the second current mirror PMOS transistor, and its drain is connected to the upper end of the fourth resistor.
[0025] Preferably, regarding the internal connection relationship of the error amplifier circuit: the base of the first PNP transistor is connected to VBP (VBP is the base bias voltage of the PNP transistor), and its collector is connected to the source of the first PMOS transistor; the base of the second PNP transistor is connected to VBP, its emitter is connected to the lower end of the second resistor, and its collector is connected to the source of the second PMOS transistor. The gate of the first PMOS transistor is connected to VBPC (VBPC is the common gate bias voltage of the PMOS transistor), and its drain is connected to the drain of the first NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor. The gate of the second PMOS transistor is connected to VBPC, its source is connected to the collector of the second PNP transistor, and its drain is connected to the drain of the second NMOS transistor and the gate of the small-size PMOS transistor. The gate of the first NMOS transistor is connected to VBNC (VBNC is the common gate bias voltage of the NMOS transistor), and its source is connected to the drain of the third NMOS transistor. The gate of the second NMOS transistor is connected to VBNC, and its source is connected to the drain of the fourth NMOS transistor. The drain of the third NMOS transistor is connected to the source of the first NMOS transistor; the drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor.
[0026] Specifically, the working principle of this utility model is as follows: Based on the structure of the high-side current sampling circuit described above, the system can maintain a sampling relationship consistent with that of conventional circuits: VSNS1=1 / 2 (R3 / R2) IL RCS.
[0027] In this circuit, VSNS1 is the voltage signal, R3 is the third resistor, R2 is the second resistor, IL is the sampling current, and RCS is the sampling resistor. The high-side current sampling circuit of this invention maintains the same function as the traditional circuit. To overcome the drawback of excessive parasitic capacitance and achieve high-speed, high-bandwidth sampling, this invention adds a new power rail to the circuit, from power supply VIN to HV_GND, where the voltage of HV_GND is preferably configured as VIN minus 5V. In one specific embodiment, using this 5V power rail effectively avoids the use of a high-voltage LDMOS transistor, thereby significantly reducing the parasitic capacitance of the operational amplifier output node.
[0028] Furthermore, this invention uses a separate small-sized PMOS transistor to effectively isolate the op-amp output node from the current mirror transistors (Mcm1, Mcm2). Through this isolation structure, the main capacitive contribution of the op-amp output node is transformed into the gate-source parasitic capacitance of the small-sized PMOS transistor, which is much smaller than the gate-source parasitic capacitance of the large-sized current mirror transistor in conventional designs. With the architecture of this invention, the main pole and unity-gain bandwidth of the high-side current sampling circuit are as follows: Wp=1 / (ROUT COUT); GBW [gmfb R1 / (1+(gmfb / gm))] GM / (2 π COUT); In the formula, R1 is the first resistor, Wp is the pole location, GBW is the loop bandwidth, ROUT and COUT are the equivalent output impedance and equivalent output capacitance of the error amplifier circuit, respectively, gmfb is the equivalent transconductance of the small-size PMOS transistor, gm is the equivalent transconductance of the first current mirror PMOS transistor Mcm1, and GM is the equivalent transconductance of the error amplifier circuit. Since the op-amp uses a power rail from VIN to HV_GND, the PN junction capacitance at node OUT_G is significantly reduced. Simultaneously, the parasitic capacitance of the small-size PMOS transistor is extremely small, so COUT is mainly composed of the CGS capacitance of the small-size PMOS transistor (CGS is the gate-source parasitic capacitance), the CGD capacitance of MN2 and the second PMOS transistor (CGD is the gate-drain parasitic capacitance). Preferably, all three MOS transistors are of minimum size, minimizing COUT and thus significantly increasing the unity-gain bandwidth of this invention compared to traditional structures.
[0029] In one specific implementation, the loop gain Av of this circuit is expressed as: Av = [gmfb] R1 / (1+(gmfb / gm))] GM ROUT. Specifically, when the circuit parameters are configured as Av=68dB, ROUT=100MΩ, and COUT=66fF, a unity-gain bandwidth GBW=60MHz can be obtained, thus successfully achieving the goal of high-speed, high-bandwidth sampling.
[0030] Furthermore, those skilled in the art will understand that, based on various implementation methods of the current sampling circuit, the technical solution of this utility model is not limited to the specific structure described above. Other alternative implementation methods include: Figure 4 and Figure 5 As shown, the small-sized PMOS transistor in the isolation module can also be replaced with an NMOS transistor, and the corresponding high-voltage transistor can be replaced with a high-voltage NMOS transistor. Meanwhile, the current mirror module can use either a common-source, common-gate structure or not, depending on the actual system accuracy and margin requirements. All the above equivalent substitutions or modifications fall within the protection scope of this utility model.
[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0032] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. A high-side high-voltage current high-speed sampling circuit, characterized in that: include: Voltage clamping module, error amplifier circuit, isolation module, and current mirror module; The voltage clamping module includes a first diode, a second diode, and a first high-voltage PMOS transistor. The cathode of the first diode is connected to the power supply VIN, and its anode is connected to the gate of the first high-voltage PMOS transistor. The drain of the first high-voltage PMOS transistor is grounded, and its source is connected to the anode of the second diode and the ground terminal of the error amplifier circuit, so as to construct a low-voltage power rail between the power supply VIN and the error amplifier circuit. The isolation module includes a small-sized PMOS transistor. The gate of the small-sized PMOS transistor is connected to the output terminal of the error amplifier circuit, its source is connected to the current mirror module, and its drain is grounded through a high-voltage device. The small-sized PMOS transistor isolates the parasitic capacitance between the output terminal of the error amplifier circuit and the current mirror module.
2. The high-side high-voltage current high-speed sampling circuit according to claim 1, characterized in that: It also includes a sampling resistor, a first resistor, and a second resistor; the upper end of the sampling resistor is connected to the upper end of the first resistor, the power supply VIN, the cathode of the first diode, and the cathode of the second diode, and the lower end of the sampling resistor is connected to the upper end of the second resistor; the lower ends of the first resistor and the lower ends of the second resistor are respectively connected to the two input terminals of the error amplifier circuit.
3. The high-side high-voltage current high-speed sampling circuit according to claim 2, characterized in that: The current mirror module includes a first current mirror PMOS transistor and a second current mirror PMOS transistor; the source of the small-sized PMOS transistor is connected to the gate of the first current mirror PMOS transistor and the gate of the second current mirror PMOS transistor; the source of the first current mirror PMOS transistor and the source of the second current mirror PMOS transistor are both connected to the lower end of the first resistor.
4. The high-side high-voltage current high-speed sampling circuit according to claim 3, characterized in that: The high-voltage device includes a second high-voltage PMOS transistor and a third high-voltage PMOS transistor; the source of the first high-voltage PMOS transistor is connected to the gate of the second high-voltage PMOS transistor and the gate of the third high-voltage PMOS transistor; the drain of the small-sized PMOS transistor is connected to the source of the second high-voltage PMOS transistor, and the drain of the second high-voltage PMOS transistor is grounded through a third resistor; the drain of the second current mirror PMOS transistor is connected to the source of the third high-voltage PMOS transistor, and the drain of the third high-voltage PMOS transistor is grounded through a fourth resistor.
5. The high-side high-voltage current high-speed sampling circuit according to claim 2, characterized in that: The input stage of the error amplifier circuit includes a first PNP transistor and a second PNP transistor. The bases of both the first and second PNP transistors are connected to a bias voltage. The emitter of the first PNP transistor is connected to the lower end of the first resistor, and the emitter of the second PNP transistor is connected to the lower end of the second resistor.
6. The high-side high-voltage current high-speed sampling circuit according to claim 5, characterized in that: The error amplifier circuit further includes a first PMOS transistor and a second PMOS transistor. The gates of both the first PMOS transistor and the second PMOS transistor are connected to a common gate bias voltage. The source of the first PMOS transistor is connected to the collector of the first PNP transistor, and the source of the second PMOS transistor is connected to the collector of the second PNP transistor.
7. The high-side high-voltage current high-speed sampling circuit according to claim 6, characterized in that: The error amplifier circuit further includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are both connected to a common gate bias voltage; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gates of the third NMOS transistor and the fourth NMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor.
8. The high-side high-voltage current high-speed sampling circuit according to claim 7, characterized in that: The sources of the third and fourth NMOS transistors serve as the ground terminals of the error amplifier circuit, and are connected together to the source of the first high-voltage PMOS transistor and the positive terminal of the second diode.
9. The high-side high-voltage current high-speed sampling circuit according to claim 7, characterized in that: The common connection point between the drain of the second PMOS transistor and the drain of the second NMOS transistor serves as the output terminal of the error amplifier circuit and is connected to the gate of the small-sized PMOS transistor.
10. The high-side high-voltage current high-speed sampling circuit according to claim 1, characterized in that: The transistor type in the isolation module is replaced with an NMOS transistor according to the system configuration; and / or, the first high-voltage PMOS transistor in the voltage clamping module is replaced with a high-voltage NMOS transistor.