A detection circuit, a detection device and an electronic device

Abstract

The present specification provides a detection circuit, a detection device and an electronic equipment. The detection circuit comprises: a first transistor, comprising a control electrode connected to a first control voltage, a first electrode connected to the control electrode of a third transistor and connected to a second control voltage, and a second electrode connected to ground; the third transistor comprises a control electrode connected to the first electrode of the first transistor and the second control voltage, a first electrode connected to the third control voltage, and a second electrode connected to the current inflow end of a unidirectional conduction element; the unidirectional conduction element comprises a current inflow end connected to the second electrode of the third transistor and a current outflow end connected to a to-be-detected plane; and a detection module. Through the technical scheme of the present specification, the monitoring blind area before the power-on of the server can be covered at low cost and reliably.

Description

Technical Field

[0001] This specification relates to a detection circuit, a detection device including the circuit, and an electronic device. Background Technology

[0002] As modern servers increasingly demand higher standards for thermal management, remote wake-up, and hibernation control, the Fake S5 power supply solution has become the industry mainstream due to its high efficiency and energy saving. The Fake S5 solution uses a single 12V main power supply for the entire system; however, before the 12V main power is applied, the system management chip lacks power and cannot perform monitoring functions, creating a critical monitoring blind spot.

[0003] If you want to use other power supplies for early monitoring, you need to add a logic chip, power it with another power supply, and control the start of the monitoring. However, introducing a logic chip increases the complexity of the board and the material cost, and also requires writing, debugging, and maintaining code. Summary of the Invention

[0004] In view of this, this specification provides a detection circuit and an apparatus and electronic device including the circuit to improve the problem of blind spots in server monitoring before the aforementioned system chip is powered on.

[0005] Specifically, the circuit is as follows:

[0006] The first transistor Q1 includes a control electrode connected to a first control voltage V1, a first electrode connected to the control electrode of the third transistor and connected to a second control voltage V2, and a second electrode grounded; used to switch the switching state according to the first control voltage; the third transistor Q3 includes a control electrode connected to the first electrode of the first transistor and the second control voltage, a first electrode connected to the third control voltage V3, and a second electrode connected to the current inflow terminal of the unidirectional conducting element D1; used to switch the switching state according to the switching state of the first transistor, and used to conduct the circuit from the first electrode of the third transistor to the unidirectional conducting element when in the conducting state; the unidirectional conducting element includes a current inflow terminal connected to the second electrode of the third transistor and a current outflow terminal connected to the plane under test; used to conduct the circuit from the third transistor to the plane under test in a unidirectional manner; a detection module is used to detect the voltage between the current outflow terminal of the unidirectional conducting element and the plane under test;

[0007] The first control voltage, the second control voltage, and the third control voltage are obtained by converting the operating voltage, and their timing lags behind the operating voltage, which is used to support the operation of the detection module.

[0008] Furthermore, the first transistor is an NMOS transistor, the second electrode is the source, the source is grounded, the control electrode is the gate, the gate is connected to a first control voltage, the first electrode is the drain, the drain is connected to the gate of the third transistor and connected to the first control voltage; the second transistor is a PMOS transistor, the control electrode is the gate, the gate is connected to the first electrode of the first transistor and connected to a second control voltage, the first electrode is the drain, the drain is connected to a third control voltage, the second electrode is the source, the source is connected to the current inflow terminal of a unidirectional conducting device; when the first transistor is off, the third transistor is on; the unidirectional conducting device is a diode, its current inflow terminal is the anode, the anode is connected to the source of the third transistor, its current outflow terminal is the cathode, the cathode is connected to the plane to be measured, and the cathode is also connected to a detection module.

[0009] Furthermore, a ninth load (R9) is connected between the control electrode of the third transistor and the first control voltage; a first load (R1) is connected between the second electrode of the third transistor and the unidirectional conducting element.

[0010] Furthermore, the second transistor Q2 includes a control electrode connected to the plane under test, a first electrode connected to the first operating voltage V5 and connected to the control electrode of the fourth transistor, and a grounded second electrode; it is used to switch the switching state according to the voltage of the plane under test; the fourth transistor Q4 includes a control electrode connected to the first electrode of the second transistor, a grounded second electrode, and a first electrode connected to the fourth control voltage V4; it is used to switch the switching state according to the voltage of the first electrode of the second transistor; the fifth transistor Q5 includes a control electrode connected to the first electrode of the fourth transistor, a first electrode connected to the second operating voltage V6 and connected to the output terminal, and a grounded second electrode; it is used to switch the switching state according to the voltage of the first electrode of the fourth transistor; the output terminal is used to output the detection result of the detection module detecting the plane under test.

[0011] Furthermore, the second transistor is an NMOS transistor, with the gate as the control electrode, connected to the plane under test, the first electrode as the drain, connected to the first operating voltage and connected to the gate of the fourth transistor, and the second electrode as the source, which is grounded; the fourth transistor is an NMOS transistor, with the gate as the control electrode, connected to the first electrode of the second transistor, the second electrode as the source, which is grounded, the first electrode as the drain, which is connected to the fourth control voltage; the fifth transistor is an NMOS transistor, with the gate as the control electrode, connected to the first electrode of the fourth transistor, the first electrode as the drain, connected to the second operating voltage and connected to the output terminal, and the second electrode as the source, which is grounded.

[0012] Furthermore, a tenth load R10 is connected between the first electrode of the second transistor and the control electrode of the fourth transistor; a third load R3 is connected between the first electrode of the fourth transistor and the fourth control voltage.

[0013] Furthermore, an eleventh load R11 is connected between the first electrode of the second transistor and the second electrode of the second transistor; a fifth load R5 is connected between the first electrode of the fifth transistor and the second electrode.

[0014] Furthermore, the output terminal is connected to a latching module, which includes: a sixth transistor Q6, including a second electrode connected to the first electrode of the fifth transistor, a control electrode connected to the second electrode of the seventh transistor, and a first electrode grounded; and a seventh transistor Q7, including a control electrode connected to the second electrode of the sixth transistor, a second electrode connected to the control electrode of the sixth transistor, and a first electrode connected to the third operating voltage V7.

[0015] Furthermore, the sixth transistor is an NMOS transistor, with the second electrode being the source, which is connected to the drain of the fifth transistor. The control electrode is the gate, which is connected to the second electrode of the seventh transistor. The first electrode is the drain, which is grounded. The seventh transistor is a PMOS transistor, with the control electrode being the gate, which is connected to the second electrode of the sixth transistor. The second electrode is the source, which is connected to the control electrode of the sixth transistor. The first electrode is the drain, which is connected to the third operating voltage.

[0016] Furthermore, an eighth load R8 is connected between the first electrode of the sixth transistor and ground; a seventh load R7 is connected between the first electrode of the seventh transistor and ground.

[0017] Furthermore, the second transistor has a second load R2 between its first electrode and the first operating voltage to prevent the fifth transistor from being mis-energized; the fourth transistor has a fourth load R4 between its first electrode and the second operating voltage to prevent the seventh transistor from being mis-energized.

[0018] Furthermore, in response to the event of the output detection result, a delay voltage V8 is applied to the control electrode of the fourth transistor to fix the operating state of the fourth transistor; there is a time interval between the application of the delay voltage and the event of the output detection result.

[0019] This specification also provides an apparatus including the detection circuit, comprising any of the detection circuits described above; a detection terminal for electrically connecting the detection circuit to the plane under test; and a power supply module for providing control voltage and / or operating voltage to the detection circuit.

[0020] This specification also provides an electronic device, including any of the detection circuits described above; a plane to be tested, for being detected by the detection circuit, so as to realize the application of the aforementioned detection circuit.

[0021] The technical solutions provided in this specification offer at least the following beneficial effects:

[0022] The technical solution described in this manual provides a low-cost and reliable solution to cover the monitoring blind spots before the server is powered on. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments of this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings of the embodiments of this specification.

[0024] Figure 1 This is a circuit diagram of one embodiment of this specification;

[0025] Figure 2 This is a circuit diagram of another embodiment of this specification;

[0026] Figure 3 This is a circuit diagram of another embodiment of this specification;

[0027] Figure 4 This is a schematic diagram of the circuit module structure in one embodiment of this specification;

[0028] Figure 5 This is a schematic diagram of a device module structure including the circuit in one embodiment of this specification;

[0029] Figure 6 This is a schematic diagram of an electronic device module containing the circuit in one embodiment of this specification. Detailed Implementation

[0030] The terminology used in the embodiments described herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The singular forms “a,” “described,” and “the” as used in this specification and claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to any and all possible combinations comprising one or more of the associated listed items.

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0032] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" may also be interpreted as "when," "when," or "in response to a determination."

[0033] Under the Fake S5 power supply scheme, the system management chip cannot perform monitoring functions due to lack of power, creating a critical monitoring blind spot. If alternative power supplies are desired for early monitoring, a logic chip needs to be added, powered by an alternative power source to control the monitoring process. However, introducing a logic chip increases board complexity and material costs, and also incurs maintenance costs associated with writing and debugging code.

[0034] If monitoring before power-on can be implemented purely through hardware, the problem of monitoring blind spots can be solved in a highly reliable manner.

[0035] In view of this, this specification provides a detection circuit and an apparatus and electronic device including the circuit to improve the problem of blind spots in server monitoring before the aforementioned system chip is powered on.

[0036] Specifically, the circuit is described later.

[0037] The first transistor Q1 includes a control electrode connected to a first control voltage V1, a first electrode connected to the control electrode of the third transistor and connected to a second control voltage V2, and a second electrode grounded; used to switch the switching state according to the first control voltage.

[0038] The third transistor Q3 includes a control electrode connected to the first electrode of the first transistor and the second control voltage, a first electrode connected to the third control voltage V3, and a second electrode connected to the current inflow terminal of the unidirectional conducting element D1; it is used to switch the switching state according to the switching state of the first transistor, and to conduct the circuit from the first electrode of the third transistor to the unidirectional conducting element when the transistor is in the conducting state.

[0039] A unidirectional conducting element includes a current inflow terminal connected to the second electrode of a third transistor and a current outflow terminal connected to the plane under test; used for unidirectional conduction of a circuit from the third transistor to the plane under test;

[0040] The detection module is used to detect the voltage between the current outlet of the unidirectional conducting element and the plane under test;

[0041] The first control voltage, the second control voltage, and the third control voltage are obtained by converting the operating voltage, and their timing lags behind the operating voltage, which is used to support the operation of the detection module.

[0042] The values ​​of the first, second, and third control voltages can be the same, partially the same, or different. Simultaneously, the sources of the first, second, and third control voltages can also be the same, partially the same, or different. The first and second control voltages should meet the operating requirements of the transistor, and the third control voltage should meet the requirement of supplying a clearly observable voltage to the plane under test after passing through the unidirectional conducting element and the voltage drop of the load in the circuit.

[0043] In one embodiment, if the first transistor and the third transistor are MOSFETs, then the first control voltage and the second control voltage should satisfy the requirement that their values ​​enable the first transistor and the third transistor to be turned on and off under different circuit states.

[0044] In one embodiment, if the device directly connected to the plane under test in the detection module is a MOSFET, then the third control voltage should be sufficient to enable the MOSFET directly connected to the plane under test in the detection module to be turned on and off after passing through the unidirectional conducting element and the voltage drop of the load in the circuit.

[0045] In one embodiment, such as Figure 1 The first transistor is an NMOS transistor, with the second electrode being the source, grounded, and the control electrode being the gate, which is connected to a first control voltage. The first electrode is the drain, which is connected to the gate of the third transistor and also connected to the first control voltage. The second transistor is a PMOS transistor, with the control electrode being the gate, which is connected to the first electrode of the first transistor and connected to a second control voltage. The first electrode is the drain, which is connected to a third control voltage. The second electrode is the source, which is connected to the current inflow terminal of a unidirectional conducting element. When the first transistor is off, the third transistor is on. The unidirectional conducting element is a diode, with its current inflow terminal being the anode, which is connected to the source of the third transistor. Its current outflow terminal is the cathode, which is connected to the plane under test and also connected to a detection module.

[0046] In one embodiment, by adjusting the voltage input position and circuit connection, the same effect of controlling the injection of a third control voltage (or a voltage whose value satisfies the same conditions as the third control voltage) into a unidirectional conducting element can be achieved when the first transistor is a PMOS transistor and the third transistor is an NMOS transistor. That is, this part of the circuit can utilize the switching characteristics determined by the threshold voltage of the transistor to inject the third control voltage (or a voltage whose value satisfies the same conditions as the third control voltage) into the unidirectional conducting element.

[0047] In one embodiment, the circuit of the above embodiment further includes a ninth load R9 connected between the control electrode of the third transistor and the first control voltage; and a first load R1 connected between the second electrode of the third transistor and the unidirectional conducting element.

[0048] In one embodiment, the detection module includes: a second transistor Q2, comprising a control electrode connected to the plane under test, a first electrode connected to a first operating voltage V5 and connected to a control electrode of a fourth transistor, and a grounded second electrode; used to switch a switching state according to the voltage of the plane under test; a fourth transistor Q4, comprising a control electrode connected to the first electrode of the second transistor, a grounded second electrode, and a first electrode connected to a fourth control voltage V4; used to switch a switching state according to the voltage of the first electrode of the second transistor; a fifth transistor Q5, comprising a control electrode connected to the first electrode of the fourth transistor, a first electrode connected to a second operating voltage V6 and connected to an output terminal, and a grounded second electrode; used to switch a switching state according to the voltage of the first electrode of the fourth transistor; and an output terminal for outputting the detection result of the detection module detecting the plane under test.

[0049] In one embodiment, such as Figure 2 The second transistor is an NMOS transistor, with the gate as the control electrode, connected to the plane under test. The first electrode is the drain, connected to the first operating voltage and connected to the gate of the fourth transistor. The second electrode is the source, grounded. The fourth transistor is an NMOS transistor, with the gate as the control electrode, connected to the first electrode of the second transistor. The second electrode is the source, grounded. The first electrode is the drain, connected to the fourth control voltage. The fifth transistor is an NMOS transistor, with the gate as the control electrode, connected to the first electrode of the fourth transistor. The first electrode is the drain, connected to the second operating voltage and connected to the output terminal. The second electrode is the source, grounded.

[0050] In one embodiment, a tenth load R10 is connected between the first electrode of the second transistor and the control electrode of the fourth transistor; a third load R3 is connected between the first electrode of the fourth transistor and the fourth control voltage.

[0051] In one embodiment, an eleventh load R11 is connected between the first electrode of the second transistor and the second electrode of the second transistor; a fifth load R5 is connected between the first electrode of the fifth transistor and the second electrode.

[0052] In one embodiment, the detection module can use an existing module or device with voltage detection function to detect the voltage of the plane to be tested.

[0053] In one embodiment, the output of the detection module implemented purely in hardware in the above embodiment is also connected to a latch module.

[0054] In one embodiment, the latching module includes: a sixth transistor Q6, including a second electrode connected to the first electrode of the fifth transistor, a control electrode connected to the second electrode of the seventh transistor, and a first electrode grounded; and a seventh transistor Q7, including a control electrode connected to the second electrode of the sixth transistor, a second electrode connected to the control electrode of the sixth transistor, and a first electrode connected to a third operating voltage V7.

[0055] For example, the sixth transistor is an NMOS transistor, with the second electrode being the source, which is connected to the drain of the fifth transistor. The control electrode is the gate, which is connected to the second electrode of the seventh transistor. The first electrode is the drain, which is grounded. The seventh transistor is a PMOS transistor, with the control electrode being the gate, which is connected to the second electrode of the sixth transistor. The second electrode is the source, which is connected to the control electrode of the sixth transistor. The first electrode is the drain, which is connected to the third operating voltage.

[0056] In one embodiment, an eighth load R8 is connected between the first electrode of the sixth transistor and ground; a seventh load R7 is connected between the first electrode of the seventh transistor and ground.

[0057] In one embodiment, the second transistor has a second load R2 between its first electrode and the first operating voltage to prevent the fifth transistor from being mis-energized; and the fourth transistor has a fourth load R4 between its first electrode and the second operating voltage to prevent the seventh transistor from being mis-energized.

[0058] In the above embodiments, the values ​​of the first operating voltage, the second operating voltage, and the third operating voltage can be the same, partially the same, or different. Simultaneously, the sources of the first operating voltage, the second operating voltage, and the third operating voltage can also be the same, partially the same, or different. The values ​​of the first operating voltage, the second operating voltage, and the third operating voltage should satisfy the requirement that the transistor located after the second transistor in the circuit topology has both on and off operating states, corresponding to the on and off states of the second transistor according to the specific circuit connection. The values ​​and sources of the fourth control voltage and the first, second, and third control voltages can be the same, partially the same, or different. The value of the fourth control voltage should satisfy the requirement that the transistor located after the fourth transistor in the circuit topology has both on and off operating states, corresponding to the on and off states of the fourth transistor according to the specific circuit connection.

[0059] In one embodiment, the latch module can be any latch circuit or device capable of implementing the latching function, such as an SR latch, a D latch, etc., and the topological position of the output result is determined according to the specific latch circuit to obtain the latched detection result.

[0060] In one embodiment, in response to an event in which a detection result is output at the output terminal, a delay voltage V8 is applied to the control electrode of the fourth transistor to fix the operating state of the fourth transistor; the application of the delay voltage is timed from the event in which the detection result is output at the output terminal.

[0061] The value and source of the delay voltage can be the same as, partially the same as, or different from, the first, second, third, and fourth control voltages. It can also be obtained from any control voltage via a delay output. The delay voltage value should ensure that the transistor located after the fourth transistor in the circuit topology has both on and off states, corresponding to the on and off states of the fourth transistor according to the specific circuit connection. Simultaneously, the delay time must ensure that a recordable and stable detection result is obtained when the power-on effect occurs.

[0062] In one embodiment, the delayed voltage can be applied at any topological location before the latch module or the output result, where the subsequent circuit state or output result can be fixed, to terminate or shut down the circuit detection function. The delay time of the delayed voltage should be sufficient to obtain and record a stable detection result, to prevent the delayed voltage from affecting the accuracy of the output result.

[0063] In this scheme, the voltage connected to the electrodes of the device is the voltage applied to the corresponding electrodes of the device, and the voltage value is a preset variable. That is, connecting a certain voltage or applying a certain voltage does not indicate that a voltage with a specific value has been injected into the device; it only indicates that a path for voltage to be injected at any time has been connected, and does not indicate that the device is in a powered-on state.

[0064] The complete working mechanism of this detection circuit is explained below through a specific circuit example.

[0065] like Figure 3 Taking transistors Q1, Q2, Q4, Q5, and Q6 as NMOS transistors, and Q3 and Q7 as PMOS transistors, and connected to loads R1 to R11, the circuit is as follows: The first to fourth control voltages are all 3.3V auxiliary voltages obtained by converting the 12V operating voltage; the 12V operating voltage is called the 12V auxiliary voltage. The operating voltage of the plane under test after power-on is the 12V main voltage, called the main power plane (12V main power plane). According to the above circuit structure, the delay voltage is the delayed 3V auxiliary voltage output after the 3V auxiliary voltage passes through the delay output unit. The complete circuit operation mechanism is as follows:

[0066] Taking the detection of a short circuit in the 12V main power plane as an example, before the 12V main power plane is powered on, a 12V voltage is applied to the drain of Q2 or the pull-up resistor R2 connected to the drain of Q2, the drain of Q5 or the pull-up resistor R4 connected to the drain of Q5, and the pull-up resistor R6 connected to the drain of Q7. A 3V3 auxiliary power is applied to the gate of Q1, the drain of Q3, and the side of R9 not connected to Q1 or Q3. Since the 3V3 auxiliary power is obtained by converting the 12V voltage, it lags slightly behind the 12V voltage in timing. Because this occurs before the 12V main plane is powered on, the main plane voltage should be 0V at this time.

[0067] After the 3V3 auxiliary power supply is applied, the Vgs (voltage difference between the gate and drain) of Q1 is approximately 3.3V, which is greater than the threshold voltage of a typical low-voltage NMOS transistor. According to the operating characteristics of NMOS transistors, Q1 turns on, pulling up the gate voltage of Q3 and causing Q3 to also turn on. Because the drain of Q3 is connected to the 3V3 auxiliary power supply, the conduction of Q3 injects 3.3V into subsequent circuitry.

[0068] At this time, if the main electrical plane is normal (not short-circuited), taking ordinary silicon and germanium diodes as examples, the forward voltage drop of a silicon diode is about 0.6V to 0.7V, and the forward voltage drop of a germanium diode is about 0.2V to 0.3V. Then, the 3.3V voltage drops to about 2.6V to 3V after passing through D1 (subtracting the forward voltage drop of the diode), that is, the voltage of the main electrical plane is about 2.6V to 3V.

[0069] If the main power plane is short-circuited, the 3.3V voltage will be grounded, meaning the main power plane voltage will be grounded (the main power plane voltage will be 0).

[0070] When the main electrical plane is not short-circuited, the voltage difference between the gate and drain of Q2 is approximately 2.6V to 3V, and Q2 is turned on. The drain voltage of Q2 is pulled down to be close to the source voltage of Q2. The gate voltage of Q4 is correspondingly pulled down, and Q4 is turned off. The drain voltage of Q4 is raised by the 3V3 auxiliary current, which simultaneously raises the gate voltage of Q5, and Q5 is turned on. The drain voltage of Q5 is pulled down, which simultaneously pulls down the gate voltage of Q7, and Q7 is turned on. The drain voltage of Q7 is raised by the 12V auxiliary current, and the source voltage is correspondingly raised. At this time, the detection point voltage is the voltage division value of R8 when R8 and Q6 are connected in series under the gate voltage of Q7, the actual value is approximately 3 to 4V (depending on the specific device parameters), that is, there is a clear voltage result, which is recorded as an output of 1. The detection point voltage raises the gate voltage of Q6, Q6 is turned on, and lowers the gate voltage of Q7, Q7 is turned off, and the result is latched.

[0071] When the main electrical plane is short-circuited, Q2 is off because its gate voltage is 0. The drain voltage of Q2 is raised by the 3V3 auxiliary current, which in turn raises the gate voltage of Q4, causing Q4 to conduct. The conduction of Q4 pulls its drain voltage down to near its source voltage, simultaneously lowering the gate voltage of Q5, causing Q5 to turn off. The drain voltage of Q5 is then raised by the 3V3 auxiliary current, simultaneously raising the gate voltage of Q7, causing Q7 to turn off. The 12V auxiliary current cannot raise the source voltage of Q7. At this point, the voltage at the detection point is approximately grounded, and the output is recorded as 0. The voltage at the detection point then lowers the gate voltage of Q6, causing Q6 to turn off, and the latched result is recorded.

[0072] That is, when the plane under test is not short-circuited, the corresponding output result is 1; when the plane under test is short-circuited, the corresponding output result is 0.

[0073] After a certain period of time (e.g., 1 second), a delayed 3V3 auxiliary power is applied to the gate of Q4, forcibly pulling up the gate voltage of Q4, and Q4 turns on. At this time, whether the plane under test is short-circuited or not no longer affects the output result of the subsequent circuit, that is, the detection process is terminated.

[0074] In the example, if the plane under test is found to be free of short circuit (output result is 1), the test is considered complete and no short circuit is confirmed, and it can be powered on and operated normally.

[0075] In one embodiment, a schematic diagram of a complete circuit module structure including a switching module 401 (using the circuitry of this solution to allow voltage injection into the plane under test 402), the plane under test 402, a detection module 403, a latching module 404, an output module 405, and a detection function shutdown module 406 is shown below. Figure 4 As shown.

[0076] The circuit provided in this manual is a pure hardware circuit that covers the monitoring blind spot before the plane under test is powered on, offering advantages such as low cost and high reliability. In practical applications, it can be flexibly combined with power supplies, other external circuits, modules, or devices, making it highly adaptable.

[0077] As one example, the test plane of the circuit provided in this specification includes, but is not limited to, the power plane of a switch; other power planes can also be used. Furthermore, the circuit provided in this specification can also be applied to other detection methods, such as leakage detection, floating ground detection, and open circuit detection.

[0078] This specification also provides an apparatus whose circuit structure is the same as or similar to that of the embodiments described above. The circuit structure can be used as a module or as part of a module in the apparatus, and the module can be supplied to independent devices for specific applications. A schematic diagram of a module structure of the detection device 508 module provided in this specification is shown below. Figure 5As shown, the system includes a power supply module 501, a switch module 502 (using the circuitry of this solution to allow voltage injection into the plane under test 509), a detection terminal 503 (for electrically connecting the detection circuit to the plane under test 509), a detection module 504, a latch module 505, an output module 506, and a detection function shutdown module 507. Modules or independent devices may have the same or similar functions and application scenarios as those described in the above embodiments, or may include application scenarios as described in the above embodiments, such as applications in short-circuit detection devices, leakage detection devices, floating ground detection devices, and open-circuit detection devices. Further details will not be provided here.

[0079] This specification also provides an electronic device, including a circuit structure and a plane under test that are the same as or similar to those in the above embodiments. The circuit structure and plane under test that are the same as or similar to those in the above embodiments can be used as a module or part of a module in the electronic device, enabling the electronic device to have a self-testing function, that is, to autonomously perform reliability testing before power-on startup to achieve its main functions.

[0080] A schematic diagram of the module structure of an electronic device 607 module with the solution provided in this specification is shown below. Figure 6 As shown, it includes a switch module 601 (using the circuit in this solution to allow voltage injection into the plane under test 602), the plane under test 602, a detection module 603, a latch module 604, an output module 605, and a detection function shutdown module 606.

[0081] The application scenarios of the electronic device are the same as or similar to those described in the above embodiments, or include the application scenarios described in the above embodiments. Further details will not be provided here.

[0082] By applying the circuit described in this manual, blind spots in server monitoring can be covered before power-on. Furthermore, the simple, purely hardware-based circuit structure offers high reliability at low cost, optimizing the material, labor, and maintenance costs associated with traditional approaches to addressing monitoring blind spots.

[0083] The descriptions of directional terms in the embodiments of this specification, such as upper end face, lower end face, end, etc., are with reference to the accompanying drawings.

[0084] Other embodiments of this specification will be readily apparent to those skilled in the art upon consideration of the specification and practice of the technical solutions disclosed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0085] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0086] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A detection circuit, characterized in that, include: The first transistor (Q1) includes a control electrode connected to a first control voltage (V1), a first electrode connected to the control electrode of the third transistor and connected to a second control voltage (V2), and a second electrode grounded. Used to switch the switch state according to the first control voltage; The third transistor (Q3) includes a control electrode connected to the first electrode of the first transistor and the second control voltage, a first electrode connected to the third control voltage (V3), and a second electrode connected to the current inflow terminal of the unidirectional conducting element (D1). A circuit for switching the switching state according to the switching state of the first transistor, and for conducting the first electrode of the third transistor to the unidirectional conducting element when the transistor is in the conducting state. A unidirectional conducting element includes a current inflow terminal connected to the second electrode of a third transistor and a current outflow terminal connected to the plane under test. A circuit used for unidirectional conduction from the third transistor to the plane under test; The detection module is used to detect the voltage between the current outlet of the unidirectional conductive element and the plane under test; The first control voltage, the second control voltage, and the third control voltage are obtained by converting the operating voltage, and their timing lags behind the operating voltage, which is used to support the operation of the detection module.

2. The circuit according to claim 1, characterized in that, The first transistor is an NMOS transistor, the second electrode is the source, the source is grounded, the control electrode is the gate, the gate is connected to the first control voltage, the first electrode is the drain, the drain is connected to the gate of the third transistor and connected to the first control voltage; The second transistor is a PMOS transistor, with the gate as the control electrode. The gate is connected to the first electrode of the first transistor and is connected to the second control voltage. The first electrode is the drain, which is connected to the third control voltage. The second electrode is the source, which is connected to the current inflow terminal of the unidirectional conducting element. When the first transistor is off, the third transistor is on. The unidirectional conducting device is a diode, with its current inflow end being the anode, which is connected to the source of the third transistor, and its current outflow end being the cathode, which is connected to the plane to be tested, and the cathode is also connected to a detection module.

3. The circuit according to claim 2, characterized in that, A ninth load (R9) is connected between the control electrode of the third transistor and the first control voltage; A first load (R1) is connected between the second electrode of the third transistor and the unidirectional conducting element.

4. The circuit according to claim 1, characterized in that, The detection module includes: The second transistor (Q2) includes a control electrode connected to the plane under test, a first electrode connected to a first operating voltage (V5) and connected to the control electrode of the fourth transistor, and a second electrode grounded; it is used to switch the switching state according to the voltage of the plane under test. The fourth transistor (Q4) includes a control electrode connected to the first electrode of the second transistor, a grounded second electrode, and a first electrode connected to a fourth control voltage (V4); it is used to switch the switching state according to the voltage of the first electrode of the second transistor. The fifth transistor (Q5) includes a control electrode connected to the first electrode of the fourth transistor, a first electrode connected to the output terminal with a second operating voltage (V6), and a second electrode grounded; used to switch the switching state according to the voltage of the first electrode of the fourth transistor. The output terminal is used to output the detection results of the detection module on the plane under test.

5. The circuit according to claim 4, characterized in that, The second transistor is an NMOS transistor, with the gate as the control electrode and the gate connected to the plane under test. The first electrode is the drain, which is connected to the first operating voltage and the gate of the fourth transistor. The second electrode is the source, which is grounded. The fourth transistor is an NMOS transistor, with the gate as the control electrode. The gate is connected to the first electrode of the second transistor, the second electrode is the source, the source is grounded, the first electrode is the drain, and the drain is connected to the fourth control voltage. The fifth transistor is an NMOS transistor with a gate as the control electrode. The gate is connected to the first electrode of the fourth transistor, which is the drain. The drain is connected to the second operating voltage and then to the output terminal. The second electrode is the source, which is grounded.

6. The circuit according to claim 4, characterized in that, A tenth load (R10) is connected between the first electrode of the second transistor and the control electrode of the fourth transistor; A third load (R3) is connected between the first electrode of the fourth transistor and the fourth control voltage.

7. The circuit according to claim 4, characterized in that, An eleventh load (R11) is connected between the first electrode of the second transistor and the second electrode of the second transistor; A fifth load (R5) is connected between the first and second electrodes of the fifth transistor.

8. The circuit according to claim 4, characterized in that, The output terminal is connected to a latch module, which includes: The sixth transistor (Q6) includes a second electrode connected to the first electrode of the fifth transistor, a control electrode connected to the second electrode of the seventh transistor, and a first electrode grounded. The seventh transistor (Q7) includes a control electrode connected to the second electrode of the sixth transistor, a second electrode connected to the control electrode of the sixth transistor, and a first electrode connected to the third operating voltage (V7).

9. The circuit according to claim 8, characterized in that, The sixth transistor is an NMOS transistor, with the second electrode being the source, which is connected to the drain of the fifth transistor. The control electrode is the gate, which is connected to the second electrode of the seventh transistor. The first electrode is the drain, which is grounded. The seventh transistor is a PMOS transistor with a gate as the control electrode. The gate is connected to the second electrode of the sixth transistor, which is the source. The source is connected to the control electrode of the sixth transistor, and the first electrode is the drain. The drain is connected to the third operating voltage.

10. The circuit according to claim 8, characterized in that, An eighth load (R8) is connected between the first electrode of the sixth transistor and ground; A seventh load (R7) is connected between the first electrode of the seventh transistor and ground.

11. The circuit according to claim 4, characterized in that, The second transistor has a second load (R2) between its first electrode and the first operating voltage to prevent the fifth transistor from being mis-energized; The fourth transistor has a fourth load (R4) between its first electrode and the second operating voltage to prevent the seventh transistor from being mis-energized.

12. The circuit according to claim 4, characterized in that, In response to an event in which a detection result is output at the output terminal, a delay voltage (V8) is applied to the control electrode of the fourth transistor to fix the operating state of the fourth transistor; there is a time interval between the application of the delay voltage and the event in which the detection result is output at the output terminal.

13. A detection device, characterized in that, include: The detection circuit as described in any one of claims 1-12; The detection end is used to electrically connect the detection circuit to the plane under test; The power supply module is used to provide control voltage and / or operating voltage to the detection circuit.

14. An electronic device, characterized in that, The device includes: The detection circuit according to any one of claims 1-12; The plane to be tested is used to be detected by the detection circuit.

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