A dual-channel transistor chip tester

Abstract

The utility model discloses a kind of dual-channel transistor chip testers, comprising: transistor chip testing machine, transistor chip testing machine is connected with the transistor to be measured by chip test box;Chip test box includes test seat, probe line b, probe line c, probe line e are equipped in test seat and are connected with transistor pin, probe line b and probe line e are connected with the HOT end of the test line and the COM end of the test line in the same group of transistor chip testing machine by switch K3 and switch K4;Light source is connected between probe line b and probe line e in series, the HOT end of light source is connected with the HOT end of test line by switch K1, the COM end of light source is connected with the COM end of test line by switch K2;Probe line b, probe line c, probe line e are connected with the test end of transistor chip testing machine by probe control switch group.The utility model discloses a kind of dual-channel transistor chip testers of high detection test compatibility, can be compatible with photosensitive transistor chip test.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor testing technology, specifically to a dual-channel transistor chip tester. Background Technology

[0002] With the rapid development of the new energy vehicle industry, the demand for thyristor optocouplers used in power control, electric vehicle charging piles, battery management systems (BMS) and other equipment is increasing. The quality of thyristor optocoupler chips will directly affect the safety of power equipment.

[0003] Chip packaging manufacturers conduct power-on tests on thyristor optocouplers during the packaging stage to ensure production quality. However, existing testing methods are cumbersome and inconvenient for testing different thyristor optocouplers in the same testing facility, as well as for flexibly switching between multiple test parameters. Utility Model Content

[0004] This invention overcomes the shortcomings of the prior art and provides a dual-channel transistor chip tester with high compatibility in testing and detection, which can be compatible with photosensitive transistor chip testing.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows: a dual-channel transistor chip tester, comprising: a transistor chip tester, wherein the transistor chip tester is connected to the transistor under test through a plurality of chip test boxes; the chip test box includes a test socket, wherein the test socket is provided with probe lines b, c, and e respectively connected to the transistor pins, the probe lines b and e being connected to the HOT and COM terminals of the test lines in the same group in the transistor chip tester through switches K3 and K4 respectively; and a light source is also connected between the probe lines b and e, the HOT terminal of the light source being connected to the HOT terminal of the test line through switch K1, and the COM terminal of the light source being connected to the COM terminal of the test line through switch K2; the probe lines b, c, and e are connected to the test terminals of the transistor chip tester through a probe control switch group.

[0006] Preferably, the port of probe line b is connected to the base (b) terminal of the transistor under test; the port of probe line e is connected to the emitter (e) terminal of the transistor under test; and the port of probe line c is connected to the collector (c) terminal of the transistor under test.

[0007] Preferably, the probe control switch assembly includes a switch K5 connected to the probe line b. The probe wire C leads out in three paths, which are respectively connected to switches K6, K7, and K8. The probe wire e leads out in three directions and is connected to switches K9, K10, and K11 respectively. One end of switch K5 and one end of switch K6 are connected to the COM and HOT terminals of the same test terminal of the transistor chip tester. One end of switch K7 and one end of switch K11 are connected to the HOT and COM terminals of the same test terminal of the transistor chip tester. Connect one end of switch K5, one end of switch K8, and one end of switch K10; One end of switch K6 is connected to one end of switch K9.

[0008] Preferably, the controlled coils interconnected by each of switches K1 to K11 are connected to the corresponding I / O terminals of the transistor chip tester through the corresponding Darlington control chip.

[0009] Preferably, the transistor chip tester is connected to the transistor under test through two sets of chip test boxes; Two sets of chip test boxes, including chip test box one and chip test box two; The transistor chip tester includes: an interconnected industrial control computer, test station one, and test station two. The industrial control computer is connected to test station one and test station two respectively via a bus.

[0010] Specifically, test station one includes interconnected SMU module A1, I / O control unit one connected to SMU module A1, SMU module B1, and SMU module B1 high voltage unit connected to SMU module B1; SMU module A1, SMU module B1, and SMU module B1 high voltage unit are respectively connected to transistor chip test box one through test lines. The I / O control unit is connected to the transistor chip test box via I / O line 1.

[0011] Specifically, test station two includes interconnected SMU module A2, I / O control unit two connected to SMU module A2, SMU module B2, and SMU module B2 high voltage unit connected to SMU module B2; SMU module A2, SMU module B2, and SMU module B2 high voltage unit are respectively connected to transistor chip test box two through test lines; I / O control unit 2 is connected to transistor chip test box 2 via I / O line 2.

[0012] Preferably, the transistor chip tester tests V (BR)CBO I CBO When switches K6 and K5 are closed, V (BR)CBO For applying current to test voltage items; I CBO For applying voltage to test current items.

[0013] Preferably, the transistor chip tester tests V (BR)CEO I CEO When the voltage is below 20V, switches K6 and K10 are closed; when the power-on parameters of the transistor chip tester are set to less than 20V, switches K7 and K11 are closed. (BR)CEO For applying current to test voltage items; I CEO For applying voltage to test current items.

[0014] Preferably, the transistor chip tester tests V (BR)EBO I EBO When the voltage is set to less than 20V, switches K9 and K5 are closed; when the voltage setting of the transistor chip tester is less than 20V, switches K3 and K4 are closed. (BR)EBO The project involves applying current and testing voltage; I EBO For applying voltage to test current items.

[0015] Preferably, the transistor chip tester tests V CE（sat） h FE When, switches K3 and K4 are closed, and switches K7 and K11 are closed, where h FE =Ic / Ib*100%, where Ic and Ib are the applied voltage and test current values; V CE（sat） The project involves applying current and testing voltage.

[0016] Preferably, if the transistor to be tested by the transistor chip tester is a phototransistor chip, then switches K1, K2, K7, and K11 are closed; Alternatively, a transistor chip tester tests V. BE（sat） When the switch is closed, switches K3, K4, K7, and K11 are closed; V BE（sat） The project involves applying current and testing voltage.

[0017] This utility model solves the defects existing in the technical background, and the beneficial technical effects of this utility model are: This invention relates to a dual-channel transistor chip tester with high compatibility in testing and detection, which is compatible with photosensitive transistor chip testing. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] Figure 1 This is a circuit diagram of the chip test box of a dual-channel transistor chip tester according to a preferred embodiment of the present invention. Figure 2This is a schematic diagram of the control circuit of the controlled coils corresponding to the interconnection of switches K1 to K11 in a dual-channel transistor chip tester according to a preferred embodiment of the present invention. Figure 3 This is a schematic diagram of the testing principle of a dual-channel transistor chip tester according to a preferred embodiment of the present invention; Figure 4 This is a preferred embodiment of a dual-channel transistor chip tester for testing the V of a transistor under test. (BR)CEO The oscilloscope waveform diagram. (This project involves applying current and voltage to the collector and emitter terminals of a transistor. Switches K6 and K10 of the transistor chip test box must be closed.) Figure 5 This is a preferred embodiment of a dual-channel transistor chip tester for testing the V of a transistor under test. (BR)CEO The test interface diagram of the tester. (This project involves applying current and voltage to the collector and emitter terminals of a transistor. Switches K6 and K10 of the transistor chip test box must be closed.) Figure 6 This is a preferred embodiment of a dual-channel transistor chip tester for testing the V of a transistor under test. CE（sat） The oscilloscope waveform (test voltage test by applying current to the collector and emitter terminals of a transistor. Current must also be applied to the base and emitter terminals to turn the transistor on). Figure 7 This is a preferred embodiment of a dual-channel transistor chip tester for testing the V of a transistor under test. CE（sat） The test interface diagram of the tester (the voltage test item involves applying current to the collector and emitter terminals of a transistor. Current must also be applied to the base and emitter terminals to turn the transistor on). Figure 8 This is a preferred embodiment of a dual-channel transistor chip tester for testing the I-channel transistor under test. CEO Test interface diagram (I) CEO (To test the leakage current of a transistor when the collector and emitter are in the off state by applying a voltage). Figure 9 This is a preferred embodiment of a dual-channel transistor chip tester for testing the h of a transistor under test. FE Test value interface diagram (h) FE This is the ratio of the current at the collector (c) and emitter (e) to the current at the base (b) and emitter (e) when the transistor is in the on state. Detailed Implementation

[0020] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. These drawings are simplified schematic diagrams, which are only used to illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0021] It should be noted that if directional indicators (such as up, down, bottom, top, etc.) are involved in the embodiments of this utility model, the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Unless otherwise explicitly specified and limited, the terms "set," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this utility model can be understood according to the specific circumstances.

[0022] Example 1, as Figures 1-3 As shown, a dual-channel transistor chip tester includes: a transistor chip tester, which is connected to the transistor under test through several chip test boxes.

[0023] Specifically, the chip test box includes a test socket, which contains probe lines b, c, and e that are respectively connected to the transistor pins. The port of probe line b is connected to the base (b) of the transistor under test; the port of probe line e is connected to the emitter (e) of the transistor under test; and the port of probe line c is connected to the collector (c) of the transistor under test.

[0024] Furthermore, probe line b and probe line e are respectively connected to the HOT terminal and COM terminal of the test line in the same group in the transistor chip tester via switches K3 and K4; a light source is also connected between probe line b and probe line e, with the HOT terminal of the light source connected to the HOT terminal of the test line via switch K1, and the COM terminal of the light source connected to the COM terminal of the test line via switch K2; probe line b, probe line c, and probe line e are connected to the test terminal of the transistor chip tester via a probe control switch group.

[0025] Specifically, the probe control switch group includes switch K5 connected to probe line b, three leads from probe line c connected to switches K6, K7, and K8 respectively, and three leads from probe line e connected to switches K9, K10, and K11 respectively. One end of switch K5 and one end of switch K6 are connected to the COM and HOT terminals of the same test terminal of the transistor chip tester; one end of switch K7 and one end of switch K11 are connected to the HOT and COM terminals of the same test terminal of the transistor chip tester; one end of switch K5, one end of switch K8, and one end of switch K10 are connected; and one end of switch K6 and one end of switch K9 are connected.

[0026] In Example 2, based on Example 1, the controlled coils corresponding to switches K1 to K11 are connected to the corresponding I / O terminals of the transistor chip tester through their respective Darlington control chips. The transistor chip tester uses existing technology, such as the scheme in patent CN116224004A (patent title: A Multi-Station Synchronous Optical Coupler Test System and Test Method Thereof); however, it is not limited to this, and other existing transistor chip testers can also be used, as long as they can at least basically meet the testing requirements of this example.

[0027] In Example 3, based on Example 1 or Example 2, the transistor chip tester is connected to the transistor under test through two sets of chip test boxes; the two sets of chip test boxes include chip test box 1 and chip test box 2; the transistor chip tester includes: an interconnected industrial control computer, test station 1, and test station 2, and the industrial control computer is connected to test station 1 and test station 2 respectively through a bus.

[0028] Specifically, test station one includes interconnected SMU module A1, I / O control unit one connected to SMU module A1, SMU module B1, and SMU module B1 high voltage unit connected to SMU module B1; SMU module A1, SMU module B1, and SMU module B1 high voltage unit are respectively connected to transistor chip test box one via test lines; I / O control unit one is connected to transistor chip test box one via I / O line one.

[0029] Specifically, test station two includes interconnected SMU module A2, I / O control unit two connected to SMU module A2, SMU module B2, and SMU module B2 high voltage unit connected to SMU module B2; SMU module A2, SMU module B2, and SMU module B2 high voltage unit are respectively connected to transistor chip test box two via test lines; I / O control unit two is connected to transistor chip test box two via I / O line two.

[0030] Example 4, based on any one of Examples 1 to 3, such as Figures 1-3 As shown, the transistor chip test box consists of a switch array composed of several sets of reed relays. I / O control lines connect to the switch array and independently control the switches, adjusting their on / off states according to different test items. Test lines 1, 2, and 3 each contain HOT and COM terminals. Specifically, the HOT terminal of test line 1-1 is connected to the "Test Line 1 HOT" port on the transistor chip test box schematic; the HOT terminal of test line 2-1 is connected to the "Test Line 2 HOT" port on the schematic; and the HOT terminal of test line 3-1 is connected to the "Test Line 3 HOT" port on the schematic. Similarly, the COM terminal of test line 1-1 is connected to the "Test Line 1 COM" port on the schematic; the COM terminal of test line 2-1 is connected to the "Test Line 2 COM" port on the schematic; and the COM terminal of test line 3-1 is connected to the "Test Line 3 COM" port on the schematic.

[0031] Preferably, the HOT end of test line one is connected to one end of switch K1, and the other end of switch K1 is led out and serves as the HOT port of the light source line, connecting to the anode of an external light source; the HOT end of test line one is connected to one end of switch K3, and the other end of switch K3 is led out and serves as the b port of the probe line, connecting to the base (b) of the transistor chip under test; the COM end of test line one is connected to one end of switch K2, and the other end of switch K2 is led out and serves as the COM port of the light source line, connecting to the cathode of an external light source; the COM end of test line one is connected to one end of switch K4, and the other end of switch K4 is led out and serves as the e port of the probe line, connecting to the emitter (e) of the transistor chip under test; Test line 2 HOT terminal is connected to one end of switch K7, and the other end of switch K7 is led out as probe line c port to connect to the collector of the transistor chip under test; test line 2 COM terminal is connected to one end of switch K11, and the other end of switch K11 is led out to connect to probe line e port. The HOT terminal of test lead 3 is connected to one end of switch K6, and the other end of switch K6 is connected to probe line port c; the HOT terminal of test lead 3 is connected to one end of switch K9, and the other end of switch K9 is connected to probe line port e; the COM terminal of test lead 3 is connected to one end of switch K5, and the other end of switch K5 is connected to probe line port b; the COM terminal of test lead 3 is connected to one end of switch K8, and the other end of switch K8 is connected to probe line port c; the COM terminal of test lead 3 is connected to one end of switch K10, and the other end of switch K10 is connected to probe line port e.

[0032] Furthermore, the structure of transistor chip test box two is the same as that of transistor chip test box one.

[0033] More specifically, the probe line C1 port of transistor chip test box one is connected to the collector (C) of the material under test one, the probe line B1 port of transistor chip test box one is connected to the base (B) of the material under test one, and the probe line C1 port of transistor chip test box one is connected to the collector (C) of the material under test one. The light source line 1 of transistor chip test box one supplies power to light source one for testing phototransistors. The probe line C2 port of transistor chip test box two is connected to the collector (C) of the material under test two, the probe line B2 port of transistor chip test box two is connected to the base (B) of the material under test two, and the probe line C2 port of transistor chip test box two is connected to the collector (C) of the material under test two. Transistor chip test box two supplies power to light source for testing phototransistors.

[0034] Example 5: Based on any one of Examples 1 to 2, the transistor chip tester tests V. (BR)CBO I CBO When switches K6 and K5 are closed, V (BR)CBO For applying current to test voltage items; I CBO For applying voltage to test current items. Specifically, V (BR)CBO Collector-base reverse breakdown voltage—that is, the reverse breakdown voltage between the collector and base when the emitter is open (E open circuit). CBO Collector-base reverse leakage current—that is, the reverse leakage current between the collector and base when the emitter of the transistor is open.

[0035] Example 6: Based on any one of Examples 1 to 3, the transistor chip tester tests V. (BR)CEO I CEO When the voltage is below 20V, switches K6 and K10 are closed; when the voltage setting of the transistor chip tester is less than 20V, switches K7 and K11 are closed. (BR)CEO To apply current to test voltage (V) (BR)CEO Collector-emitter reverse breakdown voltage—that is, the reverse breakdown voltage between the collector and emitter when the base is open (B open circuit); I CEO For applying voltage to test current items. CEO Collector-emitter reverse leakage current—that is, the reverse leakage current between the collector and emitter when the base of the transistor is open. The power-on parameters in this embodiment are provided by a transistor chip tester.

[0036] Example 7: Based on any one of Examples 1 to 3, a transistor chip tester tests V. (BR)EBO I EBOWhen the voltage is set to less than 20V, switches K9 and K5 are closed; when the voltage setting of the transistor chip tester is less than 20V, switches K3 and K4 are closed. (BR)EBO The project involves applying current and testing voltage; specifically, V (BR)EBO Emitter-base reverse breakdown voltage—that is, the reverse breakdown voltage between the emitter and base when the collector is open (C open circuit). EBO For applying voltage and testing current parameters. Specifically, I EBO Emitter-base reverse leakage current—that is, the reverse leakage current between the emitter and base when the collector of a transistor is open.

[0037] Example 8: Based on any one of Examples 1 to 3, a transistor chip tester tests V. CE（sat） h FE When, switches K3 and K4 are closed, and switches K7 and K11 are closed, where h FE =Ic / Ib*100%, where Ic and Ib are the applied voltage and test current values; V CE（sat） The project involves applying a current and testing the voltage. Specifically, V CE（sat） Collector-emitter saturation voltage—that is, the voltage drop between the collector and emitter when the transistor is in the saturation region. FE DC current amplification factor — i.e., collector current Ic / base current Ib of the transistor * 100%.

[0038] Example 9: Based on any of Examples 1 to 3, if the transistor to be tested by the transistor chip tester is a phototransistor chip, then switches K1, K2, K7, and K11 are closed.

[0039] Example 10: Based on any one of Examples 1 to 3, a transistor chip tester tests V. BE（sat） At this time, switches K3, K4, K7, and K11 are closed; V BE（sat） The project involves applying current and testing voltage. Specifically, V BE（sat） Base-emitter saturation voltage – that is, the voltage drop between the base and emitter when the transistor is in the saturation region.

[0040] Example 11: Based on any of Examples 1 to 3, when testing different items, the control of different switches inside the test box is determined and controlled by the test instrument software, and its instructions are transmitted through... Figure 3 The I / O control unit is connected to the test box via I / O lines. These I / O lines are bundled cables containing several sets of signal lines that control different switches within the test box.

[0041] The following example uses the K1 switch inside the test box: like Figure 2 As shown, signal line IO_K1 is connected to the input terminal of Darlington chip U1 (model ULN2003). The output terminal of Darlington chip U1 is connected to the controlled coil of relay switch K1. The other end of the controlled coil of K1 is connected to a +12V power supply, and the emitter of Darlington chip U1 is grounded. In the default state when the switch is open: IO_K1 is at a low level, the Darlington chip is cut off, there is no circuit between the 12V power supply, the controlled coil of K1, and ground, no current flows through the controlled coil of K1, and switch K1 cannot be turned on.

[0042] When it is necessary to turn on switch K1: IO_K1 outputs a high level, the Darlington chip is turned on, a loop is formed between the 12V power supply, the controlled coil of K1, and ground, current flows through the controlled coil of K1, and switch K1 is turned on.

[0043] Working principle: This invention discloses a dual-channel transistor chip tester with high compatibility in testing, capable of testing phototransistor chips. Transistor chip test box one is connected to the collector (c) of transistor one under test via corresponding probe lines c, the base (b) of transistor one under test via corresponding probe lines b, and the emitter (e) of transistor one under test via corresponding probe lines e. Transistor chip test box one supplies power to the corresponding light source for testing phototransistors. Transistor chip test box two is connected to the collector (c) of transistor one under test via corresponding probe lines c, the base (b) of transistor two under test via corresponding probe lines b, and the emitter (e) of transistor two under test via corresponding probe lines e. Transistor chip test box two supplies power to the corresponding light source for testing phototransistors. This invention facilitates testing of conventional collector-base (c), base-electron (b), and emitter (e) transistor chips and is also compatible with testing phototransistor chips.

[0044] The above specific embodiments are specific support for the proposed solution concept of this utility model, and should not be used to limit the protection scope of this utility model. Any equivalent changes or modifications made on the basis of this technical solution in accordance with the technical concept proposed by this utility model shall still fall within the protection scope of this utility model.

Claims

1. A dual-channel transistor chip tester, comprising: A transistor chip tester, wherein the transistor chip tester is connected to the transistor under test through a plurality of chip test boxes; characterized in that: the chip test box includes a test socket, and the test socket is provided with probe lines b, c and e respectively connected to the transistor pins, and probe lines b and e are respectively connected to the HOT terminal and COM terminal of the test lines in the same group in the transistor chip tester through switches K3 and K4 respectively; Furthermore, a light source is connected between probe line b and probe line e. The HOT end of the light source is connected to the HOT end of the test line through switch K1, and the COM end of the light source is connected to the COM end of the test line through switch K2. The probe lines b, c, and e are connected to the test terminal of the transistor chip tester via a probe control switch group.

2. The dual-channel transistor chip tester according to claim 1, characterized in that: The port of probe line b is connected to the base (b) terminal of the transistor under test; the port of probe line e is connected to the emitter (e) terminal of the transistor under test; and the port of probe line c is connected to the collector (c) terminal of the transistor under test.

3. The dual-channel transistor chip tester according to claim 2, characterized in that: The probe control switch group includes switch K5 connected to probe line b. The probe wire C leads out in three paths, which are respectively connected to switches K6, K7, and K8. The probe wire e leads out in three directions and is connected to switches K9, K10, and K11 respectively. One end of switch K5 and one end of switch K6 are connected to the COM and HOT terminals of the same test terminal of the transistor chip tester. One end of switch K7 and one end of switch K11 are connected to the HOT and COM terminals of the same test terminal of the transistor chip tester. Connect one end of switch K5, one end of switch K8, and one end of switch K10; One end of switch K6 is connected to one end of switch K9.

4. The dual-channel transistor chip tester according to claim 3, characterized in that: The controlled coils of each of the switches K1 to K11 are connected to the corresponding I / O terminals of the transistor chip tester through the corresponding Darlington control chips.

5. The dual-channel transistor chip tester according to claim 3, characterized in that: The transistor chip tester is connected to the transistor under test through two sets of chip test boxes; Two sets of chip test boxes, including chip test box one and chip test box two; The transistor chip tester includes: an interconnected industrial control computer, test station one, and test station two. The industrial control computer is connected to test station one and test station two respectively via a bus.

6. The dual-channel transistor chip tester according to claim 4, characterized in that: Transistor chip tester tests V (BR)CBO I CBO When switches K6 and K5 are closed, V (BR)CBO For applying current to test voltage items; I CBO For applying voltage to test current items.

7. The dual-channel transistor chip tester according to claim 4, characterized in that: Transistor chip tester tests V (BR)CEO I CEO When the voltage is below 20V, switches K6 and K10 are closed; when the power-on parameters of the transistor chip tester are set to less than 20V, switches K7 and K11 are closed. (BR)CEO For applying current to test voltage items; I CEO For applying voltage to test current items.

8. The dual-channel transistor chip tester according to claim 4, characterized in that: Transistor chip tester tests V (BR)EBO I EBO When the voltage is set to less than 20V, switches K9 and K5 are closed; when the voltage setting of the transistor chip tester is less than 20V, switches K3 and K4 are closed. (BR)EBO The project involves applying current and testing voltage; I EBO For applying voltage to test current items.

9. The dual-channel transistor chip tester according to claim 4, characterized in that: Transistor chip tester tests V CE（sat） h FE When, switches K3 and K4 are closed, and switches K7 and K11 are closed, where h FE =Ic / Ib*100%, where Ic and Ib are the applied voltage and test current values; V CE（sat） The project involves applying current and testing voltage.

10. The dual-channel transistor chip tester according to claim 4, characterized in that: If the transistor under test tested by the transistor chip tester is a phototransistor chip, then switches K1, K2, K7, and K11 are closed. Alternatively, a transistor chip tester tests V. BE（sat） When the switch is closed, switches K3, K4, K7, and K11 are closed; V BE（sat） The project involves applying current and testing voltage.

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