Fault detection circuit and fault detection system

Abstract

The application relates to the technical field of circuits, and particularly provides a fault detection circuit and a fault detection system, aiming to solve the technical problem of high cost of circuit fault detection in the prior art. For the purpose, the fault detection circuit comprises an operational amplifier, a bias voltage branch, a power supply voltage branch and a signal sampling branch, wherein the same direction input end of the operational amplifier is connected with the positive electrode end of a to-be-detected circuit, the opposite direction input end of the operational amplifier is connected with the negative electrode end of the to-be-detected circuit; the bias voltage branch is connected with the same phase input end of the operational amplifier; the power supply voltage branch is connected with the power supply pin of the operational amplifier; and the signal sampling branch is connected with the output end of the operational amplifier. Through the application, the number of components is reduced, the complexity and hardware cost of the circuit are reduced, and by adjusting the parameters of the bias voltage and the power supply voltage, different voltage detection ranges and fault threshold values can be adapted, so that the flexibility and applicability of the circuit are enhanced.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically providing a fault detection circuit and a fault detection system. Background Technology

[0002] With the booming development of industrial and commercial energy storage and large-scale energy storage, and the continuous advancement of battery management technology, people are placing increasingly higher demands on battery management systems in pursuit of safer and more reliable systems. Energy storage systems generally consist of multiple high-voltage battery clusters connected in parallel or series to supply power to the load. These high-voltage battery clusters typically consist of multiple cells connected in series, and then, after being combined and managed by a high-voltage box, provide high-voltage direct current to the combiner cabinet.

[0003] Traditional high-voltage detection solutions have many shortcomings in dealing with reverse connection faults and are unable to meet increasingly stringent safety and reliability requirements. When reverse connection occurs, forced reverse charging occurs inside the battery cell, which may cause electrolyte decomposition, irreversible damage to electrode materials, or even thermal runaway. It may also cause polarity-sensitive components in the battery management system or energy storage converter, such as MOSFETs and diodes, to break down due to reverse voltage.

[0004] To address the limitations of hardware-based high-voltage reverse connection detection methods, a polarity detection module can be connected in series in the circuit. However, this approach requires additional components, significantly increasing circuit design complexity, wiring difficulties, and potential failure risks, thus jeopardizing system reliability. Furthermore, this solution demands greater resources from component procurement to PCB design and manufacturing, leading to a substantial increase in hardware costs. Additionally, the additional module occupies a significant amount of space, making it less adaptable to space-constrained applications such as energy storage systems, thus limiting its widespread adoption.

[0005] Alternatively, another reverse connection protection scheme involves connecting fuses in series between the positive and negative terminals, and a reverse discharge diode such as a TVS diode in parallel. However, this scheme is a one-time protection mechanism; after the fuse blows, it must be manually replaced, which not only increases maintenance costs but may also cause the system to lose its protection capability if replacement is not done in a timely manner. In addition, under high current operating conditions, fuses and TVS diodes will generate significant conduction losses, reducing the overall system efficiency. Long-term operation may also affect the stability and lifespan of surrounding components due to heat generation.

[0006] Accordingly, there is a need in the field for a new fault detection circuit and fault detection system solution to address the above problems. Utility Model Content

[0007] In order to overcome the above-mentioned defects, this application is made to provide a fault detection circuit and a fault detection system that solves or at least partially solves the technical problem of high cost of circuit fault detection in the prior art.

[0008] In a first aspect, this application provides a fault detection circuit, including an operational amplifier, a bias voltage branch, a power supply voltage branch, and a signal sampling branch. The non-inverting input of the operational amplifier is connected to the positive terminal of the circuit under test, and the inverting input of the operational amplifier is connected to the negative terminal of the circuit under test. The bias voltage branch is connected to the non-inverting input of the operational amplifier. The power supply voltage branch is connected to the power supply pin of the operational amplifier. The signal sampling branch is connected to the output of the operational amplifier. If the voltage value obtained by the signal sampling branch is within the numerical range formed by the voltage value provided by the bias voltage branch and the voltage value provided by the power supply voltage branch, then the circuit under test is fault-free; if the voltage value obtained by the signal sampling branch is not within the numerical range, then the circuit under test is faulty.

[0009] In one technical solution of the above-mentioned fault detection circuit, the bias voltage branch includes a first voltage source, a first resistor, and a first capacitor. One end of the first resistor is connected to the first voltage source, and the other end of the first resistor and one end of the first capacitor are connected to the non-inverting input terminal of the operational amplifier. The other end of the first capacitor is grounded.

[0010] In one technical solution of the above-mentioned fault detection circuit, the power supply voltage branch includes a second voltage source and a second capacitor, wherein one end of the second capacitor and the second voltage source are connected to one of the power supply pins of the operational amplifier, the other end of the second capacitor is grounded, and the other power supply pin of the operational amplifier is grounded.

[0011] In one technical solution of the above-mentioned fault detection circuit, a feedback branch is also included. One end of the feedback branch is connected to the inverting input terminal of the operational amplifier, and the other end of the feedback branch is connected to the output terminal of the operational amplifier.

[0012] In one technical solution of the above-mentioned fault detection circuit, the feedback branch includes a second resistor and a third capacitor, wherein the second resistor and the third capacitor are connected in parallel, and one end of the second resistor and one end of the third capacitor are connected to the inverting input terminal of the operational amplifier, and the other end of the second resistor and the other end of the third capacitor are connected to the output terminal of the operational amplifier.

[0013] In one technical solution of the above-mentioned fault detection circuit, a first voltage divider branch and a second voltage divider branch are further included. The first voltage divider branch includes a plurality of resistors connected in series, and the second voltage divider branch includes a plurality of resistors connected in series. One end of the first voltage divider branch is connected to the positive terminal of the circuit under test, and the other end of the first voltage divider branch is connected to the non-inverting input terminal of the operational amplifier. One end of the second voltage divider branch is connected to the negative terminal of the circuit under test, and the other end of the second voltage divider branch is connected to the inverting input terminal of the operational amplifier.

[0014] In one technical solution of the above-mentioned fault detection circuit, a first inductor and a second inductor are further included, wherein the first inductor is connected in series with the first voltage divider branch and is located between the circuit to be detected and the first voltage divider branch; the second inductor is connected in series with the second voltage divider branch and is located between the circuit to be detected and the second voltage divider branch.

[0015] In one technical solution of the above-mentioned fault detection circuit, a first filtering circuit is further included. The first filtering circuit is disposed between the circuit to be detected and the first inductor and the second inductor. The first filtering circuit includes a fourth capacitor and a fifth capacitor. One end of the fourth capacitor is connected to the positive terminal of the circuit to be detected, the other end of the fourth capacitor is connected to one end of the fifth capacitor, and the other end of the fifth capacitor is connected to the negative terminal of the circuit to be detected.

[0016] In one technical solution of the above-mentioned fault detection circuit, a second filter circuit is also included. One end of the second filter circuit is disposed between the first inductor and the first voltage divider branch, and the other end of the second filter circuit is disposed between the second inductor and the second voltage divider branch. The second filter circuit includes a sixth capacitor.

[0017] In a second aspect, this application provides a fault detection system, which includes at least the fault detection circuit in any of the above-described fault detection circuit technical solutions.

[0018] The above-described technical solutions of this application have at least one or more of the following beneficial effects:

[0019] The technical solution of this application eliminates the need for additional complex detection modules or dedicated protection devices, significantly reducing the number of components and lowering the complexity of circuit design and hardware costs. Furthermore, by adjusting the parameters of the bias voltage and supply voltage, it can adapt to different voltage detection ranges and fault thresholds, enhancing the flexibility and applicability of the circuit. Attached Figure Description

[0020] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Furthermore, similar numbers in the drawings are used to denote similar components, wherein:

[0021] Figure 1 This is a schematic diagram of the main structure of a fault detection circuit according to an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the main structure of a fault detection circuit according to an embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the main structure of a fault detection system according to an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present utility model and are not intended to limit the present utility model; that is, the described embodiments are only some embodiments of the present utility model, not all embodiments. The components of the embodiments of the present utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present utility model provided in the accompanying drawings is not intended to limit the scope of the claimed utility model, but merely represents selected embodiments of the present utility model. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without inventive effort are within the scope of protection of the present utility model.

[0025] It should be noted that in the description of this application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "A and / or B" represents all possible combinations of A and B, such as only A, only B, or A and B. The terms "at least one A or B" or "at least one of A and B" have a similar meaning to "A and / or B" and can include only A, only B, or A and B. The singular forms of the terms "a" and "this" may also include plural forms.

[0026] See Figure 1 , Figure 1 This is a schematic diagram of the main structure of a fault detection circuit according to an embodiment of this application. Figure 1 As shown, the fault detection circuit of this application includes an operational amplifier, a bias voltage branch, a power supply voltage branch, and a signal sampling branch. The non-inverting input of the operational amplifier is connected to the positive terminal of the circuit under test, and the inverting input of the operational amplifier is connected to the negative terminal of the circuit under test. The bias voltage branch is connected to the non-inverting input of the operational amplifier. The power supply voltage branch is connected to the power supply pin of the operational amplifier. The signal sampling branch is connected to the output of the operational amplifier.

[0027] In this embodiment, the voltage at the non-inverting input of the operational amplifier is raised to a positive voltage range by the bias voltage branch. Furthermore, the voltages provided by the bias voltage branch and the supply voltage branch together form a reference voltage range that can characterize whether the circuit under test has experienced faults such as reverse polarity or open circuit.

[0028] See also Figure 1 and Figure 2In one embodiment, the bias voltage branch includes a first voltage source V1, a first resistor R13, and a first capacitor C3. One end of the first resistor R13 is connected to the first voltage source V1, and the other end of the first resistor R13 and one end of the first capacitor C3 are connected to the non-inverting input of the operational amplifier. The other end of the first capacitor C3 is grounded. Providing a precise bias voltage to the non-inverting input of the operational amplifier through the first resistor R13 not only raises the differential signal reference point to ensure the normal operating range of the operational amplifier but also provides a reference voltage to characterize whether a fault has occurred in the circuit under test. The bias voltage is decoupled to digital-analog ground via the first capacitor C3.

[0029] The power supply branch includes a second voltage source V2 and a second capacitor C4. One end of the second capacitor C4 and the second voltage source V2 are connected to one of the power supply pins of the operational amplifier, and the other end of the second capacitor C4 is grounded. The other power supply pin of the operational amplifier is also grounded. The entire operational amplifier is powered by the second voltage source V2 and decoupled through the second capacitor C4.

[0030] The fault detection circuit of this application may further include a feedback branch. One end of the feedback branch is connected to the inverting input of the operational amplifier, and the other end is connected to the output of the operational amplifier. Specifically, the feedback branch includes a second resistor R16 and a third capacitor C5, wherein the second resistor R16 and the third capacitor C5 are connected in parallel, and one end of the second resistor R16 and one end of the third capacitor C5 are both connected to the inverting input of the operational amplifier, and the other end of the second resistor R16 and the other end of the third capacitor C5 are both connected to the output of the operational amplifier. The inverting input of the operational amplifier forms a feedback network through the parallel connection of the second resistor R16 and the third capacitor C5, and finally transmits the voltage signal to the preset control center through the signal sampling branch. The signal sampling branch may include a resistor R17 and a capacitor C6, which together form a first-order low-pass filter and output a sampled signal.

[0031] The fault detection circuit of this application may further include a first voltage divider branch and a second voltage divider branch for voltage reduction. Each voltage divider branch includes several resistors connected in series. One end of the first voltage divider branch is connected to the positive terminal of the circuit under test, and the other end of the first voltage divider branch is connected to the non-inverting input terminal of the operational amplifier. One end of the second voltage divider branch is connected to the negative terminal of the circuit under test, and the other end of the second voltage divider branch is connected to the inverting input terminal of the operational amplifier. For example, in one embodiment, such as... Figure 2As shown, the resistors connected in series in the first voltage divider branch include R1-R6 and R14, and the resistors connected in series in the second voltage divider branch include R7-R12 and R15. Through the voltage divider branches, the high voltage from the detection circuit is divided step by step to finally obtain a low voltage signal that can be received and processed by the operational amplifier.

[0032] To suppress high-frequency common-mode noise signals appearing between the positive and negative terminals of the circuit under test and ground, the fault detection circuit of this application may further include a first inductor and a second inductor, wherein the first inductor is connected in series with the first voltage divider branch and located between the circuit under test and the first voltage divider branch; the second inductor is connected in series with the second voltage divider branch and located between the circuit under test and the second voltage divider branch. Specifically, as shown... Figure 2 As shown, the first inductor L1 is located between the circuit under test and the first voltage divider branch, and the second inductor L2 is located between the circuit under test and the second voltage divider branch. The first inductor L1 and the second inductor L2 serve as high-frequency noise suppression components, capable of filtering out high-frequency interference at the positive and negative terminals of the circuit under test.

[0033] To further suppress interference at the positive and negative terminals of the circuit under test, this application may further include a first filter circuit. The first filter circuit is disposed between the circuit under test and the first inductor and the second inductor. The first filter circuit includes a fourth capacitor and a fifth capacitor, wherein one end of the fourth capacitor is connected to the positive terminal of the circuit under test, the other end of the fourth capacitor is connected to one end of the fifth capacitor, and the other end of the fifth capacitor is connected to the negative terminal of the circuit under test. Figure 2 As shown, the first filter circuit includes a fourth capacitor C1 and a fifth capacitor C2. The fourth capacitor C1 is connected to the positive terminal of the circuit under test, and the fifth capacitor C2 is connected to the negative terminal of the circuit under test. The fourth capacitor C1 and the fifth capacitor C2, connected in parallel between the positive and negative terminals of the circuit under test, form a differential-mode filter network. By providing a low-impedance loop for high-frequency differential-mode noise, they effectively suppress differential interference between the positive and negative terminals.

[0034] This application may further include a second filter circuit, one end of which is disposed between the first inductor and the first voltage divider branch, and the other end of which is disposed between the second inductor and the second voltage divider branch. The second filter circuit includes a sixth capacitor. Figure 2 As shown, the sixth capacitor C7, located after the first inductor L1 and the second inductor L2, is connected across the positive terminal of the circuit under test after filtering, the negative terminal of the circuit under test, and the ground, thus forming a common-mode filtering path. This can effectively bypass the common-mode noise between the high-voltage line and the ground. It works together with the first and second inductors, the fourth capacitor C1, and the fifth capacitor C2 to form a complete π-type EMI filter.

[0035] In one implementation, with Figure 2 For example, the circuit under test can be a loop composed of several battery cells connected in series, or it can be a load loop connected to an electrical device. For a circuit under test consisting of several battery cells connected in series, the positive terminal is measured as BAT+, the negative terminal as BAT-, and the voltage obtained by the corresponding signal sampling branch is V. bat_out For the load circuit, the positive terminal is measured as HV+, the negative terminal as HV-, and the voltage obtained by the corresponding signal sampling branch is V. hv_out The voltage divider resistors R1~R6 and R7~R12 are 1MΩ surface-mount resistors, R14 and R15 are 75KΩ surface-mount resistors, and R16 is an 8.2KΩ surface-mount resistor. The first voltage source V1 of the bias voltage branch is 0.3V, and the second voltage source V2 of the supply voltage branch is 3.3V.

[0036] Take a circuit under test consisting of several battery cells connected in series as an example:

[0037] The voltage value of the circuit under test is V bat+ -V bat- =(V bat_out -0.3)*(R7+R8+R9+R10+R11+R12+R15) / R16, i.e., V bat+ -V bat- =(V bat_out -0.3)*6075 / 8.2, the voltage V obtained by the corresponding signal sampling branch. bat_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*(V bat+ -V bat- ) + 0.3V = 8.2 / 6075 * (V bat+ -V bat- +0.3V;

[0038] When the positive and negative terminals of the circuit under test are reversed, the voltage collected is V. bat_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*(V bat- -V bat+ +0.3V, where V bat- -V bat+ Much less than 0. The maximum voltage of the circuit to be detected in this embodiment is V. max_bat =3.7V * 416 = 1539.2V, the minimum voltage is V min_bat =2.5V * 416 = 1040V. When the positive and negative terminals of the circuit under test are reversed, the maximum reverse voltage is V. bat_out =8.2 / 6075*(-1539.2V)+0.3V=-1.778V<0V, minimum reverse voltage is Vbat_out =8.2 / 6075*(-1040V)+0.3V=-1.104V<0V, both of which are less than the 0.3V bias voltage and less than 0. Therefore, it can be determined that the positive and negative terminals of the circuit under test are reversed.

[0039] When an open circuit occurs in the circuit under test, V bat+ -V bat- The voltage obtained is 0V, and the voltage is V. bat_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*0+0.3V, V bat_out =0.3V, the collected voltage is 0.3V, which is equal to the bias voltage. Therefore, it can be determined that there is a broken wire fault in the circuit under test.

[0040] When the circuit under test is fault-free, the voltage collected is V. bat_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*(V bat+ -V bat- +0.3V, by selecting the resistance values ​​of resistors R7~R12, R15, and R16, V can be adjusted. bat_out The maximum voltage obtained should not exceed 3.3V, that is, the obtained V. bat_out The normal voltage range is 0.3V to 3.3V.

[0041] In addition, the maximum detectable BAT voltage in this embodiment is V. bat+ -V bat- =(V bat_out -0.3)*(R7+R8+R9+R10+R11+R12+R15) / R16=(3.3-0.3)*6075 / 8.2=2222V, the minimum detectable BAT voltage is V. bat+ -V bat- =(V bat_out -0.3)*(R7+R8+R9+R10+R11+R12+R15) / R16=(0.3-0.3)*6075 / 8.2=0V. The circuit designed in this embodiment can detect high voltage BAT of 0~2222V. The actual battery pack voltage range is 1040~1539.2V.

[0042] Taking the load circuit connected to the electrical device as the circuit to be tested as an example:

[0043] The voltage value of the circuit under test is V hv+ -V hv- =(V hv_out -0.3)*(R7+R8+R9+R10+R11+R12+R15) / R16, i.e., V hv+ -Vhv- =(V bat_out -0.3)*6075 / 8.2, corresponding to the voltage V obtained by the signal sampling branch. hv_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*(V hv+ -V hv- ) + 0.3V = 8.2 / 6075 * (V hv+ -V hv- +0.3V.

[0044] When the positive and negative terminals of the circuit under test are reversed, the voltage collected is V. hv_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*(V hv- -V hv+ +0.3V, where V hv- -V hv+ Much less than 0. The maximum voltage of the circuit to be detected in this embodiment is V. max_hv =3.7V * 416 = 1539.2V, the minimum voltage is V min_hv =2.5V * 416 = 1040V. When the positive and negative terminals of the circuit under test are reversed, the maximum reverse voltage is V. hv_out =8.2 / 6075*(-1539.2V)+0.3V=-1.778V<0V, minimum reverse voltage is V hv_out =8.2 / 6075*(-1040V)+0.3V=-1.104V<0V, both of which are less than the 0.3V bias voltage and less than 0. Therefore, it can be determined that the positive and negative terminals of the circuit under test are reversed.

[0045] When an open circuit occurs in the circuit under test, V hv+ -V hv- The voltage obtained is 0V, and the voltage is V. hv_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*0+0.3V, V hv_out =0.3V, the collected voltage is 0.3V, which is equal to the bias voltage. Therefore, it can be determined that there is a broken wire fault in the circuit under test.

[0046] When the circuit under test is fault-free, the voltage collected is V. hv_out =R16 / (R7+R8+R9+R10+R11+R12+R15)*(V hv+ -V hv- +0.3V, by selecting the resistance values ​​of resistors R7~R12, R15, and R16, V can be adjusted. hv_out The maximum voltage obtained should not exceed 3.3V, that is, the obtained V. hv_outThe normal voltage range is 0.3V to 3.3V.

[0047] In addition, the maximum detectable HV voltage in this embodiment is V. hv+ -V hv- =(V hv_out -0.3)*(R7+R8+R9+R10+R11+R12+R15) / R16=(3.3-0.3)*6075 / 8.2=2222V, minimum HV voltage is V hv+ -V hv- =(V hv_out -0.3)*(R7+R8+R9+R10+R11+R12+R15) / R16=(0.3-0.3)*6075 / 8.2=0V. The circuit designed in this embodiment can detect high voltage HV of 0~2222V. The actual load terminal voltage range is 1040~1539.2V.

[0048] Secondly, this application also provides a fault detection system, which includes at least the fault detection circuit from any of the above embodiments. Figure 3 , Figure 3 This is a schematic diagram of the main structure of a fault detection system according to an embodiment of this application. Figure 3 As shown, the fault detection system in this embodiment may include a main control chip, a high-voltage detection module (integrated fault detection circuit), a switch drive circuit, a battery pack, a load, and circuits such as main positive and main negative relays.

[0049] In this embodiment, the main control chip serves as the core of the BMS control system. It receives voltages from the battery terminal (BAT) and load terminal (HV) via a high-voltage detection module, and uses software algorithms to ensure the accuracy of the collected data. Based on the collected high-voltage signals, it performs relevant fault judgments and outputs relevant relay drive signals to control the on / off state of the high-voltage circuit. Optionally, in some embodiments, the main control chip includes, but is not limited to, a microcontroller or embedded chip. In this embodiment, the main control chip is an MCU. The high-voltage detection circuit, as a core component of the BMS, is primarily responsible for real-time monitoring of the high-voltage signals of BAT and HV, providing the system with accurate voltage data and safety protection functions. Furthermore, the high-voltage detection circuit also has a reverse connection detection function to prevent damage to components caused by reverse power connection, further improving the system's reliability and robustness. The main positive and main negative relays are key control switches for the high-voltage circuit, connected in series in the positive and negative main circuits of the battery pack, respectively. The main positive relay is mainly responsible for connecting or disconnecting the battery's power supply to the load; the main negative relay serves as a redundant protection switch for the system's main circuit, working in conjunction with the main positive relay to disconnect the high-voltage circuit in case of a fault, ensuring system safety. In a BMS (Battery Management System), the switch drive circuit is responsible for safely and reliably controlling the on / off operation of relays or contactors. Its core function is to convert the low-voltage control signal output from the main control chip into a power signal capable of driving high-voltage, high-current switching devices. The battery pack consists of multiple cells connected in series and parallel, forming the high-voltage DC power supply for the energy storage system. The load refers to all electrical systems powered by the battery pack and energy systems capable of charging the battery pack.

[0050] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.

Claims

1. A fault detection circuit, characterized in that, This includes operational amplifiers, bias voltage branches, supply voltage branches, and signal sampling branches, among which... The non-inverting input terminal of the operational amplifier is connected to the positive terminal of the circuit under test, and the inverting input terminal of the operational amplifier is connected to the negative terminal of the circuit under test. The bias voltage branch is connected to the non-inverting input of the operational amplifier; The power supply voltage branch is connected to the power supply pin of the operational amplifier; The signal sampling branch is connected to the output terminal of the operational amplifier; If the voltage value obtained by the signal sampling branch is within the range of the voltage value provided by the bias voltage branch and the voltage value provided by the power supply voltage branch, then the circuit under test is fault-free; if the voltage value obtained by the signal sampling branch is not within the range, then the circuit under test is faulty.

2. The fault detection circuit according to claim 1, characterized in that, The bias voltage branch includes a first voltage source, a first resistor, and a first capacitor, wherein, One end of the first resistor is connected to the first voltage source, and the other end of the first resistor and one end of the first capacitor are connected together to the non-inverting input of the operational amplifier. The other end of the first capacitor is grounded.

3. The fault detection circuit according to claim 1, characterized in that, The power supply voltage branch includes a second voltage source and a second capacitor, wherein... One end of the second capacitor and the second voltage source are connected together to one of the power supply pins of the operational amplifier, the other end of the second capacitor is grounded, and the other power supply pin of the operational amplifier is grounded.

4. The fault detection circuit according to claim 1, characterized in that, It also includes a feedback branch, one end of which is connected to the inverting input of the operational amplifier, and the other end of which is connected to the output of the operational amplifier.

5. The fault detection circuit according to claim 4, characterized in that, The feedback branch includes a second resistor and a third capacitor, wherein, The second resistor and the third capacitor are connected in parallel, and one end of the second resistor and one end of the third capacitor are connected to the inverting input terminal of the operational amplifier, while the other end of the second resistor and the other end of the third capacitor are connected to the output terminal of the operational amplifier.

6. The fault detection circuit according to claim 1, characterized in that, It also includes a first voltage divider branch and a second voltage divider branch. The first voltage divider branch includes several resistors connected in series, and the second voltage divider branch includes several resistors connected in series. One end of the first voltage divider branch is connected to the positive terminal of the circuit under test, and the other end of the first voltage divider branch is connected to the non-inverting input terminal of the operational amplifier. One end of the second voltage divider branch is connected to the negative terminal of the circuit under test, and the other end of the second voltage divider branch is connected to the inverting input terminal of the operational amplifier.

7. The fault detection circuit according to claim 6, characterized in that, It also includes a first inductor and a second inductor, wherein, The first inductor is connected in series with the first voltage divider branch and is located between the circuit to be tested and the first voltage divider branch; The second inductor is connected in series with the second voltage divider branch and is located between the circuit to be tested and the second voltage divider branch.

8. The fault detection circuit according to claim 7, characterized in that, It also includes a first filter circuit, which is disposed between the circuit to be detected and the first inductor and the second inductor. The first filter circuit includes a fourth capacitor and a fifth capacitor, wherein... One end of the fourth capacitor is connected to the positive terminal of the circuit under test, the other end of the fourth capacitor is connected to one end of the fifth capacitor, and the other end of the fifth capacitor is connected to the negative terminal of the circuit under test.

9. The fault detection circuit according to claim 7, characterized in that, It also includes a second filter circuit, one end of which is disposed between the first inductor and the first voltage divider branch, and the other end of which is disposed between the second inductor and the second voltage divider branch. The second filter circuit includes a sixth capacitor.

10. A fault detection system, characterized in that, The system includes at least the fault detection circuit according to any one of claims 1-9.

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