An active balancing matrix mos switch failure detection circuit

Abstract

The utility model discloses a kind of active equalization matrix MOS switch failure detection circuit, including chip U8: it is provided with battery negative end MOS detection enable signal pin SWEN1, battery positive end MOS detection enable signal pin SWEN2, MOS fault signal trigger pin SWFB, pin SWFB low level is effective, normal state is high level, pin SWFB is connected with VDD by pull-up;Optocoupler isolation module: including optocoupler U1, U2, U3, U4, connect with chip U8;MOS tube matrix: contain charge and discharge control MOS tube, connect with optocoupler isolation module;Digital isolator U7, for isolating transmission chip U8's high voltage fault signal to chip U6;Microcontroller chip U6, for issuing fault detection instruction and receiving fault information.This active equalization matrix MOS switch failure detection circuit is based on the fault trigger pin of equalization chip and optocoupler isolation mechanism design, build a set of circuit architecture simple, control logic simple, detection precision high and control efficiency optimal MOS switch failure detection system.

Description

Technical Field

[0001] This utility model relates to the field of detection circuit technology, specifically to an active equalization matrix MOS switch failure detection circuit. Background Technology

[0002] In an active balancing BMS system, it is necessary to continuously control the charging and discharging of individual batteries based on their voltage levels. This requires a large number of MOSFETs to switch the batteries between charging and discharging states. In the industry, active balancing charging and discharging is typically achieved using a switching matrix composed of discrete MOSFETs. If these MOSFETs fail, it poses a risk of short circuits to the batteries. Therefore, effectively detecting MOSFET failure is crucial for the safe operation of the entire system. Thus, an active balancing matrix MOSFET switch failure detection circuit needs to be designed. Utility Model Content

[0003] The purpose of this invention is to provide an active equalization matrix MOS switch failure detection circuit to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution: an active equalization matrix MOS switch failure detection circuit, comprising: Chip U8: It is equipped with a battery negative terminal MOS detection enable signal pin SWEN1, a battery positive terminal MOS detection enable signal pin SWEN2, and a MOS fault signal trigger pin SWFB. The SWFB pin is active low and normally high. The SWFB pin is pulled up to VDD. Optical isolation module: includes optical couplers U1, U2, U3, and U4, which are respectively connected to chip U8; MOS transistor matrix: contains charge and discharge control MOS transistors, and the MOS transistor matrix is ​​connected to the optocoupler isolation module; Digital isolator U7 is used to isolate the high-voltage fault signal of transmission chip U8 to chip U6. Chip U8 is connected to digital isolator U7 through the fault signal isolation transmission pin (Fault) and the serial communication isolation transmission pin (TXS, RXS). The microcontroller chip U6 is used to issue fault detection commands and receive fault information. Chip U6 is connected to the digital isolator U7 through the fault detection pin (Fault) and the serial communication pins (RXS, TXS).

[0005] Preferably, the chip U8 is a Gateron GT4801 chip, the negative terminal of the optocoupler U1 is connected to pin SWEN1, the positive terminal of the optocoupler U1 is connected to VDD through resistor R26, and the emitter of the optocoupler U1 is connected to the positive terminal of the optocoupler U2. The negative terminal of the optocoupler U2 is connected to the P- terminal, and the collector of the optocoupler U2 is connected to the SWFB pin. The collector of the optocoupler U4 is connected to the pin SWFB, and the positive terminal of the optocoupler U4 is connected to the emitter of the optocoupler U3. The negative terminal of the optocoupler U3 is connected to pin SWEN2 of the GT4801 chip U8, its positive terminal is connected to VDD through resistor R25, and its collector is connected to the P+ terminal.

[0006] Preferably, the MOS switch failure detection circuit is connected to the series battery pack, which is composed of individual cells Cell1, Cell2, ..., Celln connected in series, and the charge and discharge control MOS transistors include MOS transistors Q1-Q4n, where n is an integer greater than or equal to 3; The source (S) of MOSFET Q4i is connected to the source (S) of MOSFET Q(4i-1). The source (S) of MOSFET Q4i is connected to the source (S) of MOSFETs Q(4i-2) and Q(4i-3) through resistors R2i and R(2i-1). The gate (G) of MOSFETs Q4i, Q(4i-1), Q(4i-2), and Q(4i-3) is connected to the drive signal pin gA[i] of GT4801 chip U8. The drain (D) of MOSFET Q(4i-1) is connected to the positive terminal of the single cell Celli, and the drain (D) of MOSFET Q(4i-3) is connected to the negative terminal of Celli. i=1,…,n; The drain of the MOS transistor Q4i is connected to the P+ terminal, and the drain of the MOS transistor Q(4i-2) is connected to the P- terminal, i=1,…,n; The negative terminal of the optocoupler U4 is connected to the negative terminal of the single cell Cell1, and the collector of the optocoupler U1 is connected to the positive terminal of the single cell Celln.

[0007] Preferably, n=12.

[0008] The microcontroller U6 of this invention serves as the control core, primarily responsible for issuing equalization and fault detection commands, and reporting fault information to the display interface after receiving it. The digital signal isolator U7 constructs a safety isolation barrier between high-voltage and low-voltage areas, ensuring signal transmission while avoiding electrical interference and safety risks. The GT4801 chip U8 from Gateron implements the MOSFET fault detection function.

[0009] Compared with the prior art, the beneficial effects of this utility model are: This active equalization matrix MOS switch failure detection circuit is designed based on the fault trigger pin of the equalization chip and the optocoupler isolation mechanism. It constructs a MOS switch failure detection system with a simple circuit architecture, clear control logic, high detection accuracy and excellent control efficiency. Attached Figure Description

[0010] Figure 1This is the circuit for the active equalization matrix MOS switch failure detection circuit. Figure 1 ; Figure 2 This is the circuit for the active equalization matrix MOS switch failure detection circuit. Figure 2 ; Figure 3 A schematic diagram of the Q47 short-circuit failure circuit provided by this utility model; Figure 4 A schematic diagram of the short-circuit failure loop of Q47 and Q3 provided by this utility model; Figure 5 This is a schematic diagram of the Q2 short-circuit failure loop provided by this utility model; Figure 6 A schematic diagram of the short-circuit failure loop of Q2 and Q46 provided by this utility model. Detailed Implementation

[0011] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0012] Please see Figures 1-2 This utility model provides a technical solution: An active equalization matrix MOS switch failure detection circuit includes a GT4801 chip U8: it is equipped with a battery negative terminal MOS detection enable signal pin SWEN1, a battery positive terminal MOS detection enable signal pin SWEN2, and a MOS fault signal trigger pin SWFB. The SWFB pin is active low and normally high. The SWFB pin is pulled up to VDD. Optical isolation module: includes optical couplers U1, U2, U3, and U4, which are respectively connected to the GT4801 chip U8; MOS transistor matrix: contains charge / discharge control MOS transistors; Digital isolator U7 is used to isolate the high-voltage fault signal of transmission chip U8 to chip U6. Chip U8 is connected to digital isolator U7 through the fault signal isolation transmission pin (Fault) and the serial communication isolation transmission pin (TXS, RXS). The microcontroller chip U6 is used to issue fault detection commands and receive fault information. Chip U6 is connected to the digital isolator U7 through the fault detection pin (Fault) and the serial communication pins (RXS, TXS).

[0013] The pinout of the GT4801 chip is as follows: SWFB: MOS fault signal trigger pin of the GT4801 chip; SWEN1: Battery negative terminal MOS detection enable signal pin; SWEN2: Battery positive terminal MOS detection enable signal pin; gA[1]…gA

[12] : Drive signal pins of U8 in GT4801 chip.

[0014] The negative terminal of optocoupler U1 is connected to pin SWEN1, the positive terminal of optocoupler U1 is connected to VDD through resistor R26, the emitter of optocoupler U1 is connected to the positive terminal of optocoupler U2, the negative terminal of optocoupler U2 is connected to the P- terminal, and the collector of optocoupler U2 is connected to pin SWFB.

[0015] The collector of optocoupler U1 is connected to the drain of MOSFET Q47 and one end of Cell12. The other end of Cell12 is connected to the drain of MOSFET Q45. The other end of Cell1 is connected to the drain of MOSFET Q1 and the negative terminal of optocoupler U4.

[0016] The collector of optocoupler U4 is connected to pin SWFB, and the positive terminal of optocoupler U4 is connected to the emitter of optocoupler U3. The negative terminal of optocoupler U3 is connected to pin SWEN2 of GT4801 chip U8, its positive terminal is connected to VDD through resistor R25, and its collector is connected to the P+ terminal.

[0017] The MOS switch failure detection circuit is connected to the series battery pack, which is composed of individual cells Cell1, Cell2, ..., Cell12 connected in series. The charge and discharge control MOS transistors include MOS transistors Q1-Q48.

[0018] The drain of MOSFET Q48 and MOSFET Q4 is connected to the P+ terminal, the source of MOSFET Q48 is connected to the source of MOSFET Q47, the source of MOSFET Q48 is connected to the source of MOSFET Q46 and MOSFET Q45 through resistors R24 and R23, the drain of MOSFET Q46 and MOSFET Q2 is connected to the P- terminal, and the gate of MOSFET Q48, MOSFET Q47, MOSFET Q46 and MOSFET Q45 is connected to the drive signal gA of GT4801 chip U8

[12] .

[0019] The source of MOSFET Q4 is connected to the source of MOSFET Q3. The source of MOSFET Q4 is connected to the source of MOSFET Q2 and MOSFET Q1 through resistors R2 and R1. The gates of MOSFET Q4, MOSFET Q3, MOSFET Q2 and MOSFET Q1 are all connected to the drive signal gA of GT4801 chip U8[1].

[0020] Similarly, the source (S) of MOSFET Q24 is connected to the source (S) of MOSFET Q23. The source (S) of MOSFET Q24 is connected to the source (S) of MOSFETs Q22 and Q21 through resistors R12 and R11. The gate (G) of MOSFETs Q24, Q23, Q22, and Q21 is connected to the drive signal gA of GT4801 chip U8 [6]. The drain (D) of MOSFET Q23 is connected to the positive terminal of cell 6, the drain (D) of MOSFET Q21 is connected to the negative terminal of cell 6, the drain (D) of MOSFET Q24 is connected to the P+ terminal, and the drain (D) of MOSFET Q22 is connected to the P- terminal. The connection methods of other MOSFETs and cell batteries are similar.

[0021] Introduction to the failure detection principle of matrix MOS switches: The GT4801 chip U8 has SWEN1 as the MOS detection enable signal for the negative terminal (P-) of the battery, SWEN2 as the MOS detection enable signal for the positive terminal (P+) of the battery, and SWFB as the MOS fault signal trigger pin, which is active low and normally high.

[0022] Taking Q47 short-circuit failure as an example: like Figure 3 As shown, the GT4801 chip U8 self-test controls SWEN2 to output 0, and optocoupler U3 is turned on. At this time, P+ is pulled low. If MOSFET Q47 is short-circuited, Cell12+, Q47, Q48 body diode, P+, and Cell1- form a circuit, and the secondary side of optocoupler U4 is turned on, and SWFB is pulled low (the conduction circuit is shown in the green loop in the figure below), triggering the SWFB fault alarm of GT4801 chip U8. GT4801 chip U8 transmits the Fault signal to microcontroller (MCU) chip U6 through digital isolator U7. At the same time, the fault type is transmitted to microcontroller (MCU) chip U6 by the serial communication UART of GT4801 chip U8.

[0023] Taking the short-circuit failure of Q47 and Q3 as an example: like Figure 4As shown, the GT4801 chip U8 self-test controls SWEN2 to output 0, and optocoupler U3 is turned on. At this time, P+ is pulled low. If Q47 is short-circuited, Cell12+, Q47, Q48 body diodes, P+, and Cell1- form a circuit, and the secondary side of optocoupler U4 is turned on, and SWFB is pulled low (the circuit is shown in the green loop in the diagram below), triggering the SWFB fault alarm of the GT4801 chip U8. If Q3 is short-circuited, Cell1+, Q3, Q4 body diodes, P+, and B1- form a circuit, and the secondary side of optocoupler U4 is turned on, and SWFB is pulled low (the circuit is shown in the green loop on the right side of the diagram below), triggering the SWFB fault alarm of the GT4801 chip U8. The GT4801 chip U8 transmits the Fault signal to the microcontroller (MCU) chip U6 through the digital isolator U7. At the same time, the fault type is transmitted to the microcontroller (MCU) chip U6 by the serial communication UART of the GT4801 chip U8.

[0024] Taking Q2 short-circuit failure as an example: like Figure 5 As shown, the GT4801 chip U8 self-test controls SWEN1 to output 0, and optocoupler U1 is turned on. At this time, P- is pulled high. If Q2 is short-circuited, Cell12+, P-, Q2, Q1 body diode, and Cell1- form a circuit, and the secondary side of optocoupler U2 is turned on, and SWFB is pulled low (the circuit is shown in the green loop in the figure below), triggering the GT4801 chip U8 fault alarm. The GT4801 chip U8 transmits the Fault signal to the microcontroller (MCU) chip U6 through the digital isolator U7. At the same time, the fault type is transmitted to the microcontroller (MCU) chip U6 by the serial communication UART of the GT4801 chip U8.

[0025] Taking the short-circuit failure of Q2 and Q46 as an example: like Figure 6 As shown, the GT4801 chip U8 self-test controls SWEN1 to output 0, and optocoupler U1 is turned on, at which time P- is pulled high. If Q2 is short-circuited, Cell12+, P-, Q2, Q1 body diode, and Cell1- form a circuit, and the secondary side of optocoupler U2 is turned on, and SWFB is pulled low (the circuit is shown in the green loop in the diagram below), triggering the GT4801 chip U8 fault alarm. If Q46 is short-circuited, Cell12+, P-, Q46, Q45 body diode, and Cell12- form a circuit, and the secondary side of optocoupler U2 is turned on, and SWFB is pulled low (the circuit is shown in the green loop on the right side of the diagram below), triggering the GT4801 chip U8 fault alarm. The GT4801 chip U8 transmits the Fault signal to the microcontroller (MCU) chip U6 through the digital isolator U7, and at the same time, the fault type is transmitted to the microcontroller (MCU) chip U6 via the serial communication UART of the GT4801 chip U8.

[0026] The failure detection principle for other MOSFETs is the same as above.

[0027] Key component parameter list: This active equalization matrix MOS switch failure detection circuit is designed based on the fault trigger pin and optocoupler isolation mechanism of the equalization GT4801U8 chip. It constructs a MOS switch failure detection system with a simple circuit architecture, clear control logic, high detection accuracy and excellent control efficiency.

[0028] All parts not described in this utility model are the same as or can be implemented using existing technology. Although embodiments of this utility model have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this utility model, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A failure detection circuit for an active equalization matrix MOS switch, characterized in that: It includes: Chip U8: It is equipped with a battery negative terminal MOS detection enable signal pin SWEN1, a battery positive terminal MOS detection enable signal pin SWEN2, and a MOS fault signal trigger pin SWFB. The SWFB pin is active low and normally high. The SWFB pin is pulled up to VDD. Optical isolation module: includes optical couplers U1, U2, U3, and U4, which are respectively connected to chip U8; MOS transistor matrix: contains charge and discharge control MOS transistors, and the MOS transistor matrix is ​​connected to the optocoupler isolation module; Digital isolator U7 is used to isolate the high-voltage fault signal of transmission chip U8 to chip U6. Chip U8 is connected to digital isolator U7 through the fault signal isolation transmission pin (Fault) and the serial communication isolation transmission pin (TXS, RXS). The microcontroller chip U6 is used to issue fault detection commands and receive fault information. Chip U6 is connected to the digital isolator U7 through the fault detection pin (Fault) and serial communication pins (RXS, TXS).

2. The active equalization matrix MOS switch failure detection circuit according to claim 1, characterized in that: The chip U8 is a Gateron GT4801 chip. The negative terminal of the optocoupler U1 is connected to pin SWEN1, the positive terminal of the optocoupler U1 is connected to VDD through resistor R26, and the emitter of the optocoupler U1 is connected to the positive terminal of the optocoupler U2. The negative terminal of the optocoupler U2 is connected to the P- terminal, and the collector of the optocoupler U2 is connected to the SWFB pin. The collector of the optocoupler U4 is connected to the pin SWFB, and the positive terminal of the optocoupler U4 is connected to the emitter of the optocoupler U3. The negative terminal of the optocoupler U3 is connected to pin SWEN2 of the GT4801 chip U8, its positive terminal is connected to VDD through resistor R25, and its collector is connected to the P+ terminal.

3. The active equalization matrix MOS switch failure detection circuit according to claim 2, characterized in that: The MOS switch failure detection circuit is connected to the series battery pack, which is composed of individual cells Cell1, Cell2, ..., Celln connected in series. The charge and discharge control MOS transistors include MOS transistors Q1-Q4n, where n is an integer greater than or equal to 3. The source (S) of MOSFET Q4i is connected to the source (S) of MOSFET Q(4i-1). The source (S) of MOSFET Q4i is connected to the source (S) of MOSFETs Q(4i-2) and Q(4i-3) through resistors R2i and R(2i-1). The gate (G) of MOSFETs Q4i, Q(4i-1), Q(4i-2), and Q(4i-3) is connected to the drive signal pin gA[i] of GT4801 chip U8. The drain (D) of MOSFET Q(4i-1) is connected to the positive terminal of the single cell Celli, and the drain (D) of MOSFET Q(4i-3) is connected to the negative terminal of Celli. i=1,…,n; The drain of the MOS transistor Q4i is connected to the P+ terminal, and the drain of the MOS transistor Q(4i-2) is connected to the P- terminal, i=1,…,n; The negative terminal of the optocoupler U4 is connected to the negative terminal of the single cell Cell1, and the collector of the optocoupler U1 is connected to the positive terminal of the single cell Celln.

4. The active equalization matrix MOS switch failure detection circuit according to claim 3, characterized in that: n=12。

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