A broken line detection circuit based on analog quantity acquisition

Abstract

The utility model discloses a kind of broken line detection circuit based on analog quantity acquisition, it includes: signal conversion module, access analog quantity output port to receive analog quantity signal, for converting analog quantity signal into voltage signal uniformly;Negative voltage clamping module, the input end of connection signal conversion module, for when analog quantity output port has no output, the input of signal conversion module is clamped to negative voltage;Proportional amplification module, the output end of connection signal conversion module and access the ADC port of rear chip, for the output signal of signal conversion module is adjusted and input to rear chip and does acquisition processing;Comparator module, the output end of connection proportional amplification module and access the IO port of rear chip, for by comparing the output signal of proportional amplification module to generate high-low level signal input to rear chip and do broken line detection processing.The circuit structure of the application is simple, can realize the acquisition of analog quantity signal and identify the broken line fault of analog quantity.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a wire breakage detection circuit based on analog signal acquisition. Background Technology

[0002] In industrial automation, it is frequently necessary to acquire 0-10V / 4-20mA analog signals. When a disconnection occurs in this analog signal, an emergency shutdown or change in control mode is often required. An alarm should be triggered when the system experiences a static disconnection to prevent restarting with a fault. Currently, voltage-type or current-type analog signal sampling technologies primarily achieve analog signal sampling. While some technologies can detect disconnections, the circuitry is complex and can only detect disconnections in differential digital inputs, not analog signals. Utility Model Content

[0003] This utility model provides a circuit for detecting broken wires based on analog signal acquisition, which solves the problem that existing technologies cannot detect broken wires in analog signals.

[0004] This utility model embodiment provides a disconnection detection circuit based on analog signal acquisition, comprising: a signal conversion module, connected to an analog output port to receive analog signals, used to convert the analog signals into voltage signals; a negative voltage clamping module, connected to the input terminal of the signal conversion module, used to clamp the input of the signal conversion module to negative voltage when there is no output at the analog output port; a proportional amplifier module, connected to the output terminal of the signal conversion module and connected to the ADC port of a subsequent chip, used to adjust the output signal of the signal conversion module and input it to the subsequent chip for acquisition processing; and a comparator module, connected to the output terminal of the proportional amplifier module and connected to the IO port of the subsequent chip, used to generate high and low level signals by comparing the output signals of the proportional amplifier module and input them to the subsequent chip for disconnection detection processing.

[0005] Furthermore, it also includes a delay control module, which is connected to the negative pressure clamping module and is used to control the clamping of the signal conversion module input by the negative pressure clamping module.

[0006] Furthermore, the negative pressure clamping module includes a negative pressure power supply and a first resistor. The first end of the first resistor is connected between the input terminal of the signal conversion module and the analog output port, and the second end of the first resistor is connected to the negative pressure power supply.

[0007] Furthermore, the delay control module includes a second resistor, a third resistor, and a first optocoupler. The anode of the first optocoupler is connected to a power supply, and the cathode of the first optocoupler is connected to a control signal through the third resistor. The second end of the first resistor is connected to the negative voltage power supply via the collector and emitter of the first optocoupler. The second resistor is connected in parallel between the anode and cathode of the first optocoupler.

[0008] Furthermore, it also includes a voltage follower module, and the output of the proportional amplifier module is connected to the ADC port of the subsequent chip through the voltage follower module.

[0009] Furthermore, it also includes a first filtering module and a second filtering module, wherein the first filtering module is connected to the output terminal of the voltage follower module, and the second filtering module is connected to the output terminal of the comparator module.

[0010] Furthermore, the signal conversion module includes a jumper and a fourth resistor. The first end of the jumper is connected to the input terminal of the signal conversion module through the fourth resistor, and the second end of the jumper is grounded.

[0011] Furthermore, the proportional amplifier module includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first diode, a second diode, and a first operational amplifier. The non-inverting input terminal of the first operational amplifier is connected to the analog output port through the fifth resistor, the inverting input terminal is grounded through the seventh resistor, and the output terminal is connected to the anode of the first diode and the cathode of the second diode. The cathode of the first diode is connected to the ADC port of the subsequent chip and is connected to the inverting input terminal of the first operational amplifier through the ninth resistor. The anode of the second diode is connected to the inverting input terminal of the first operational amplifier through the eighth resistor.

[0012] Furthermore, the comparator module includes a first voltage comparator, a tenth resistor, an eleventh resistor, and a twelfth resistor. The non-inverting input of the first voltage comparator is connected to the output of the proportional amplifier module, and the inverting input is connected to a negative voltage power supply through the tenth resistor and grounded through the eleventh resistor. The output of the first voltage comparator is connected to one end of the twelfth resistor and connected to the IO port of the subsequent chip, and the other end of the twelfth resistor is connected to the power supply.

[0013] Furthermore, the comparator module includes a second operational amplifier, a tenth resistor, an eleventh resistor, and a twelfth resistor. The non-inverting input of the second operational amplifier is connected to the output of the proportional amplifier module, and the inverting input is connected to a negative voltage power supply through the tenth resistor and grounded through the eleventh resistor. The output of the second operational amplifier is connected to one end of the twelfth resistor and connected to the I / O port of the subsequent chip, and the other end of the twelfth resistor is connected to the inverting input of the second operational amplifier.

[0014] This utility model provides a disconnection detection circuit based on analog signal acquisition, comprising: a signal conversion module, connected to the analog output port to receive analog signals, used to convert analog signals into voltage signals; a negative voltage clamping module, connected to the input of the signal conversion module, used to clamp the input of the signal conversion module to negative voltage when there is no output at the analog output port; a proportional amplifier module, connected to the output of the signal conversion module and connected to the ADC port of the subsequent chip, used to adjust the output signal of the signal conversion module and input it to the subsequent chip for acquisition processing; and a comparator module, connected to the output of the proportional amplifier module and connected to the IO port of the subsequent chip, used to generate high and low level signals by comparing the output signals of the proportional amplifier module and input them to the subsequent chip for disconnection detection processing. This circuit achieves disconnection detection without affecting the analog signal sampling function and accuracy, effectively improving the stability, reliability, and safety of the equipment operation. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a structural block diagram of the circuit for detecting broken wires based on analog signal acquisition. Figure 2 This is another structural block diagram of the circuit for detecting broken wires based on analog signal acquisition; Figure 3 This is a circuit diagram of the open circuit detection circuit based on analog signal acquisition; Figure 4 This is another circuit diagram of the circuit for detecting broken wires based on analog signal acquisition; Figure 5 This is another circuit diagram of the circuit for detecting broken wires based on analog signal acquisition; The labels for the attached figures are as follows: 10. Signal conversion module; 20. Negative pressure clamping module; 21. Delay control module; 30. Proportional amplifier module; 40. Comparator module; 50. Voltage follower module; 60. First filter module; 70. Second filter module. Detailed Implementation

[0017] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0018] The directional terms used in this invention, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for explanation and understanding of this invention, and not for limiting it. Furthermore, in the accompanying drawings, structures that are similar or identical are indicated by the same reference numerals.

[0019] Reference Figures 1 to 5 This utility model provides a disconnection detection circuit based on analog signal acquisition. The structure and working principle of this circuit are described in detail below with reference to the accompanying drawings. The disconnection detection circuit includes: a signal conversion module 10, connected to an analog output port to receive analog signals and converting them into voltage signals; a negative voltage clamping module 20, connected to the input of the signal conversion module 10, clamping the input of the signal conversion module 10 to a negative voltage when there is no output at the analog output port; a proportional amplifier module 30, connected to the output of the signal conversion module 10 and connected to the ADC port of a subsequent chip, adjusting the output signal of the signal conversion module 10 and inputting it to the subsequent chip for acquisition processing; and a comparator module 40, connected to the output of the proportional amplifier module 30 and connected to the IO port of the subsequent chip, generating high and low level signals by comparing the output signals of the proportional amplifier module 30 and inputting them to the subsequent chip for disconnection detection processing.

[0020] In specific implementation, such as Figure 1As shown, the analog signal acquisition-based open circuit detection circuit mainly includes a signal conversion module 10, a negative voltage clamping module 20, a proportional amplifier module 30, and a comparator module 40. The input of the signal conversion module 10 is connected to an analog output port, which is a port on the instrument / device that generates the analog signal, such as the output of a current sensor in a power device. The analog output port outputs an analog signal, which can include current-type and voltage-type analog signals. Specifically, voltage-type analog signals are converted and transmitted using voltage transmission, while current-type analog signals are converted and transmitted using current transmission. The signal conversion module 10 can uniformly convert analog signals into voltage signals. When the analog signal provided by the analog output port is a current-type analog signal, it is converted into a voltage signal by the signal conversion module 10. If the analog signal provided by the analog output port is already a voltage-type analog signal, the signal conversion module 10 can output it as a voltage signal without changing its signal form. The negative pressure clamping module 20 is connected to the input terminal of the signal conversion module 10. Its function is to clamp the input of the signal conversion module 10 to negative voltage when there is no output at the analog output port, that is, when there is no analog signal output. The input side of the signal conversion module 10 is negative voltage.

[0021] Specifically, such as Figure 1 As shown, the proportional amplifier module 30 is connected to the output terminal of the signal conversion module 10 and then connected to the ADC port MCU_ADC of the subsequent chip. The subsequent chip is typically an MCU, and its ADC port is used as a signal acquisition port. The voltage signal output by the signal conversion module 10 is input to the proportional amplifier module 30. The proportional amplifier module 30 adjusts the output signal of the signal conversion module 10, that is, it adjusts the magnitude of the voltage signal output by the signal conversion module 10, bringing the voltage signal into a range that the subsequent chip can recognize. Then, the adjusted voltage signal is output to the subsequent chip for signal acquisition processing, so that the subsequent chip can acquire analog signals and realize the analog signal acquisition function.

[0022] Specifically, such as Figure 1 As shown, comparator module 40 is connected to the output of proportional amplifier module 30 and connected to the MCU_GPIO port of the subsequent chip. The IO port of the subsequent chip is used as a fault detection port. Comparator module 40 can generate high and low level signals by comparing the output signal of proportional amplifier module 30. Specifically, comparator module 40 compares the voltage signal regulated by proportional amplifier module 30 with a preset reference value, and outputs a high or low level signal based on the comparison result. The high and low level signals are input to the IO port of the subsequent chip, which performs fault detection processing. The subsequent chip determines whether the instrument / equipment generating the analog signal has a fault by checking the level status of the IO port.

[0023] In one embodiment, reference is made to Figure 2 It also includes a delay control module 21, which is connected to the negative pressure clamping module 20 and is used to control the clamping of the signal conversion module 10 input by the negative pressure clamping module 20.

[0024] In specific implementation, the circuit also includes a delay control module 21, which is connected to the input of the proportional amplifier module 30. Its function is to control the negative pressure clamping module 20 to clamp the input of the signal conversion module 10. In practical applications, analog signals are usually output by sensors within the instrument / equipment. Some sensor models have negative pressure protection. Since the negative pressure clamping module 20 clamps the input of the signal conversion module 10 to negative pressure, it also clamps the analog output port to negative pressure. Therefore, it is necessary to wait until the sensor power supply stabilizes before using the delay control module 21 to control the clamping of the signal conversion module 10's input by the negative pressure clamping module 20, ensuring that the input of the signal conversion module 10 is clamped to negative pressure. This prevents the instrument / equipment from stopping operation due to negative pressure protection.

[0025] Furthermore, referring to Figure 3 The negative pressure clamping module 20 includes a negative pressure power supply VSS and a first resistor R1. The first end of the first resistor R1 is connected between the input terminal of the signal conversion module 10 and the analog output port, and the second end of the first resistor R1 is connected to the negative pressure power supply VSS.

[0026] In specific implementation, the delay control module 21 can be composed of a first resistor R1 and a negative voltage power supply VSS. The first end of the first resistor R1 is connected to the input terminal of the signal conversion module 10, and the second end of the first resistor R1 is connected to the negative voltage power supply VSS. When an analog signal disconnection fault occurs, the analog output port has no output, and the first resistor R1 pulls down the input of the signal conversion module 10 to a negative voltage. For analog signal generation instruments / equipment that do not have a negative voltage protection function, the resistance value of the first resistor R1 should be relatively large, so that both the negative voltage and current are very small, minimizing the impact of the analog output disconnection and preventing damage to the components of the analog signal generation instrument / equipment.

[0027] Furthermore, referring to Figure 4 The delay control module 21 includes a second resistor R2, a third resistor R3, and a first optocoupler PC1. The anode of the first optocoupler PC1 is connected to a power supply, and the cathode of the first optocoupler PC1 is connected to a control signal through the third resistor R3. The second end of the first resistor R1 is connected to the negative voltage power supply VSS through the collector and emitter of the first optocoupler PC1. The second resistor R2 is connected in parallel between the anode and cathode of the first optocoupler PC1.

[0028] In specific implementations, when the analog signal generating instrument / equipment is equipped with a negative voltage protection function, the delay control module 21 also includes a second resistor R2, a third resistor R3, and a first optocoupler PC1. The anode of the first optocoupler PC1 is connected to the power supply VDD, and the cathode of the first optocoupler PC1 is connected to the control signal GPIO through the third resistor R3. The control signal can be issued by an external circuit, for example, driven by an external MCU. The second end of the first resistor R1 is connected to the negative voltage power supply VSS via the collector and emitter of the first optocoupler PC1. That is, the second end of the second resistor R2 is connected to the collector of the first optocoupler PC1, and the emitter of the first optocoupler PC1 is connected to the negative voltage power supply VSS. The second resistor R2 is connected in parallel between the anode and cathode of the first optocoupler PC1. In practical applications, controlling the on / off state of the first optocoupler PC1 via GPIO signals controls the input voltage of the signal conversion module 10. When the first optocoupler PC1 is off, the input of the signal conversion module 10 is normal. When the first optocoupler PC1 is on, the input of the signal conversion module 10 is pulled down to the negative voltage power supply VSS through the first resistor R1, thereby clamping the input of the signal conversion module 10 to a negative voltage. By controlling the GPIO signal, it is ensured that the power supply to the instrument / equipment generating analog signals is stable before turning on the first optocoupler PC1, thus clamping the input of the signal conversion module 10 to a negative voltage and preventing the instrument / equipment generating analog signals from triggering negative voltage protection and stopping operation.

[0029] In one embodiment, reference is made to Figure 1 and Figure 2 It also includes a voltage follower module 50, and the output terminal of the proportional amplifier module 30 is connected to the ADC port of the subsequent chip through the voltage follower module 50.

[0030] In a specific implementation, the circuit further includes a voltage follower module 50. The output of the proportional amplifier module 30 is connected to the ADC port of the subsequent chip through the voltage follower module 50. That is, the input of the voltage follower module 50 is connected to the output of the proportional amplifier module 30, and the output is connected to the ADC port of the subsequent chip. The function of the voltage follower module 50 is to perform voltage following on the output of the proportional amplifier module 30, match the impedance, improve the stability of the output signal, and enable the subsequent chip to acquire analog signals more accurately.

[0031] Furthermore, referring to Figure 3 and Figure 4The voltage follower module 50 includes a third operational amplifier U2 and a thirteenth resistor R10. The non-inverting input of the third operational amplifier U2 is connected to the output of the proportional amplifier module 30 through the thirteenth resistor R10. The inverting input of the third operational amplifier U2 is connected to the input. The output of the third operational amplifier U2 is connected to the ADC port of the subsequent chip.

[0032] In specific implementation, the voltage follower module 50 includes a third operational amplifier U2 and a thirteenth resistor R10. The non-inverting input terminal of the third operational amplifier U2 is connected to the output terminal of the proportional amplifier module 30 through the thirteenth resistor R10. The inverting input terminal of the third operational amplifier U2 is connected to its own input terminal, so that the output voltage follows the input voltage. The output terminal of the third operational amplifier U2 is connected to the ADC port of the subsequent chip.

[0033] In one embodiment, reference is made to Figure 1 and Figure 2 It also includes a first filter module 60 and a second filter module 70. The first filter module 60 is connected to the output terminal of the voltage follower module 50, and the second filter module 70 is connected to the output terminal of the comparator module 40.

[0034] In practical implementation, the open circuit detection circuit based on analog signal acquisition also includes a first filtering module 60 and a second filtering module 70. The first filtering module 60 is connected to the output terminal of the voltage follower module 50 and is used to filter the output signal of the voltage follower module 50 to reduce signal noise, making the signal input to the ADC port of the subsequent chip more stable and improving the accuracy of the analog signal acquisition by the subsequent chip. The second filtering module 70 is connected to the output terminal of the comparator module 40 and is used to filter the output signal of the comparator module 40 to make the analog signal input to the IO port of the subsequent chip more stable and improve the accuracy of the subsequent chip in identifying open circuit faults.

[0035] Furthermore, referring to Figure 3 and Figure 4 The first filter module 60 may include a fifteenth resistor R11 and a first capacitor C6, and the second filter module 70 may include a sixteenth resistor R15 and a second capacitor C8. The output of the voltage follower module 50 is connected to the ADC port of the subsequent chip through the fifteenth resistor R11, and one end of the first capacitor C6 is connected to one end of the fifteenth resistor R11, while the other end is grounded. The output of the comparator module 40 is connected to the IO port of the subsequent chip through the sixteenth resistor R15, and one end of the second capacitor C8 is connected to one end of the sixteenth resistor R15, while the other end is grounded.

[0036] In one embodiment, reference is made to Figure 3 and Figure 4The signal conversion module 10 includes a jumper J1 and a fourth resistor R4. The first end of the jumper J1 is connected to the input terminal of the signal conversion module 10 through the fourth resistor R4, and the second end of the jumper J1 is grounded.

[0037] In specific implementation, the signal conversion module 10 includes a jumper J1 and a fourth resistor R4. Jumper J1 is a connector with multiple independent pins. The first end of jumper J1 is connected to the input terminal of the signal conversion module 10 via the fourth resistor R4, and the second end of jumper J1 is grounded. In practical applications, when the input analog signal is current, jumper J1 is normally grounded, and the current can be converted to voltage via the fourth resistor R4. Adjusting the resistance value of the fourth resistor R4 can change the output voltage. For example, if the input analog signal is a 4-20mA current, a 500Ω fourth resistor R4 can convert the 4-20mA current signal to a voltage signal within the 0-10V range, thus unifying the input range. When the input analog signal is voltage, operating jumper J1 can disconnect the grounding of the fourth resistor R4, thus not affecting the input of the voltage-type analog signal to the subsequent modules.

[0038] In one embodiment, reference is made to Figure 3 and Figure 4 The proportional amplifier module 30 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first diode D2, a second diode D3, and a first operational amplifier U1. The non-inverting input terminal of the first operational amplifier U1 is connected to the analog output port through the fifth resistor R5, the inverting input terminal is grounded through the seventh resistor R7, and the output terminal is connected to the anode of the first diode D2 and the cathode of the second diode D3. The cathode of the first diode D2 is connected to the ADC port of the subsequent chip and is connected to the inverting input terminal of the first operational amplifier U1 through the ninth resistor R9. The anode of the second diode D3 is connected to the inverting input terminal of the first operational amplifier U1 through the eighth resistor R8.

[0039] In specific implementation, refer to Figure 3 and Figure 4The proportional amplifier module 30 mainly includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first diode D2, a second diode D3, and a first operational amplifier U1. The non-inverting input of the first operational amplifier U1 is connected to the analog output port through the fifth resistor R5 to input an analog signal. The inverting input of the first operational amplifier U1 is grounded through the seventh resistor R7. The output of the first operational amplifier U1 is connected to the anode of the first diode D2 and the cathode of the second diode D3. The cathode of the first diode D2 is connected to the ADC port of the subsequent chip and is connected to the inverting input of the first operational amplifier U1 through the ninth resistor R9. The anode of the second diode D3 is connected to the inverting input of the first operational amplifier U1 through the eighth resistor R8. The amplification ratio of the proportional amplifier module 30 can be set according to the input range of the analog signal and the recognition range of the ADC port of the subsequent chip. For example, if the input range of the analog signal is larger than the recognition range of the ADC port of the subsequent chip, the amplification ratio is set to less than 1. The first diode D2 switches the ninth resistor R9 as the feedback path for the first op-amp U1 when the input voltage signal is normal (i.e., a positive voltage). By properly setting the resistance value of the ninth resistor R9, the voltage signal can be amplified to a range recognizable by the ADC port of the subsequent chip. The second diode D3 switches the eighth resistor R8 as the feedback path for the first op-amp U1 when the input voltage is negative. By properly setting the resistance value of the eighth resistor R8, the negative voltage can be amplified, ensuring effective recognition after input to the comparator module 40. When the input analog signal is disconnected, the negative voltage generated cannot be transmitted to the ADC port of the subsequent chip due to the presence of the first diode D2, thus protecting the safety of the subsequent chip.

[0040] In one embodiment, reference is made to Figure 3 and Figure 4 The comparator module 40 includes a first voltage comparator U3, a tenth resistor R12, an eleventh resistor R13, and a twelfth resistor R14. The non-inverting input of the first voltage comparator U3 is connected to the output of the proportional amplifier module 30, and the inverting input is connected to the negative voltage power supply VSS through the tenth resistor R12 and grounded through the eleventh resistor R13. The output of the first voltage comparator U3 is connected to one end of the twelfth resistor R14 and connected to the IO port of the subsequent chip. The other end of the twelfth resistor R14 is connected to the power supply.

[0041] In specific implementation, the comparator module 40 is designed as a voltage comparator. The comparator module 40 includes a first voltage comparator U3, a tenth resistor R12, an eleventh resistor R13, and a twelfth resistor R14. The non-inverting input terminal of the first voltage comparator U3 is connected to the output terminal of the proportional amplifier module 30. The inverting input terminal of the first voltage comparator U3 is connected to the negative voltage power supply VSS through the tenth resistor R12 and is also connected to ground through the eleventh resistor R13. The output terminal of the first voltage comparator U3 is connected to one end of the twelfth resistor R14 and connected to the IO port of the subsequent chip. The other end of the twelfth resistor R14 is connected to the power supply VDD. In practical applications, the voltage signal output after adjustment by the proportional amplifier module 30 is transmitted to the non-inverting input terminal of the first voltage comparator U3. By adjusting the resistance values ​​of the tenth resistor R12 and the eleventh resistor R13, the Err level of the output signal of the first voltage comparator U3 can be flipped when the input signal changes significantly. When the input analog signal is normal and disconnected, the output terminal of the first voltage comparator U3 has different level states. The subsequent chip can identify and determine whether the input analog signal is disconnected based on the level state of the output terminal of the first voltage comparator U3.

[0042] In one embodiment, reference is made to Figure 5 The comparator module 40 includes a second operational amplifier U3, a tenth resistor R12, an eleventh resistor R13, and a twelfth resistor R14. The non-inverting input of the second operational amplifier U3 is connected to the output of the proportional amplifier module 30, and the inverting input is connected to the negative voltage power supply VSS through the tenth resistor R12 and grounded through the eleventh resistor R13. The output of the second operational amplifier U3 is connected to one end of the twelfth resistor R14 and connected to the IO port of the subsequent chip. The other end of the twelfth resistor R14 is connected to the inverting input of the second operational amplifier U3.

[0043] In practical implementation, the comparator module 40 is designed as a hysteresis comparator. The comparator module 40 includes a second operational amplifier U3, a tenth resistor R12, an eleventh resistor R13, and a twelfth resistor R14. The non-inverting input of the second operational amplifier U3 is connected to the output of the proportional amplifier module 30. The inverting input of the second operational amplifier U3 is connected to the negative voltage power supply VSS through the tenth resistor R12 and also connected to ground through the eleventh resistor R13. The output of the second operational amplifier U3 is connected to one end of the twelfth resistor R14 and then to the I / O port of the subsequent chip. The other end of the twelfth resistor R14 is connected to the inverting input of the second operational amplifier U3. In practical applications, the voltage signal output after adjustment by the proportional amplifier module 30 is transmitted to the non-inverting input of the second operational amplifier U3. By adjusting the resistance values ​​of the tenth resistor R12, the eleventh resistor R13, and the twelfth resistor R14, a reasonable hysteresis threshold can be set, allowing the Err level of the output signal of the second operational amplifier U3 to flip when the input signal changes significantly. When the input analog signal is normal or disconnected, the output of the second operational amplifier U3 will be at different levels. The subsequent chip can identify whether the input analog signal is disconnected based on the level of the output of the second operational amplifier U3.

[0044] In summary, the circuit of this application can realize the disconnection detection function without affecting the analog sampling function and accuracy, effectively improving the stability, reliability and safety of equipment operation.

[0045] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A circuit for detecting broken wires based on analog signal acquisition, characterized in that, include: The signal conversion module is connected to the analog output port to receive analog signals and is used to convert the analog signals into voltage signals. A negative pressure clamping module is connected to the input terminal of the signal conversion module and is used to clamp the input of the signal conversion module to negative pressure when there is no output at the analog output port. A proportional amplifier module is connected to the output terminal of the signal conversion module and to the ADC port of the subsequent chip. It is used to adjust the output signal of the signal conversion module and input it to the subsequent chip for acquisition and processing. The comparator module is connected to the output of the proportional amplifier module and to the I / O port of the subsequent chip. It is used to generate high and low level signals by comparing the output signal of the proportional amplifier module and input them to the subsequent chip for disconnection detection.

2. The open circuit detection circuit based on analog signal acquisition according to claim 1, characterized in that, It also includes a delay control module, which is connected to the negative pressure clamping module and is used to control the clamping of the signal conversion module input by the negative pressure clamping module.

3. The open circuit detection circuit based on analog signal acquisition according to claim 2, characterized in that, The negative pressure clamping module includes a negative pressure power supply and a first resistor. The first end of the first resistor is connected between the input terminal of the signal conversion module and the analog output port, and the second end of the first resistor is connected to the negative pressure power supply.

4. The open circuit detection circuit based on analog signal acquisition according to claim 3, characterized in that, The delay control module includes a second resistor, a third resistor, and a first optocoupler. The anode of the first optocoupler is connected to a power supply, and the cathode of the first optocoupler is connected to a control signal through the third resistor. The second end of the first resistor is connected to the negative voltage power supply through the collector and emitter of the first optocoupler. The second resistor is connected in parallel between the anode and cathode of the first optocoupler.

5. The open circuit detection circuit based on analog signal acquisition according to any one of claims 1-4, characterized in that, It also includes a voltage follower module, and the output of the proportional amplifier module is connected to the ADC port of the subsequent chip through the voltage follower module.

6. The open circuit detection circuit based on analog signal acquisition according to claim 5, characterized in that, It also includes a first filtering module and a second filtering module, wherein the first filtering module is connected to the output terminal of the voltage follower module and the second filtering module is connected to the output terminal of the comparator module.

7. The open circuit detection circuit based on analog signal acquisition according to any one of claims 1-4, characterized in that, The signal conversion module includes a jumper and a fourth resistor. The first end of the jumper is connected to the input terminal of the signal conversion module through the fourth resistor, and the second end of the jumper is grounded.

8. The open circuit detection circuit based on analog signal acquisition according to any one of claims 1-4, characterized in that, The proportional amplifier module includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first diode, a second diode, and a first operational amplifier. The non-inverting input of the first operational amplifier is connected to the analog output port through the fifth resistor, and the inverting input is grounded through the seventh resistor. The output is connected to the anode of the first diode and the cathode of the second diode. The cathode of the first diode is connected to the ADC port of the subsequent chip and is connected to the inverting input of the first operational amplifier through the ninth resistor. The anode of the second diode is connected to the inverting input of the first operational amplifier through the eighth resistor.

9. The open circuit detection circuit based on analog signal acquisition according to any one of claims 1-4, characterized in that, The comparator module includes a first voltage comparator, a tenth resistor, an eleventh resistor, and a twelfth resistor. The non-inverting input of the first voltage comparator is connected to the output of the proportional amplifier module, and the inverting input is connected to a negative voltage power supply through the tenth resistor and grounded through the eleventh resistor. The output of the first voltage comparator is connected to one end of the twelfth resistor and connected to the I / O port of the subsequent chip, and the other end of the twelfth resistor is connected to the power supply.

10. The open circuit detection circuit based on analog signal acquisition according to any one of claims 1-4, characterized in that, The comparator module includes a second operational amplifier, a tenth resistor, an eleventh resistor, and a twelfth resistor. The non-inverting input of the second operational amplifier is connected to the output of the proportional amplifier module, and the inverting input is connected to a negative voltage power supply through the tenth resistor and grounded through the eleventh resistor. The output of the second operational amplifier is connected to one end of the twelfth resistor and connected to the I / O port of the subsequent chip. The other end of the twelfth resistor is connected to the inverting input of the second operational amplifier.

Images