A detection system for intelligent network connection whole vehicle CAN communication fault

Abstract

The utility model relates to CAN bus detection field, concretely relates to a kind of detection system for intelligent network connection whole car CAN communication fault, including CAN bus, CAN transceiver circuit, FPGA and host computer;The FPGA is monitored CAN bus data by CAN transceiver circuit, and is connected with host computer communication;Clock management unit, configuration unit, CAN controller unit, error detection unit and UPD sending unit are provided in FPGA by hardware language setting.There is CAN communication fault detection system provided by the utility model, and the communication state of CAN bus is realized by CAN transceiver circuit and is collected in real time, and FPGA sets up fault detection unit by hardware language, and the data of transceiver module is analyzed in real time and is automatically classified by fault detection unit, and fault point can be positioned quickly, and the diagnostic efficiency is greatly improved.Data processing result can be transmitted to host computer by UDP sending unit, realize remote monitoring and management, guarantee the operation safety of system, and provide operation and maintenance efficiency.

Description

Technical Field

[0001] This utility model relates to the field of CAN bus detection, specifically to a detection system for CAN communication faults in intelligent connected vehicles. Background Technology

[0002] With the rapid advancement of automotive intelligence and connectivity technologies, the vehicle CAN communication system has gradually become a key technology for intelligent connected vehicles to achieve vehicle control, real-time monitoring, and inter-module information exchange. Due to its high reliability, real-time performance, and anti-interference capabilities, the CAN bus is widely used in modern automotive electronic and electrical architectures. Multiple important functional modules within the vehicle (such as sensors, gateways, and control units) work collaboratively through the CAN bus to achieve data sharing and command communication throughout the vehicle. However, the vehicle CAN communication system frequently faces the threat of failure in complex operating environments, directly affecting the stability and safety of vehicle functions. Utility Model Content

[0003] The purpose of this utility model is to provide a detection system for CAN communication faults in intelligent connected vehicles to solve the problems mentioned in the background art. The system includes a CAN bus, a CAN transceiver circuit, an FPGA, and a host computer. The FPGA listens to CAN bus data through the CAN transceiver circuit and communicates with the host computer. The FPGA is equipped with a clock management unit, a configuration unit, a CAN controller unit, an error detection unit, and a UPD transmission unit, all configured in hardware.

[0004] Furthermore, the CAN transceiver circuit includes a CAN transceiver chip and its peripheral circuits, the peripheral circuits including power filtering and communication interface protection circuits and CAN bus protection circuits.

[0005] Furthermore, the power filtering and communication interface protection circuit includes a capacitor C1 and a Zener diode DZ1. The two ends of the capacitor C1 are connected to the GND and VCC terminals of the CAN transceiver chip, respectively. The negative terminal of the Zener diode DZ1 is connected to the VCC terminal of the CAN transceiver chip, and the positive terminal is connected to the GND terminal of the CAN transceiver chip. The VCC terminal of the CAN transceiver chip is connected to a 3.3V power supply, and the GND terminal is grounded.

[0006] Furthermore, the CAN bus protection circuit includes a common-mode inductor L-GM1, diodes D1, D2, D3, D4, D5, D6, a bidirectional TVS diode DR1, resistors R1, R2, R3, R4, capacitor C2, and glass diodes S1 and S2. Diodes D1, D2, D3, D4, and bidirectional TVS diode DR1 form a bridge diode array connected to the CANH and CANL ports of the CAN transceiver chip, and are connected to the CANH and CANL terminals of the bus via resistors R1 and R2. A glass diode S1 and resistor R4 are connected in parallel between the CANH and CANL terminals of the CAN bus, and the CANL terminal of the CAN bus is connected to the common ground PE via glass diode S2. Resistor R3 is connected in parallel with capacitor C2, and its two ends are connected to the CANG terminal of the CAN transceiver chip and the common ground PE, respectively. The anode of diode D5 is connected to the CANG terminal of the CAN transceiver chip, and the cathode is connected to the cathode of diode D1. The cathode of diode D6 is connected to the CANG terminal of the CAN transceiver chip, and the anode is connected to the anode of diode D2.

[0007] Furthermore, the FPGA also includes peripheral circuitry, which includes a JTAG circuit, a crystal oscillator circuit, and a power supply circuit. Beneficial effects

[0008] The CAN communication fault detection system provided by this invention uses a CAN transceiver circuit to collect the communication status of the CAN bus in real time. An FPGA, configured via hardware language, sets up a fault detection unit to analyze and automatically classify the data from the transceiver module in real time, enabling rapid fault location and significantly improving diagnostic efficiency. The data processing results can be transmitted to a host computer via a UDP sending unit, enabling remote monitoring and management, ensuring system operational security, and improving maintenance efficiency.

[0009] This invention also provides a CAN transceiver circuit, which can effectively improve the system's reliability, anti-interference ability and stability while realizing CAN bus communication function. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the overall module of this utility model; Figure 2 This is a circuit diagram of the CAN transceiver circuit of this utility model; Detailed Implementation

[0011] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model. Example 1:

[0012] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0013] like Figure 1 As shown in the figure, this embodiment provides a detection system for CAN communication faults in intelligent connected vehicles, including: CAN bus: As the main data transmission channel for vehicle communication, it is used to realize data exchange between in-vehicle devices.

[0014] CAN transceiver circuit: responsible for converting the differential electrical signals of the CAN bus into digital signals that can be processed by the FPGA, and sending digital signals to the CAN bus.

[0015] FPGA core module: The core processing platform of the entire system, which includes several key unit modules for fault detection, data processing and communication control.

[0016] Host computer: The system's monitoring and control terminal, used to receive fault detection information and data feedback from the FPGA. It interacts with the FPGA via a UDP interface, receives and analyzes fault detection results, and performs functions such as remote monitoring, configuration management, data storage, and reporting.

[0017] The FPGA serves as the central processing unit of the system, integrating and managing the following functional modules: Time Management Unit: Time synchronization is crucial in CAN communication fault detection. The time management unit provides a precise time base to mark the time of fault occurrence, enabling data recording and processing.

[0018] CAN controller: Responsible for parsing and monitoring the data from the CAN transceiver module.

[0019] By filtering and parsing CAN bus messages, valid data is extracted, and it is analyzed whether there are communication faults such as short circuits, bit errors, and data packet loss.

[0020] Configuration unit: Provides configurable parameters (such as communication rate, fault detection threshold, etc.) for the system to adapt to different vehicle architectures and CAN bus protocols (such as CAN2.0 and CANFD).

[0021] Fault detection unit: It can detect, classify and locate faults in the CAN bus and transceiver circuits, including problems such as broken signal lines, short circuits, and damage to differential signals.

[0022] UDP Transmitting Unit: Transmits detected fault information and CAN data to the host computer via the UDP protocol for remote monitoring and fault management.

[0023] In addition to the internal units configured via hardware languages ​​mentioned above, the FPGA chip also includes some peripheral circuits, specifically: JTGA (Joint Test Action Group Interface): Provides a debugging interface for FPGAs, used for developing, debugging, and maintaining the internal logic of FPGAs online.

[0024] Crystal oscillator module: Provides the clock source required for system operation, and is used to maintain high-precision timing for CAN communication and other modules.

[0025] Power module: Provides a stable power supply for the FPGA and peripheral circuits to ensure normal operation.

[0026] The detection process is as follows: The CAN bus transmits vehicle communication data to the CAN transceiver circuit, which converts the differential signal into a digital signal and then transmits it to the FPGA. The FPGA's CAN controller parses the received data packets and transmits them to the fault detection unit for status monitoring. The fault detection unit analyzes in real time whether there are faults in the CAN bus and transceiver circuit (such as short circuits, bit errors, signal loss, etc.). The time management unit records the fault time for easy trajectory tracing and analysis. The configuration unit ensures that the system can flexibly adjust parameters according to specific usage scenarios (protocol type, rate requirements, etc.). The FPGA uploads the data packets and fault detection results to the host computer via the UDP sending unit. The host computer analyzes and stores the received data for remote monitoring and subsequent maintenance. Example 2:

[0027] This embodiment provides a specific scheme for the CAN transceiver circuit in Embodiment 1, such as... Figure 2 As shown. The CAN transceiver chip uses the CTM8251KT chip, with power filtering and communication interface protection circuitry on the left side and CAN bus protection circuitry on the right side. Specifically: The power filtering and communication interface protection circuit includes a capacitor C1 and a Zener diode DZ1. The two ends of the capacitor C1 are connected to the GND and VCC terminals of the CAN transceiver chip, respectively. The negative terminal of the Zener diode DZ1 is connected to the VCC terminal of the CAN transceiver chip, and the positive terminal is connected to the GND terminal of the CAN transceiver chip. The VCC terminal of the CAN transceiver chip is connected to a 3.3V power supply, and the GND terminal is grounded.

[0028] The CAN bus protection circuit includes a common-mode inductor L-GM1, diodes D1, D2, D3, D4, D5, D6, a bidirectional TVS diode DR1, resistors R1, R2, R3, R4, a capacitor C2, and glass diodes S1 and S2. Diodes D1, D2, D3, D4, and bidirectional TVS diode DR1 form a bridge diode array connected to the CANH and CANL ports of the CAN transceiver chip, and are connected to the CANH and CANL terminals of the bus via resistors R1 and R2. A glass diode S1 and resistor R4 are connected in parallel between the CANH and CANL terminals of the CAN bus, and the CANL terminal of the CAN bus is connected to the common ground PE via glass diode S2. Resistor R3 is connected in parallel with capacitor C2, and its two ends are connected to the CANG terminal of the CAN transceiver chip and the common ground PE, respectively. The anode of diode D5 is connected to the CANG terminal of the CAN transceiver chip, and the cathode is connected to the cathode of diode D1. The cathode of diode D6 is connected to the CANG terminal of the CAN transceiver chip, and the anode is connected to the anode of diode D2.

[0029] The circuit technology can achieve the following functions: CAN bus core communication: The CTM8251KTCAN transceiver is used to implement differential signal transmission and reception functions to build CAN bus physical layer communication.

[0030] Signal protection: Transient overvoltage, differential signal interference and high-frequency noise are suppressed by TVS diode array (D1-D6), filter inductor (L-GM) and filter capacitor (C2).

[0031] Fault detection: The switches (S1, S2) and monitoring design are responsible for real-time detection of short circuits, open circuits and signal abnormalities.

[0032] Grounding protection and voltage regulation: By configuring Zener diodes (DZ1), grounding (PE) and voltage regulation filtering devices, the circuit operation is ensured to be stable and external interference is prevented from damaging key components.

[0033] The circuit scheme provided in this embodiment efficiently integrates several core functions such as protection, detection, and communication, which can significantly improve the communication reliability, security, and fault diagnosis capability of the CAN bus, and has broad application value and development potential in the fields of intelligent connected vehicles and industrial Internet of Things.

[0034] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A detection system for CAN communication faults in intelligent connected vehicles, characterized in that: It includes a CAN bus, a CAN transceiver circuit, an FPGA, and a host computer; the FPGA listens to CAN bus data through the CAN transceiver circuit and communicates with the host computer; the FPGA has a clock management unit, a configuration unit, a CAN controller unit, an error detection unit, and a UPD transmission unit configured in hardware language. The CAN transceiver circuit includes a CAN transceiver chip and its peripheral circuits, the peripheral circuits including power filtering and communication interface protection circuits and CAN bus protection circuits; The CAN bus protection circuit includes a common-mode inductor L-GM1, diodes D1, D2, D3, D4, D5, D6, a bidirectional TVS diode DR1, resistors R1, R2, R3, R4, a capacitor C2, and glass diodes S1 and S2. Diodes D1, D2, D3, D4, and the bidirectional TVS diode DR1 form a bridge diode array connected to the CANH and CANL ports of the CAN transceiver chip, and are connected to the CANH and CANL terminals of the bus via resistors R1 and R2. A glass diode S1 and a resistor R4 are connected in parallel between the CANH and CANL terminals of the CAN bus, and the CANL terminal of the CAN bus is connected to the common ground PE via glass diode S2. Resistor R3 and capacitor C2 are connected in parallel, with their two ends connected to the CANG terminal of the CAN transceiver chip and the common ground PE, respectively. The anode of diode D5 is connected to the CANG terminal of the CAN transceiver chip, and the cathode is connected to the cathode of diode D1. The cathode of diode D6 is connected to the CANG terminal of the CAN transceiver chip, and the anode is connected to the anode of diode D2.

2. The CAN communication fault detection system according to claim 1, characterized in that: The power filtering and communication interface protection circuit includes a capacitor C1 and a Zener diode DZ1. The two ends of the capacitor C1 are connected to the GND and VCC terminals of the CAN transceiver chip, respectively. The negative terminal of the Zener diode DZ1 is connected to the VCC terminal of the CAN transceiver chip, and the positive terminal is connected to the GND terminal of the CAN transceiver chip. The VCC terminal of the CAN transceiver chip is connected to a 3.3V power supply, and the GND terminal is grounded.

3. The CAN communication fault detection system according to claim 1, characterized in that: The FPGA also includes peripheral circuitry, which includes a JTAG circuit, a crystal oscillator circuit, and a power supply circuit.

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