A clock adaptive flexible configuration circuit

Abstract

The utility model relates to a flexible configuration circuit of clock self -adaptation, including input clock module, programmable clock chip, control module, clock distribution module, FPGA load module and power module, input clock module is connected with programmable clock chip, control module programmable clock chip connects, programmable clock chip is connected with clock distribution module, clock distribution module is connected with FPGA load module, power module is connected with input clock module, programmable clock chip, control module, clock distribution module and FPGA load module respectively, realized the double selection function of clock source and the full link adaptation of clock signal, input clock module provides two kinds of selection of local crystal oscillator and external clock, control module can switch clock type and configure programmable clock chip flexibly, finally through clock distribution module will stable configuration after clock accurate supply multiple FPGAs, satisfies the differentiating demand of FPGA load to clock signal under different scenes, improves the versatility and adaptability of circuit.

Description

Technical Field

[0001] This utility model relates to the field of clock technology, and in particular to a flexible configuration circuit for clock self-adaptation. Background Technology

[0002] Processor chips on various circuit boards require a clock to operate, and external interfaces such as fiber optic cables also need a reference clock. Clock implementations on these boards can use fixed-frequency crystal oscillators or programmable clock chips like the CMCD6208. Typically, programmable clock chips are configured upon power-on and cannot be changed during operation. This limits the operating frequency of the processor or the transmission baud rate of the interface, especially the fiber optic interface speed. Users often connect fiber optic cables of various speeds to the board. To ensure proper communication across these cables, the speed of each fiber optic cable needs to be configured online to adapt to the speed of the connected devices. Current technology is not flexible enough; it either uses a crystal oscillator or configures the CMCD6208 to output a specific clock. Utility Model Content

[0003] The purpose of this invention is to provide a clock-adaptive, flexible configuration circuit to solve the problems existing in the prior art.

[0004] The above-mentioned technical objective of this utility model is achieved through the following technical solution:

[0005] A clock-adaptive flexible configuration circuit includes an input clock module, a programmable clock chip, a control module, a clock distribution module, an FPGA load module, and a power supply module. The input clock module is connected to the programmable clock chip and provides a local crystal oscillator clock or an external input clock to the programmable clock chip. The control module, connected to the programmable clock chip, outputs control signals to select the input clock type of the programmable clock chip. The programmable clock chip is connected to the clock distribution module and transmits the configured clock signal to the clock distribution module. The clock distribution module is connected to the FPGA load module and distributes the clock signal to each FPGA chip. The power supply module is connected to the input clock module, the programmable clock chip, the control module, the clock distribution module, and the FPGA load module to provide operating power.

[0006] By adopting the above technical solution, dual clock source selection and end-to-end clock signal adaptation are achieved. The input clock module provides two options: a local crystal oscillator and an external clock. The control module can flexibly switch clock types and configure programmable clock chips. Finally, the clock distribution module accurately supplies the stable configured clock to multiple FPGAs, meeting the differentiated clock signal requirements of FPGA loads in different scenarios and improving the circuit's versatility and adaptability.

[0007] In a further embodiment, the input clock module includes a local crystal oscillator output pin and an external clock input / output pin; the local crystal oscillator output pin is connected to a programmable clock chip for transmitting the local crystal oscillator clock; the external clock input / output pin is connected to the programmable clock chip for transmitting the external input clock.

[0008] By adopting the above technical solution, the local crystal oscillator output pin directly provides a stable built-in clock source for the programmable clock chip, while the external clock input / output pin provides an interface for receiving external clock signals. At the same time, the input / output design of this pin reserves space for subsequent expansion of the clock signal inverted output function, further enhancing the flexibility of clock source selection and the scalability of the circuit.

[0009] In a further embodiment, the programmable clock chip includes XTAL_IN, EXT_CLK_IN, REF_SEL, SCLK, SDI, SDO, CSB, OUT0, and VDD; XTAL_IN is connected to the local crystal oscillator output pin of the input clock module; EXT_CLK_IN is connected to the external clock input / output pin of the input clock module; REF_SEL is connected to the control module; SCLK is connected to the control module; SDI is connected to the control module; SDO is connected to the control module; CSB is connected to the control module; OUT0 is connected to the clock distribution module; and VDD is connected to the power supply module.

[0010] By adopting the above technical solution, XTAL_IN and EXT_CLK_IN ensure that the two clock sources can be accurately connected, REF_SEL and SPI related pins allow the control module to accurately send clock selection commands and configuration parameters, and OUT0 transmits the configured stable clock signal to the clock distribution module, ensuring reliable transmission of control commands and clock signals at the chip level and laying the hardware foundation for clock adaptive configuration.

[0011] In a further embodiment, the control module includes REF_SEL_OUT, SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_CS, RED_LED, GREEN_LED, and VDD3.3; REF_SEL_OUT is connected to the REF_SEL of the programmable clock chip and is used to output high and low level signals to control the programmable clock chip to select the input clock type; SPI_SCLK is connected to the SCLK of the programmable clock chip and is used to transmit the SPI communication clock signal; SPI_MOSI is connected to the SDI of the programmable clock chip and is used to send configuration commands to the programmable clock chip; SPI_MISO is connected to the REF_SEL of the programmable clock chip... The SDO connection is used to receive status data from the programmable clock chip; the SPI_CS connection is connected to the CSB of the programmable clock chip to control the start and stop of SPI communication; the RED_LED is connected to the cathode of the external red indicator light through a current-limiting resistor, and the anode of the red indicator light is connected to the 3.3V_OUT of the power module to control the red indicator light to indicate configuration failure; the GREEN_LED is connected to the cathode of the external green indicator light through a current-limiting resistor, and the anode of the green indicator light is connected to the 3.3V_OUT of the power module to control the green indicator light to indicate configuration success; the VDD3.3 connection is connected to the 3.3V_OUT of the power module to receive 3.3V operating power.

[0012] By adopting the above technical solution, REF_SEL_OUT directly determines the clock type through high and low levels, the SPI communication pin ensures bidirectional transmission of configuration commands, sending commands and receiving status, and RED_LED and GREEN_LED intuitively reflect the configuration success or failure status through their on / off state. The circuit status can be quickly determined without additional detection equipment, which greatly improves the accuracy of clock configuration and the efficiency of fault diagnosis.

[0013] In a further embodiment, the clock distribution module includes CLK_IN, CLK_OUT1, CLK_OUT2, CLK_OUT3, CLK_OUT4, and VDD; CLK_IN is connected to OUT0 of the programmable clock chip and is used to receive the configured clock signal output by the programmable clock chip; CLK_OUT1 is connected to FPGA1_CLK of the FPGA load module; CLK_OUT2 is connected to FPGA2_CLK of the FPGA load module; CLK_OUT3 is connected to FPGA3_CLK of the FPGA load module; CLK_OUT4 is connected to FPGA4_CLK of the FPGA load module, and CLK_OUT1 to CLK_OUT4 are used to distribute the clock signal to each FPGA chip; VDD is connected to 1.8V_OUT of the power supply module and is used to receive 1.8V operating power.

[0014] By adopting the above technical solution, after CLK_IN receives the same clock output from the programmable clock chip, it is accurately distributed to the four FPGAs through CLK_OUT1 to CLK_OUT4, ensuring that the clock signal obtained by each FPGA has high synchronization and strong stability, avoiding FPGA malfunctions caused by clock inconsistency, and perfectly adapting to the clock supply requirements of multiple FPGA loads.

[0015] In a further embodiment, the FPGA load module includes FPGA1_CLK, FPGA2_CLK, FPGA3_CLK, FPGA4_CLK, and VDD; FPGA1_CLK is connected to CLK_OUT1 of the clock distribution module; FPGA2_CLK is connected to CLK_OUT2 of the clock distribution module; FPGA3_CLK is connected to CLK_OUT3 of the clock distribution module; and FPGA4_CLK is connected to CLK_OUT4 of the clock distribution module. FPGA1_CLK to FPGA4_CLK are used to receive the allocated clock signal; VDD is connected to 1.8V_OUT of the power supply module and is used to receive 1.8V operating power.

[0016] By adopting the above technical solution, the output pins of FPGA1_CLK to FPGA4_CLK correspond one-to-one with the clock distribution module, avoiding incorrect clock signal connection. At the same time, the 1.8V power input matches the voltage requirements of the FPGA, providing support for the FPGA to work normally under the dual protection of stable clock and compatible power supply, and ensuring the reliability of the load module.

[0017] In a further embodiment, the power supply module includes 3.3V_OUT and 1.8V_OUT; the 3.3V_OUT is connected to the power supply pin of the input clock module, the VDD of the programmable clock chip, and the VDD3.3 of the control module, respectively, to provide a 3.3V operating power supply; the 1.8V_OUT is connected to the VDD of the clock distribution module and the VDD of the FPGA load module, respectively, to provide a 1.8V operating power supply.

[0018] By adopting the above technical solution, 3.3V_OUT matches the voltage requirements of the input clock module, programmable clock chip and control module, and 1.8V_OUT adapts to the voltage specifications of the clock distribution module and FPGA load module, avoiding module damage or abnormal operation caused by voltage mismatch. At the same time, the voltage output can reduce power interference between different modules and ensure the stability and safety of the power supply of the entire circuit.

[0019] In summary, this utility model has the following beneficial effects:

[0020] 1. By ensuring that the output pins of the clock distribution module correspond one-to-one with those of FPGA1_CLK to FPGA4_CLK, clock signal misconnection is avoided. At the same time, the 1.8V power input matches the voltage requirements of the FPGA, providing support for the FPGA to work normally under the dual protection of stable clock and compatible power supply, thus ensuring the reliability of the load module. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall principle of this utility model. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings.

[0023] Identical parts are indicated by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "upper," and "lower" used in the following description refer to the attached figures. Figure 1 In this specification, the terms "bottom surface" and "top surface," "inner" and "outer" refer to the direction toward or away from the geometry of a specific component. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this specification, "a plurality of" means two or more, unless otherwise explicitly and specifically defined by the direction of the center.

[0024] Example 1:

[0025] like Figure 1As shown, a clock-adaptive flexible configuration circuit includes an input clock module, a programmable clock chip, a control module, a clock distribution module, an FPGA load module, and a power supply module. The input clock module is connected to the programmable clock chip and provides a local crystal oscillator clock or an external input clock to the programmable clock chip. The control module is connected to the programmable clock chip and outputs control signals to select the input clock type of the programmable clock chip. The programmable clock chip is connected to the clock distribution module and transmits the configured clock signal to the clock distribution module. The clock distribution module is connected to the FPGA load module and distributes the clock signal to each FPGA chip. The power supply module is connected to the input clock module, the programmable clock chip, the control module, the clock distribution module, and the FPGA load module to provide operating power.

[0026] The input clock module includes a local crystal oscillator output pin and an external clock input / output pin; the local crystal oscillator output pin is connected to the programmable clock chip and is used to transmit the local crystal oscillator clock; the external clock input / output pin is connected to the programmable clock chip and is used to transmit the external input clock.

[0027] The programmable clock chip includes XTAL_IN, EXT_CLK_IN, REF_SEL, SCLK, SDI, SDO, CSB, OUT0, and VDD. XTAL_IN is connected to the local crystal output pin of the input clock module; EXT_CLK_IN is connected to the external clock input / output pin of the input clock module; REF_SEL is connected to REF_SEL_OUT of the control module; SCLK is connected to SPI_SCLK of the control module; SDI is connected to SPI_MOSI of the control module; SDO is connected to SPI_MISO of the control module; CSB is connected to SPI_CS of the control module; OUT0 is connected to CLK_IN of the clock distribution module; and VDD is connected to 3.3V_OUT of the power supply module.

[0028] The control module includes REF_SEL_OUT, SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_CS, RED_LED, GREEN_LED, and VDD3.3. REF_SEL_OUT is connected to the REF_SEL pin of the programmable clock chip and is used to output high / low level signals to control the programmable clock chip to select the input clock type. SPI_SCLK is connected to the SCLK pin of the programmable clock chip and is used to transmit the SPI communication clock signal. SPI_MOSI is connected to the SDI pin of the programmable clock chip and is used to send configuration commands to the programmable clock chip. SPI_MISO is connected to the SDO pin of the programmable clock chip. Used to receive status data from the programmable clock chip; SPI_CS is connected to the CSB of the programmable clock chip and is used to control the start and stop of SPI communication; RED_LED is connected to the cathode of the external red indicator light through a current-limiting resistor, and the anode of the red indicator light is connected to the 3.3V_OUT of the power module, used to control the red indicator light to illuminate to indicate configuration failure; GREEN_LED is connected to the cathode of the external green indicator light through a current-limiting resistor, and the anode of the green indicator light is connected to the 3.3V_OUT of the power module, used to control the green indicator light to illuminate to indicate configuration success; VDD3.3 is connected to the 3.3V_OUT of the power module and is used to receive 3.3V operating power.

[0029] The clock distribution module includes CLK_IN, CLK_OUT1, CLK_OUT2, CLK_OUT3, CLK_OUT4, and VDD. CLK_IN is connected to OUT0 of the programmable clock chip and is used to receive the configured clock signal output by the programmable clock chip. CLK_OUT1 is connected to FPGA1_CLK of the FPGA load module. CLK_OUT2 is connected to FPGA2_CLK of the FPGA load module. CLK_OUT3 is connected to FPGA3_CLK of the FPGA load module. CLK_OUT4 is connected to FPGA4_CLK of the FPGA load module. CLK_OUT1 to CLK_OUT4 are used to distribute the clock signal to each FPGA chip. VDD is connected to 1.8V_OUT of the power supply module and is used to receive the 1.8V operating power supply.

[0030] The FPGA load module includes FPGA1_CLK, FPGA2_CLK, FPGA3_CLK, FPGA4_CLK, and VDD; FPGA1_CLK is connected to CLK_OUT1 of the clock distribution module; FPGA2_CLK is connected to CLK_OUT2 of the clock distribution module; FPGA3_CLK is connected to CLK_OUT3 of the clock distribution module; FPGA4_CLK is connected to CLK_OUT4 of the clock distribution module. The above FPGA1_CLK to FPGA4_CLK are used to receive the distributed clock signal; VDD is connected to 1.8V_OUT of the power supply module and is used to receive 1.8V operating power.

[0031] The power supply module includes 3.3V_OUT and 1.8V_OUT; 3.3V_OUT is connected to the power supply pin of the input clock module, the VDD of the programmable clock chip, and the VDD3.3 of the control module, respectively, to provide 3.3V operating power; 1.8V_OUT is connected to the VDD of the clock distribution module and the VDD of the FPGA load module, respectively, to provide 1.8V operating power.

[0032] Specific implementation process: The power supply module is started, providing 3.3V operating power to the input clock module, programmable clock chip, and control module via 3.3V_OUT, and 1.8V operating power to the clock distribution module and FPGA load module via 1.8V_OUT, ensuring all modules are power-on ready. The input clock module is in standby mode, providing the local crystal clock through its local crystal output pin and preparing to receive external input clocks through its external clock input / output pins. Both clock signals are connected to the corresponding pins of the programmable clock chip. After the control module starts, it outputs a high / low level signal to the REF_SEL pin of the programmable clock chip via REF_SEL_OUT to select the current clock type—a high level selects the external input clock, and a low level selects the local crystal clock. Subsequently, the control module communicates with the programmable clock chip via the SPI interface: SPI_SCLK provides the communication clock, SPI_MOSI sends specific configuration instructions to the SDI pin of the programmable clock chip, and the programmable clock chip feeds back configuration status data to the control module via the SDO pin and SPI_MISO; the SPI_CS pin controls the start and stop of SPI communication through high and low levels to ensure the accuracy of instruction transmission. After receiving the feedback data, if the control module determines that the configuration is successful, it controls the GREEN_LED pin to output a low level, illuminating the green indicator light; if the configuration fails, it controls the RED_LED pin to output a low level, illuminating the red indicator light, providing a clear feedback on the configuration result. After processing the clock signal according to the instructions of the control module, the programmable clock chip transmits the configured stable clock signal to the CLK_IN pin of the clock distribution module via the OUT0 pin. After receiving the clock signal, the clock distribution module performs synchronous processing through internal circuitry, and then transmits it to the FPGA1_CLK to FPGA4_CLK pins of the FPGA load module via the CLK_OUT1 to CLK_OUT4 pins respectively, realizing the synchronous distribution of the clock signal to multiple FPGA chips. Ultimately, each FPGA chip completes its own logic operations and data processing based on the received clock signal, and the entire circuit operates normally with the support of clock adaptive configuration and stable transmission.

[0033] In the embodiments disclosed in this utility model, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments disclosed in this utility model according to the specific circumstances.

[0034] This specific embodiment is merely an explanation of the present utility model and is not intended to limit the present utility model. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but as long as they are within the scope of the claims of the present utility model, they are protected by patent law.

Claims

1. A clock-adaptive flexible configuration circuit, characterized in that: It includes an input clock module, a programmable clock chip, a control module, a clock distribution module, an FPGA load module, and a power supply module; the input clock module is connected to the programmable clock chip and is used to provide the programmable clock chip with a local crystal oscillator clock or an external input clock; The control module is connected to the programmable clock chip and is used to output control signals to select the input clock type of the programmable clock chip. The programmable clock chip is connected to the clock distribution module and is used to transmit the configured clock signal to the clock distribution module. The clock distribution module is connected to the FPGA load module and is used to distribute the clock signal to each FPGA chip. The power supply module is connected to the input clock module, the programmable clock chip, the control module, the clock distribution module, and the FPGA load module respectively and is used to provide operating power.

2. The clock-adaptive flexible configuration circuit according to claim 1, characterized in that: The input clock module includes a local crystal oscillator output pin and an external clock input / output pin; the local crystal oscillator output pin is connected to a programmable clock chip for transmitting the local crystal oscillator clock; the external clock input / output pin is connected to a programmable clock chip for transmitting the external input clock.

3. The clock-adaptive flexible configuration circuit according to claim 2, characterized in that: The programmable clock chip includes XTAL_IN, EXT_CLK_IN, REF_SEL, SCLK, SDI, SDO, CSB, OUT0, and VDD; XTAL_IN is connected to the local crystal oscillator output pin of the input clock module; EXT_CLK_IN is connected to the external clock input / output pin of the input clock module; REF_SEL is connected to the control module; SCLK is connected to the control module; SDI is connected to the control module; SDO is connected to the control module; CSB is connected to the control module; OUT0 is connected to the clock distribution module; and VDD is connected to the power supply module.

4. The clock-adaptive flexible configuration circuit according to claim 3, characterized in that: The control module includes REF_SEL_OUT, SPI_SCLK, SPI_MOSI, SPI_MISO, SPI_CS, RED_LED, GREEN_LED, and VDD3.

3. REF_SEL_OUT is connected to the REF_SEL of the programmable clock chip and is used to output high and low level signals to control the programmable clock chip to select the input clock type. SPI_SCLK is connected to the SCLK of the programmable clock chip and is used to transmit the SPI communication clock signal. SPI_MOSI is connected to the SDI of the programmable clock chip and is used to send configuration commands to the programmable clock chip. SPI_MISO is connected to the SDO of the programmable clock chip. The SPI_CS pin is connected to the CSB pin of the programmable clock chip and is used to control the start and stop of SPI communication. The RED_LED pin is connected to the cathode of the external red indicator light through a current-limiting resistor, and the anode of the red indicator light is connected to the 3.3V_OUT pin of the power module, used to control the red indicator light to illuminate to indicate configuration failure. The GREEN_LED pin is connected to the cathode of the external green indicator light through a current-limiting resistor, and the anode of the green indicator light is connected to the 3.3V_OUT pin of the power module, used to control the green indicator light to illuminate to indicate configuration success. The VDD3.3 pin is connected to the 3.3V_OUT pin of the power module and is used to receive 3.3V operating power.

5. The clock-adaptive flexible configuration circuit according to claim 4, characterized in that: The clock distribution module includes CLK_IN, CLK_OUT1, CLK_OUT2, CLK_OUT3, CLK_OUT4, and VDD. CLK_IN is connected to OUT0 of the programmable clock chip and is used to receive the configured clock signal output by the programmable clock chip. CLK_OUT1 is connected to FPGA1_CLK of the FPGA load module. CLK_OUT2 is connected to FPGA2_CLK of the FPGA load module. CLK_OUT3 is connected to FPGA3_CLK of the FPGA load module. CLK_OUT4 is connected to FPGA4_CLK of the FPGA load module. CLK_OUT1 to CLK_OUT4 are used to distribute the clock signal to each FPGA chip. VDD is connected to 1.8V_OUT of the power supply module and is used to receive the 1.8V operating power supply.

6. The clock-adaptive flexible configuration circuit according to claim 5, characterized in that: The FPGA load module includes FPGA1_CLK, FPGA2_CLK, FPGA3_CLK, FPGA4_CLK, and VDD; FPGA1_CLK is connected to CLK_OUT1 of the clock distribution module; FPGA2_CLK is connected to CLK_OUT2 of the clock distribution module; FPGA3_CLK is connected to CLK_OUT3 of the clock distribution module; and FPGA4_CLK is connected to CLK_OUT4 of the clock distribution module. FPGA1_CLK to FPGA4_CLK are used to receive the allocated clock signal; VDD is connected to 1.8V_OUT of the power supply module and is used to receive 1.8V operating power.

7. A clock-adaptive flexible configuration circuit according to claim 6, characterized in that: The power supply module includes 3.3V_OUT and 1.8V_OUT; the 3.3V_OUT is connected to the power supply pin of the input clock module, the VDD of the programmable clock chip, and the VDD3.3 of the control module, respectively, to provide a 3.3V operating power supply; the 1.8V_OUT is connected to the VDD of the clock distribution module and the VDD of the FPGA load module, respectively, to provide a 1.8V operating power supply.

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