Reset circuit based on external watchdog and battery management system

Abstract

The disclosure provides a kind of reset circuit based on external watchdog and battery management system, the reset circuit based on external watchdog described includes microcontroller, external watchdog chip and current-limiting resistance.The power input end of external watchdog chip is connected to external power supply, signal monitoring end is connected with the periodic signal output end of microcontroller by current-limiting resistance, and the reset input end of microcontroller is connected with the reset signal output end of external watchdog chip.This circuit uses external independent external watchdog chip to monitor battery system, effectively isolates internal circuit interference, and improves system protection reliability.When battery system fails, such as microcontroller is in trouble or cannot normally execute task, external watchdog chip can quickly detect the absence of periodic signal, and triggers reset operation within preset timeout, timely interrupts fault state, to effectively protect the safety of battery system.

Description

Technical Field

[0001] This disclosure relates to the technical field of battery management systems, and in particular to a reset circuit and battery management system based on an external watchdog. Background Technology

[0002] With the widespread use of portable electronic devices, battery management systems (BMS) play a crucial role in ensuring the normal operation of devices and the safe use of batteries. BMS performs important functions such as battery status monitoring, charging management, discharging management, and system protection. Among these, system protection is of paramount importance, effectively preventing abnormal conditions such as overcharging, over-discharging, and overheating of the battery, thereby extending battery life and ensuring safe device use.

[0003] Traditional BMS system protection implementations typically employ an internal watchdog timer. This timer periodically resets the battery system to prevent system crashes caused by software faults. However, in practical applications, this type of internal watchdog timer often suffers from insufficient reliability. Because it resides within the system, it is susceptible to various internal interference factors, leading to false triggers or missed triggers. False triggers cause the system to reset unexpectedly during normal operation, impacting user experience; missed triggers prevent timely reset when a system fault occurs, leaving the system in a persistent abnormal state. Utility Model Content

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a reset circuit and battery management system based on an external watchdog timer to reduce internal interference and improve reliability through an external watchdog module.

[0005] The purpose of this disclosure is achieved through the following technical solution:

[0006] A reset circuit based on an external watchdog timer includes a microcontroller, an external watchdog chip, and a current-limiting resistor. The power input terminal of the external watchdog chip is connected to an external power supply terminal. The signal monitoring terminal of the external watchdog chip is connected to the periodic signal output terminal of the microcontroller through the current-limiting resistor. The reset input terminal of the microcontroller is connected to the reset signal output terminal of the external watchdog chip. The ground terminal of the external watchdog chip is grounded.

[0007] In one embodiment, the reset circuit based on the external watchdog further includes a voltage divider resistor, the first end of which is connected to an external power supply terminal, and the second end of which is connected to the power input terminal of the external watchdog chip.

[0008] In one embodiment, the reset circuit based on an external watchdog further includes a filter capacitor, the first end of which is connected to the second end of the voltage divider resistor, and the second end of the filter capacitor is grounded.

[0009] In one embodiment, the filter capacitor is an adjustable capacitor.

[0010] In one embodiment, the reset circuit based on an external watchdog further includes a timeout adjustment resistor, the first end of which is connected to the delay control terminal of the external watchdog chip, and the second end of which is connected to a ground terminal.

[0011] In one embodiment, the timeout adjustment resistor is an adjustable resistor.

[0012] In one embodiment, the reset circuit based on the external watchdog further includes a reset current-limiting resistor, the first end of which is connected to the reset input terminal of the microcontroller, and the second end of which is connected to the reset signal output terminal of the external watchdog chip.

[0013] In one embodiment, the external watchdog chip is model SGM821.

[0014] In one embodiment, the microcontroller is model LPC5506JHI48.

[0015] This application also provides a battery management system, including the reset circuit based on an external watchdog as described in any embodiment.

[0016] Compared with the prior art, this disclosure has at least the following advantages:

[0017] The aforementioned external watchdog-based reset circuit effectively isolates potential interference from internal circuits by employing an independent external watchdog chip to monitor the battery system. It is also unaffected by the complex internal environment of the microcontroller, thus improving the reliability of system protection. When a battery system malfunctions, such as when the microcontroller fails or cannot perform its tasks, the external watchdog chip can quickly detect the absence of a periodic signal and trigger a reset operation within a preset timeout period. This helps to promptly interrupt the fault state and effectively protect the battery system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this disclosure and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a circuit diagram of a reset circuit based on an external watchdog, according to one embodiment. Detailed Implementation

[0020] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure.

[0021] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0023] To better understand the technical solutions and beneficial effects of this disclosure, the following detailed description is provided in conjunction with specific embodiments:

[0024] like Figure 1As shown, a reset circuit 10 based on an external watchdog in one embodiment of this disclosure includes a microcontroller U2, an external watchdog chip UM1, and a current-limiting resistor RM3. The power input terminal VDD of the external watchdog chip UM1 is used to connect to an external power supply terminal. The signal monitoring terminal M_RSTDONE of the external watchdog chip UM1 is connected to the periodic signal output terminal DONE of the microcontroller U2 through the current-limiting resistor RM3. The reset input terminal MCU_RST of the microcontroller U2 is connected to the reset signal output terminal RSTn of the external watchdog chip UM1. The ground terminal GND of the external watchdog chip UM1 is grounded.

[0025] In this embodiment, when the battery system is in normal operation, to ensure that the system does not crash due to software failure, the microcontroller U2 periodically outputs a level signal from its periodic signal output terminal DONE. This level signal is transmitted to the signal monitoring terminal M_RSTDONE of the external watchdog chip UM1 after passing through the current-limiting resistor RM3. The current-limiting resistor RM3 plays a crucial role in limiting the current during this process. It effectively prevents excessive current from the signal output from the microcontroller U2, thereby avoiding excessive current surges to the signal monitoring terminal of the external watchdog chip UM1 and protecting the external watchdog chip UM1 from damage.

[0026] Specifically, when the signal monitoring terminal M_RSTDONE of the external watchdog chip UM1 receives a level signal from the microcontroller U2, the timer inside the external watchdog chip UM1 will be reset and restart the timing. If the microcontroller U2 can continuously send level signals according to the normal cycle, the timer of the external watchdog chip UM1 will not time out, and the reset signal output terminal RSTn will not output a low level signal. Therefore, the reset input terminal MCU_RST of the microcontroller U2 will not receive a reset signal, and the battery system can continue to operate stably. Each functional module works normally according to the predetermined program, realizing effective monitoring of battery status, charging and discharging management, and other operations.

[0027] Furthermore, when the battery system malfunctions, the microcontroller U2 cannot execute tasks according to the normal program flow, or it may enter a fault state, preventing it from sending a level signal from the periodic signal output terminal DONE to the external watchdog chip UM1 according to the preset cycle. In this case, the timer inside the external watchdog chip UM1 will continue counting. Since there is no level signal to reset the timer, when the count reaches the preset timeout period, the reset signal output terminal RSTn of the external watchdog chip UM1 will output a low-level signal. This low-level signal is transmitted to the reset input terminal MCU_RST of the microcontroller U2. When the reset input terminal MCU_RST of the microcontroller U2 receives the low-level signal, it triggers a reset operation, causing the microcontroller U2 to reinitialize and return to its initial state. This may clear the fault state and allow the normal program execution to resume, thereby preventing abnormal situations such as battery overcharging, over-discharging, and overheating caused by the fault.

[0028] The aforementioned external watchdog-based reset circuit 10 effectively isolates potential interference from internal circuits by employing an independent external watchdog chip UM1 to monitor the battery system. It is also unaffected by the complex internal environment of the microcontroller, thus improving the reliability of system protection. When a battery system malfunctions, such as when the microcontroller U2 fails or cannot perform its tasks, the external watchdog chip UM1 can quickly detect the absence of periodic signals and trigger a reset operation within a preset timeout period. This helps to promptly interrupt the fault state and effectively protect the safety of the battery system.

[0029] In another embodiment, the microcontroller U2 is a battery management chip, i.e., a BMS chip.

[0030] like Figure 1 As shown, in one embodiment, the reset circuit 10 based on the external watchdog also includes a voltage divider resistor RM1. The first end of the voltage divider resistor RM1 is connected to the external power supply terminal, and the second end of the voltage divider resistor RM1 is connected to the power input terminal VDD of the external watchdog chip UM1. In this embodiment, the voltage divider resistor RM1 serves as a voltage regulator. In practical applications, the voltage provided by the external power supply terminal may not fully meet the operating voltage requirements of the external watchdog chip UM1. By introducing the voltage divider resistor RM1, the voltage provided by the external power supply terminal can be divided, ensuring that the power input terminal VDD of the external watchdog chip UM1 receives a suitable voltage value. This allows the external watchdog chip UM1 to operate in a stable voltage environment, avoiding performance instability or damage caused by excessively high or low voltage.

[0031] like Figure 1As shown, in one embodiment, the reset circuit 10 based on the external watchdog also includes a filter capacitor CM1. The first terminal of the filter capacitor CM1 is connected to the second terminal of the voltage divider resistor RM1, and the second terminal of the filter capacitor CM1 is grounded. In this embodiment, the filter capacitor CM1 has a significant filtering effect. In a battery system, the external power supply terminal is often affected by various electromagnetic interferences, noise, and power fluctuations. The filter capacitor CM1 can absorb and buffer these high-frequency noises and transient interferences, converting them into a small amount of heat dissipation. This makes the voltage received by the power input terminal VDD of the external watchdog chip UM1 more stable, ensuring that the external watchdog chip UM1 can work in a stable power environment, avoiding malfunctions or performance degradation caused by power noise, and improving the reliability and stability of the entire reset circuit. Secondly, structurally, the introduction of the filter capacitor CM1 enhances the circuit's anti-interference capability. Together with the voltage divider resistor RM1, it forms a simple RC filter circuit, which performs preliminary preprocessing of the power signal. This effectively reduces the interference received by other components in the subsequent circuit, improving the anti-interference performance of the entire circuit system.

[0032] like Figure 1 As shown, in one embodiment, the filter capacitor CM1 is an adjustable capacitor. In this embodiment, the environment in which the battery system operates is complex and variable, and the intensity and frequency of electromagnetic interference, noise, and power fluctuations experienced by the external power supply are not constant. For example, when the battery system is in a strong electromagnetic interference environment, such as near a large motor or high-frequency transmitting equipment, a large amount of high-frequency noise and transient interference will be mixed into the power signal. By increasing the capacitance value of the adjustable filter capacitor CM1, its absorption and buffering ability against high-frequency noise and transient interference can be enhanced. A larger capacitance value means that the filter capacitor CM1 can store more charge, thereby more effectively converting the interference signal into a small amount of heat dissipation when facing high-intensity interference. This makes the voltage received by the power input terminal VDD of the external watchdog chip UM1 more stable, ensuring that the external watchdog chip UM1 can still work in a stable power environment under strong interference conditions, avoiding malfunctions or performance degradation caused by power noise, and greatly improving the reliability and stability of the reset circuit in complex electromagnetic environments.

[0033] like Figure 1As shown, in one embodiment, the reset circuit 10 based on the external watchdog also includes a timeout adjustment resistor RM2. The first end of the timeout adjustment resistor RM2 is connected to the delay control terminal DELAY of the external watchdog chip UM1, and the second end of the timeout adjustment resistor RM2 is connected to ground. In this embodiment, the timeout adjustment resistor RM2, connected to the delay control terminal DELAY of the external watchdog chip UM1, forms a resistor divider network. This network can affect the charging or discharging rate of the internal timer of the external watchdog chip UM1, thereby adjusting the timeout time of the timer. By changing the resistance value of the timeout adjustment resistor RM2, the timeout threshold of the external watchdog chip UM1 can be precisely adjusted, so that the reset operation can be triggered at an appropriate time when a battery system failure occurs. In practical applications, the resistance value of the timeout adjustment resistor RM2 needs to be determined according to the specific characteristics and operating requirements of the battery system. For example, in scenarios requiring rapid fault response, a smaller resistance value can be selected to shorten the timeout time, ensuring that the external watchdog chip UM1 can quickly detect the abnormality of the microcontroller U2 and trigger the reset operation. In scenarios where system stability is critical and a certain fault tolerance time is acceptable, a larger resistance value can be selected to extend the timeout period and avoid accidental reset operations caused by brief signal fluctuations or transient interference.

[0034] like Figure 1 As shown, in one embodiment, the timeout adjustment resistor RM2 is an adjustable resistor. In this embodiment, the timeout adjustment resistor RM2 allows the user to dynamically adjust the timeout period of the external watchdog chip UM1 according to the actual operating conditions and needs of the battery system. When the battery system faces different workloads, environmental conditions, or fault modes, the reset triggering timing of the external watchdog chip UM1 can be precisely controlled by adjusting the resistance value of the timeout adjustment resistor RM2. Specifically, when the battery system is operating under high load or complex electromagnetic environment, the timeout period can be shortened by reducing the resistance value of the timeout adjustment resistor RM2 to ensure that the system can respond quickly and recover stability; while when the system is under low load or stable operation, the resistance value of the timeout adjustment resistor RM2 can be increased to extend the timeout period to reduce unnecessary reset operations.

[0035] like Figure 1As shown, in one embodiment, the reset circuit 10 based on the external watchdog also includes a reset current-limiting resistor RM4. The first terminal of the reset current-limiting resistor RM4 is connected to the reset input terminal MCU_RST of the microcontroller U2, and the second terminal of the reset current-limiting resistor RM4 is connected to the reset signal output terminal RSTn of the external watchdog chip UM1. In this embodiment, when the external watchdog chip UM1 triggers a reset operation, the reset signal output terminal RSTn outputs a low-level signal. Due to the possible presence of parasitic capacitance, inductance, and other components in the circuit, as well as sudden changes in power supply voltage, this low-level signal may be accompanied by a transient large current. The reset current-limiting resistor RM4 can effectively limit the amplitude of this transient large current, preventing it from exceeding the maximum current that the reset input terminal MCU_RST of the microcontroller U2 can withstand, thereby avoiding damage to the MCU_RST pin due to overcurrent.

[0036] like Figure 1 As shown, in one embodiment, the external watchdog chip is model SGM821. In this embodiment, SGM821 features ultra-low power consumption. In a battery management system, power consumption is a critical indicator; excessive power consumption accelerates battery depletion and shortens battery life. SGM821's ultra-low power design minimizes battery drain while continuously monitoring the battery system's operating status. Even when the battery system is in operation for extended periods, SGM821's power consumption will not significantly impact battery performance, thus ensuring longer and more stable battery system operation. Furthermore, SGM821 possesses a precise timer function. During normal battery system operation, microcontroller U2 periodically outputs a level signal to reset SGM821's timer. Because the timer is accurate, as long as microcontroller U2 continuously sends level signals according to the normal cycle, SGM821 can accurately determine the system status without misjudgment. When the battery system malfunctions and the microcontroller U2 fails to send a level signal from the DONE output terminal according to the preset cycle, the SGM821's timer can accurately time out to the preset timeout period and trigger a reset operation in a timely manner. This precise timing function ensures that the reset operation is executed at the appropriate time under various operating conditions, preventing premature resets from affecting the normal operation of the system and delayed resets from exacerbating the fault, thus effectively improving the reliability and stability of the battery system.

[0037] like Figure 1As shown, in one embodiment, the microcontroller is an LPC5506JHI48. In this embodiment, the LPC5506JHI48 is a high-performance microcontroller with powerful computing capabilities and fast data processing speed. In the external watchdog-based reset circuit, it can more efficiently output a level signal from the DONE output terminal according to a preset period. Compared to ordinary microcontrollers, the LPC5506JHI48 can more precisely control the time interval of the signal output, ensuring that the timer inside the external watchdog chip UM1 can be accurately reset, avoiding misjudgments. On the other hand, the LPC5506JHI48 has rich peripheral interfaces, integrating various communication interfaces (such as I2C, SPI, UART, etc.), enabling the microcontroller to easily interact and communicate with other modules in the battery system. The rich peripheral interfaces provide convenient conditions for the functional expansion and integration of the battery system, allowing the system to be flexibly configured and upgraded according to different application requirements, enhancing the system's adaptability and versatility.

[0038] This application also provides a battery management system, including a reset circuit 10 based on an external watchdog timer according to any embodiment. In this embodiment, when the battery system is in normal operation, to ensure that the system does not crash due to software failure, the microcontroller U2 periodically outputs a level signal from its periodic signal output terminal DONE. This level signal is transmitted to the signal monitoring terminal M_RSTDONE of the external watchdog chip UM1 after passing through the current-limiting resistor RM3. The current-limiting resistor RM3 plays a crucial current-limiting role in this process, effectively preventing excessive signal current from the microcontroller U2, thereby avoiding excessive current surge to the signal monitoring terminal of the external watchdog chip UM1 and protecting the external watchdog chip UM1 from damage. Specifically, when the signal monitoring terminal M_RSTDONE of the external watchdog chip UM1 receives the level signal from the microcontroller U2, the timer inside the external watchdog chip UM1 is reset and restarts counting. If microcontroller U2 continuously sends level signals according to the normal cycle, the timer of the external watchdog chip UM1 will not time out, and the reset signal output terminal RSTn will not output a low-level signal. Therefore, the reset input terminal MCU_RST of microcontroller U2 will not receive a reset signal, and the battery system can operate continuously and stably. Each functional module works normally according to the predetermined program, realizing effective monitoring of battery status, charging and discharging management, and other operations. Furthermore, when the battery system malfunctions, microcontroller U2 cannot execute tasks according to the normal program flow, or it enters a fault state, causing it to be unable to send level signals from the periodic signal output terminal DONE to the external watchdog chip UM1 according to the preset cycle. At this time, the timer inside the external watchdog chip UM1 will continue counting. Since there is no level signal to reset the timer, when the count reaches the preset timeout period, the reset signal output terminal RSTn of the external watchdog chip UM1 will output a low-level signal. This low-level signal is transmitted to the reset input terminal MCU_RST of microcontroller U2. When the reset input terminal MCU_RST of microcontroller U2 receives a low-level signal, it will trigger a reset operation, causing microcontroller U2 to be reinitialized and restored to its initial state. This may clear the fault state and allow the program to resume normal execution, thereby preventing abnormal situations such as battery overcharging, over-discharging, and overheating caused by the fault.

[0039] Compared with the prior art, this disclosure has at least the following advantages:

[0040] The aforementioned external watchdog-based reset circuit 10 effectively isolates potential interference from internal circuits by employing an independent external watchdog chip UM1 to monitor the battery system. It is also unaffected by the complex internal environment of the microcontroller, thus improving the reliability of system protection. When a battery system malfunctions, such as when the microcontroller U2 fails or cannot perform its tasks, the external watchdog chip UM1 can quickly detect the absence of periodic signals and trigger a reset operation within a preset timeout period. This helps to promptly interrupt the fault state and effectively protect the safety of the battery system.

[0041] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A reset circuit based on an external watchdog timer, characterized in that, The device includes a microcontroller, an external watchdog chip, and a current-limiting resistor. The power input terminal of the external watchdog chip is used to connect to an external power supply terminal. The signal monitoring terminal of the external watchdog chip is connected to the periodic signal output terminal of the microcontroller through the current-limiting resistor. The reset input terminal of the microcontroller is connected to the reset signal output terminal of the external watchdog chip. The ground terminal of the external watchdog chip is grounded. The reset circuit based on the external watchdog also includes a voltage divider resistor, a filter capacitor, and a timeout adjustment resistor. The first end of the voltage divider resistor is connected to the external power supply terminal, and the second end of the voltage divider resistor is connected to the power input terminal of the external watchdog chip. The first terminal of the filter capacitor is connected to the second terminal of the voltage divider resistor, and the second terminal of the filter capacitor is grounded; the filter capacitor is an adjustable capacitor. The first end of the timeout adjustment resistor is connected to the delay control terminal of the external watchdog chip, and the second end of the timeout adjustment resistor is connected to the ground terminal; the timeout adjustment resistor is an adjustable resistor.

2. The reset circuit based on an external watchdog timer according to claim 1, characterized in that, The reset circuit based on the external watchdog also includes a reset current-limiting resistor. The first end of the reset current-limiting resistor is connected to the reset input terminal of the microcontroller, and the second end of the reset current-limiting resistor is connected to the reset signal output terminal of the external watchdog chip.

3. The reset circuit based on an external watchdog timer according to claim 1, characterized in that, The external watchdog chip is model SGM821.

4. The reset circuit based on an external watchdog timer according to claim 1, characterized in that, The microcontroller is model LPC5506JHI48.

5. A battery management system, characterized in that, Includes the reset circuit based on an external watchdog as described in any one of claims 1 to 4.

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