Graphics processing module and computer device

Abstract

The application relates to a graphics processing module and a computer device. The graphics processing module comprises a central processor, a chipset connected to the central processor, a first graphics processor integrated in the chipset, a graphics card connector connected to the central processor, a separate graphics card comprising a second graphics processor arranged on the graphics card connector, and a signal output circuit connected to the chipset and the graphics card connector, the signal output circuit comprising a first display signal output path and a second display signal output path. The first display signal output path outputs a first display signal, and the second display signal output path outputs a second display signal. The first display signal is output by the first graphics processor, and the second display signal is output by the second graphics processor. In the technical scheme, the graphics processing module can output display signals through different graphics processors, thereby meeting different requirements and effectively improving the applicability of the graphics processing module.

Description

Technical Field

[0001] This application relates to the field of computer hardware technology, and in particular to a graphics processing module and a computer device. Background Technology

[0002] With the development of technology, computer equipment has become an increasingly indispensable electronic product. The graphics processing module (GPU), as a crucial hardware component of computer equipment, generates display signals, enabling the computer to output these signals to a connected monitor to display images or videos to the user. Typically, a GPU is based on a central processing unit (CPU) and is paired with a graphics processing unit (GPU) depending on the application requirements.

[0003] In existing technical solutions, the architecture of the graphics processing module is selected according to the preset application scenario: one architecture is to use a low-power GPU integrated in the chipset, which is suitable for computing tasks with low graphics processing performance requirements; the other architecture is to use a separate high-performance GPU, which is suitable for complex graphics processing scenarios.

[0004] However, both of the aforementioned architectural solutions can only meet relatively singular needs. A graphics processing module designed for low power consumption cannot meet sudden high-performance graphics processing demands, while a graphics processing module designed for high performance will cause unnecessary energy consumption when performing low-load tasks. It is evident that existing graphics processing modules are difficult to apply to scenarios with diverse needs, exhibiting poor applicability. Utility Model Content

[0005] Therefore, it is necessary to provide a graphics processing module and computer device that can be applied to various application scenarios, so as to solve the technical problem of poor applicability of existing graphics processing modules.

[0006] A graphics processing module, comprising:

[0007] CPU;

[0008] A chipset assembly connected to the central processing unit, wherein a first graphics processor is integrated in the chipset assembly;

[0009] A graphics card connector is connected to the central processing unit, and the graphics card connector is equipped with a discrete graphics card including a second graphics processor;

[0010] A signal output circuit is connected to the chipset and the graphics card connector. The signal output circuit includes a first display signal output path and a second display signal output path. The first display signal output path outputs a first display signal, and the second display signal output path outputs a second display signal. The first display signal is a display signal output by the first graphics processor, and the second display signal is a display signal output by the second graphics processor.

[0011] In one embodiment, the signal output circuit includes at least one high-speed switch and at least one graphics signal converter. The first end of the graphics signal converter is connected to the graphics signal interface of the chipset, the second end of the graphics signal converter is connected to the first switching terminal of the high-speed switch, the second switching terminal of the high-speed switch is connected to the graphics card connector, and the common terminal of the high-speed switch outputs the first display signal or the second display signal.

[0012] In one embodiment, the graphics processing module further includes:

[0013] The first firmware transmission circuit is connected to the central processing unit;

[0014] The second firmware transmission circuit is connected to the chipset;

[0015] The first firmware storage unit is connected to the first firmware transmission circuit and stores a first boot firmware for the first graphics processor and a second boot firmware for the second graphics processor.

[0016] The second firmware storage unit is connected to the second firmware transmission circuit and stores a first initialization firmware for the first graphics processor and a second initialization firmware for the second graphics processor.

[0017] In one embodiment, the graphics processing module further includes:

[0018] The baseboard management controller is connected to the central processing unit, the signal output circuit, the first firmware transmission circuit, and the second firmware transmission circuit, respectively.

[0019] In one embodiment, the graphics processing module further includes:

[0020] Complex programmable logic devices are connected to the central processing unit and the baseboard management controller, respectively.

[0021] In one embodiment, the graphics processing module further includes:

[0022] Multiple memory controllers are connected to the central processing unit; wherein, the memory controllers are used to connect to a first dynamic random access memory, which serves as the system memory of the graphics processing module.

[0023] In one embodiment, the graphics processing module further includes:

[0024] A video memory controller is connected to the chipset; wherein the video memory controller is used to connect to a second dynamic random access memory, the second dynamic random access memory serving as the system video memory of the graphics processing module.

[0025] In one embodiment, the graphics processing module further includes:

[0026] Ethernet controller, connected to the central processing unit;

[0027] Multiple Ethernet port chips are connected to the Ethernet controller.

[0028] In one embodiment, the graphics processing module further includes:

[0029] A clock chip is connected to the central processing unit.

[0030] In one embodiment, a computer device is provided, including the graphics processing module described in any of the preceding claims.

[0031] The aforementioned graphics processing module includes a chipset connected to the central processing unit (CPU) and a graphics card connector. It also includes a signal output circuit. The chipset integrates a first graphics processor, and the graphics card connector can connect to a standalone graphics card including a second graphics processor. The signal output circuit is connected to the chipset and the graphics card connector. The signal output circuit includes a first display signal output path and a second display signal output path. The first display signal output path transmits a first display signal output by the first graphics processor, and the second display signal output path transmits a second display signal output by the second graphics processor. Through the technical solution provided in this application, the graphics processing module can output display signals through both the integrated first graphics processor and the standalone second graphics processor during operation. This allows the graphics processing module to meet diverse needs and effectively improves its applicability. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the graphics processing module.

[0034] Figure 2 This is a schematic diagram showing the connections of the internal components of the graphics processing module.

[0035] Figure 3 This is a schematic diagram of the external interface of the graphics processing module;

[0036] Figure 4 This is a schematic diagram of a computer device.

[0037] Explanation of reference numerals in the attached figures:

[0038] 010 Central Processing Unit (CPU); 020 Chipset; 021 First Graphics Processor; 030 Graphics Card Connector; 040 Dedicated Graphics Card; 041 Second Graphics Processor; 050 Signal Output Circuit; 051 Graphics Signal Converter; 052 High-Speed ​​Switch; 060 First Firmware Storage Unit; 070 First Firmware Transmission Circuit; 080 Second Firmware Storage Unit; 090 Second Firmware Transmission Circuit; 100 Backplane Management Controller; 110 Complex Programmable Logic Device (Programmable Logic Device); 120 Memory Controller; 130 Video Memory Controller; 140 Ethernet Controller; 150 Ethernet Port Chip; 160 Clock Chip. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0042] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0043] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0045] This application aims to address the technical problem that existing graphics processing module architectures are relatively fixed, making it difficult to simultaneously meet the requirements of low power consumption and high performance, resulting in poor applicability. To this end, this application provides a graphics processing module and computer device that achieves flexible adaptation to different application scenarios through a dual graphics processor architecture, significantly improving the applicability of the graphics processing module.

[0046] Reference Figure 1 In one embodiment, the graphics processing module includes:

[0047] Central Processing Unit 010;

[0048] Chipset 020 is connected to central processing unit 010, and first graphics processor 021 is integrated in chipset 020;

[0049] Graphics card connector 030 connects to central processing unit 010, and a discrete graphics card 040 including a second graphics processor 041 is provided on graphics card connector 030;

[0050] The signal output circuit 050 connects the chipset 020 and the graphics card connector 030. The signal output circuit 050 includes a first display signal output path and a second display signal output path. The first display signal output path outputs a first display signal, and the second display signal output path outputs a second display signal. The first display signal is a display signal output by the first graphics processor 021, and the second display signal is a display signal output by the second graphics processor 041.

[0051] Specifically, the CPU 010 serves as the computing core of the entire graphics processing module, responsible for running the operating system, applications, and coordinating the work of other components within the graphics processing module. The selection of the CPU 010 is not unique; as an example, the CPU 010 can be a Tengrui D2000 processor.

[0052] The chipset 020 connects to the central processing unit 010, serving as a bridge and expanding the input / output interfaces. The chipset 020 integrates a first graphics processor 021. As a graphics processor integrated within the chipset 020, the first graphics processor 021 is suitable for general display, office applications, or low-load computing tasks with low graphics performance requirements. Its power consumption is typically around 15W, significantly lower than the graphics processor located in the discrete graphics card 040. The selection of the chipset 020 is not unique; as an example, the Phytium X100 chipset can be used for the chipset 020.

[0053] In one embodiment, the chipset 020 is connected to the central processing unit 010 via a PCIe 3.0 x 16 (peripheral component interconnect express, high-speed serial computer expansion bus) interface.

[0054] The graphics card connector 030 also connects to the central processing unit 010. A dedicated graphics card 040 is mounted on the graphics card connector 030, which includes a second graphics processor 041. The second graphics processor 041 operates based on the dedicated graphics card 040. Compared to the first graphics processor 021, the second graphics processor 041 has relatively higher computing power and is suitable for graphics rendering, video encoding / decoding, or high-load computing tasks with high graphics performance requirements. The dedicated graphics card 040 can be fixedly mounted on the graphics card connector 030, meaning the graphics processing module comes pre-installed with a fixed model of dedicated graphics card 040. Alternatively, the dedicated graphics card 040 can be detachable from the graphics card connector 030, allowing users to replace it at any time to meet different needs. The choice of graphics card connector 030 is not unique; for example, it can be an MXM connector or a standard PCIe slot. Similarly, the choice of dedicated graphics card 040 is not unique; as an example, the dedicated graphics card 040 can be a Jingjia Micro JH930.

[0055] In one embodiment, the graphics card connector 030 is connected to the central processing unit 010 via a PCIe 3.0 x8 interface.

[0056] The signal output circuit 050 is connected to the chipset 020 and the graphics card connector 030, respectively, and is responsible for outputting the display signal generated by the selected graphics processor to the external display interface of the graphics processing module. The signal output circuit 050 internally includes a first display signal output path and a second display signal output path. The first display signal output path is used to transmit the first display signal generated by the first graphics processor 021, and the second display signal output path is used to transmit the second display signal generated by the second graphics processor 041. By controlling the signal output circuit 050 to select one of the first or second display signal output paths to be active, it can be determined whether the entire graphics processing module operates in low-power integrated graphics mode or high-performance discrete graphics mode.

[0057] The technical solution provided in this application allows the graphics processing module to freely switch target graphics processors during operation. It can output display signals through the integrated, low-power first graphics processor 021 or through the independent, high-performance second graphics processor 041. This enables the graphics processing module to meet diverse needs and effectively improves its applicability.

[0058] Reference Figure 2In one embodiment, the signal output circuit 050 includes at least one high-speed switching device 052 and at least one graphics signal converter 051. The first end of the graphics signal converter 051 is connected to the graphics signal interface of the chipset 020, the second end of the graphics signal converter 051 is connected to the first switching end of the high-speed switching device 052, the second switching end of the high-speed switching device 052 is connected to the graphics card connector 030, and the common end of the high-speed switching device 052 outputs a first display signal or a second display signal.

[0059] Specifically, the signal output circuit 050 selects the output path of the display signal. In this embodiment, in order to achieve reliable switching between the first display signal and the second display signal and improve signal quality, the signal output circuit 050 includes at least one graphic signal converter 051 and at least one high-speed switching switch 052.

[0060] In this embodiment, the native graphics signal interface of the first graphics processor 021 is a DP (DisplayPort) signal, while the interface ultimately provided by the graphics processing module is the more universal HDMI 2.0 (High Definition Multimedia Interface) interface. Therefore, a graphics signal converter 051 is required. The first end of the graphics signal converter 051 is connected to the graphics signal interface of the chipset 020, converting the multiple DP signals output by the chipset 020 into HDMI signals in real time, and then outputting the HDMI signals to the high-speed switch 052.

[0061] The converted first display signal needs to be selected between the first display signal and the second display signal output by the second graphics processor 041. This selection function is implemented by the high-speed switch 052. The first switching terminal of the high-speed switch 052 is connected to the second terminal of the graphics signal converter 051, specifically to the HDMI signal pin on the graphics signal converter 051. This path carries the first display signal from the first graphics processor 021. The second switching terminal of the high-speed switch 052 is connected to the graphics card connector 030, specifically to the HDMI signal pin directly output by the second graphics processor 041 on the graphics card connector 030. This path carries the second display signal from the second graphics processor 041. The output terminal of the common terminal signal output circuit 050 of the high-speed switch 052 is connected to the HDMI output pin of the external interface of the graphics processing module, for ultimately outputting either the first or second display signal.

[0062] The high-speed switching switch 052 can selectively connect the first switching terminal and the common terminal, or selectively connect the second switching terminal and the common terminal. When the graphics processing module uses the first graphics processor 021 as the target graphics processor, the high-speed switching switch 052 can be configured to connect the first switching terminal and the common terminal through an external control signal. When the graphics processing module uses the second graphics processor 041 as the target graphics processor, the high-speed switching switch 052 can be configured to connect the second switching terminal and the common terminal through another external control signal.

[0063] The selection of graphic signal converter 051 and high-speed switching switch 052 is not unique. As an example, graphic signal converter 051 can be equipped with GSV6201 chip, and high-speed switching switch 052 can be equipped with ASW3642 chip.

[0064] In the technical solution provided in this embodiment, the signal formats of the first display signal and the second display signal are unified based on the graphics signal converter 051, and a hardware switching scheme based on the high-speed switch 052 is used to achieve a two-way output of the first display signal and the second display signal. This embodiment can solve the technical problem of inconsistent native output signal formats of different graphics processors, and can achieve a two-way output of the first display signal and the second display signal with simple control logic.

[0065] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0066] The first firmware transmission circuit 070 is connected to the central processing unit 010;

[0067] The second firmware transmission circuit 090 is connected to the chip set 020;

[0068] The first firmware storage unit 060 is connected to the first firmware transmission circuit 070 and stores a first boot firmware for the first graphics processor 021 and a second boot firmware for the second graphics processor 041.

[0069] The second firmware storage unit 080 is connected to the second firmware transmission circuit 090 and stores a first initialization firmware for the first graphics processor 021 and a second initialization firmware for the second graphics processor 041.

[0070] Specifically, the graphics processing module is configured to call and adapt to different graphics processors by loading different boot firmware and initialization firmware.

[0071] The first firmware storage unit 060 stores a first boot firmware for the first graphics processor 021 and a second boot firmware for the second graphics processor 041. The first firmware storage unit 060 is connected to the central processing unit 010 via a first firmware transmission circuit 070. Both the first and second boot firmware are used to initialize the entire graphics processing module. When the graphics processing module is initialized using the first boot firmware, it is configured to load the first graphics processor 021; when it is initialized using the second boot firmware, it is configured to load the second graphics processor 041. In this embodiment, both the first and second boot firmware are UEFI (Unified Extensible Firmware Interface) files and are both loaded and executed by the central processing unit 010.

[0072] Continue to refer to Figure 2 In one embodiment, the first firmware storage unit 060 includes a first firmware memory and a second firmware memory. The first firmware memory stores a first boot firmware, and the second firmware memory stores a second boot firmware. As an example, both the first firmware memory and the second firmware memory are SPI FLASH (a non-volatile memory based on the Serial Peripheral Interface protocol) chips, specifically the GD25LQ128 chip. The first firmware transmission circuit 070 includes a high-speed switching switch 052. The first switching terminal of the high-speed switching switch 052 is connected to the first firmware memory, the second switching terminal of the high-speed switching switch 052 is connected to the second firmware memory, and the common terminal of the high-speed switching switch 052 is connected to the central processing unit 010. By controlling the high-speed switching switch 052, the first boot firmware can be selected to be transmitted to the central processing unit 010, or the second boot firmware can be selected to be transmitted to the central processing unit 010.

[0073] The second firmware storage unit 080 stores a first initialization firmware for the first graphics processor 021 and a second initialization firmware for the second graphics processor 041. The second firmware storage unit 080 is connected to the chipset 020 via a second firmware transmission circuit 090. Both the first and second initialization firmware are used to initialize the two graphics processing modules respectively. When the chipset 020 loads the first initialization firmware, the first graphics processor 021 is initialized; when the chipset 020 loads the second initialization firmware, the second graphics processor 041 is initialized. In this embodiment, both the first and second initialization firmware are VBIOS (Video BIOS, graphics card BIOS) files, and both are loaded and executed by the chipset 020.

[0074] Continue to refer to Figure 2In one embodiment, the second firmware storage unit 080 includes a third firmware memory and a fourth firmware memory. The third firmware memory stores the first initialization firmware, and the fourth firmware memory stores the second initialization firmware. As an example, both the third and fourth firmware memories are SPI FLASH chips, specifically the GD25LQ128 chip. The second firmware transmission circuit 090 includes a high-speed switching switch 052. The first switching terminal of the high-speed switching switch 052 is connected to the third firmware memory, and the second switching terminal of the high-speed switching switch 052 is connected to the fourth firmware memory. The common connection of the high-speed switching switch 052 is to the chipset 020. By controlling the high-speed switching switch 052, the first initialization firmware can be selected to be transmitted to the central processing unit 010, or the second initialization firmware can be selected to be transmitted to the central processing unit 010.

[0075] Based on the above embodiments, regardless of the target graphics processor currently selected, the graphics processing module can obtain the correct configuration from the lowest boot stage, thereby improving the stability and reliability of the switching.

[0076] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0077] The baseboard management controller 100 is connected to the central processing unit 010, the signal output circuit 050, the first firmware transmission circuit 070, and the second firmware transmission circuit 090, respectively.

[0078] Specifically, the Baseboard Management Controller (BMC) 100 controls the various components in the graphics processing module. The BMC 100 is connected to the central processing unit 010, the signal output circuit 050, the first firmware transmission circuit 070, and the second firmware transmission circuit 090, respectively. It controls the signal output circuit 050, the first firmware transmission circuit 070, and the second firmware transmission circuit 090 based on received graphics processor switching commands. As an example, the BMC 100 can be a CL32F407VGT6 microcontroller.

[0079] In one embodiment, the backplane management controller 100 communicates with the central processing unit 010 through interfaces such as I2C (Inter-Integrated Circuit) or UART (Universal Asynchronous Receiver / Transmitter) to report status information or receive control commands from the operating system.

[0080] When the target graphics processor of the graphics processing module is the first graphics processor 021, the baseboard management controller 100 sends a first control command to the signal output circuit 050, the first firmware transmission circuit 070, and the second firmware transmission circuit 090, causing the signal output circuit 050 to conduct the first display signal output path, the first firmware transmission circuit 070 to transmit the first boot firmware in the first firmware storage unit 060, and the second firmware transmission circuit 090 to transmit the first initialization firmware in the second firmware storage unit 080. When the target graphics processor of the graphics processing module is the second graphics processor 041, the baseboard management controller 100 sends a second control command to the signal output circuit 050, the first firmware transmission circuit 070, and the second firmware transmission circuit 090, causing the signal output circuit 050 to conduct the second display signal output path, the first firmware transmission circuit 070 to transmit the second boot firmware in the first firmware storage unit 060, and the second firmware transmission circuit 090 to transmit the second initialization firmware in the second firmware storage unit 080. In the above control process, the first control command and the second control command can specifically act on the high-speed switch in the signal output circuit 050, the high-speed switch in the first firmware transmission circuit 070, and the high-speed switch in the second firmware transmission circuit 090.

[0081] In addition, the baseboard management controller 100 is also used to monitor the temperature of key components on the graphics processing module, as well as the voltage and current information of each power supply. After being collected and processed, this information is reported to the upper-level management system, realizing real-time monitoring and management of the health status of the graphics processing module.

[0082] In this embodiment, the baseboard management controller 100 controls each component in the graphics processing module and senses the overall working status of the graphics processing module.

[0083] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0084] The complex programmable logic device 110 is connected to the central processing unit 010 and the baseboard management controller 100, respectively.

[0085] Specifically, to handle strict timing logic and low-speed interface conversion, the graphics processing module also includes a complex programmable logic device (CPLD) 110. The CPLD 110 is used to power on various components in the graphics processing module, such as the central processing unit (CPU) 010 and the chipset 020, in a predetermined order and time interval, avoiding hardware damage or startup failure due to timing errors. As an example, the CPLD 110 can be a GW1N-LV4PG256C6 / I5.

[0086] The complex programmable logic device 110 is connected to both the central processing unit 010 and the baseboard management controller 100, and works in conjunction with the baseboard management controller 100 to handle the timing relationships of various components. For example, in a typical control scenario, when the baseboard management controller 100 receives a signal indicating that the target graphics processor has been switched to the second graphics processor 041, it will not immediately release the reset signal of the second graphics processor 041. Instead, it will wait for a good power signal sent by the complex programmable logic device 110 to confirm that the power supply of the entire graphics processing module has stabilized before controlling the reset signal of the second graphics processor 041 to go high, thus officially enabling the second graphics processor 041 to leave the reset state and start working. When the baseboard management controller 100 receives a signal indicating that the target graphics processor has been switched to the first graphics processor 021, it will clamp the reset signal of the second graphics processor 041 to a low level, keeping the second graphics processor 041 in a disabled state.

[0087] In this embodiment, the complex programmable logic device 110 and the baseboard management controller 100 work together to maintain the internal timing of the graphics processing module and the power state of each device, which greatly improves the stability and reliability of the graphics processing module.

[0088] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0089] Multiple memory controllers 120 are connected to the central processing unit 010; among them, the memory controllers 120 are used to connect to the first dynamic random access memory, which serves as the system memory of the graphics processing module.

[0090] Specifically, the central processing unit 010 is connected to multiple memory controllers 120, which can be integrated inside the central processing unit 010 or connected to the central processing unit 010 as external components. The memory controllers 120 are used to connect to a first dynamic random access memory, which can be a DDR4 (Double Data Rate SDRAM Gen4) chip.

[0091] In one embodiment, the central processing unit 010 integrates two DDR4 memory controllers 120 to achieve a dual-channel memory configuration. The first dynamic random access memory adopts CXDQ3A8AM-WG, and the two DDR4 memory controllers 120 are connected to 36 CXDQ3A8AM-WG chips to achieve 32GB of system memory.

[0092] In one embodiment, the graphics processing module further includes:

[0093] The video memory controller 130 is connected to the chipset 020; wherein, the video memory controller 130 is used to connect to the second dynamic random access memory, which serves as the system video memory of the graphics processing module.

[0094] Specifically, the memory controller 130 is connected to the chipset 020. The memory controller 130 can be integrated inside the chipset 020 or connected to the chipset 020 as an external component. The memory controller 130 is used to connect a second dynamic random access memory (DRAM), which can be an LPDDR4 (Low Power Double Data Rate SDRAM Gen4) chip. As an example, the second DRAM can be a CXDB5CCAM-MK.

[0095] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0096] Ethernet controller 140 is connected to central processing unit 010;

[0097] Multiple Ethernet port chips 150 are connected to Ethernet controller 140.

[0098] Specifically, to provide rich network connectivity, the graphics processing module also includes an Ethernet controller 140 and multiple Ethernet port chips 150. The Ethernet controller 140 is connected to the central processing unit 010, and the multiple Ethernet port chips 150 are all connected to the Ethernet controller 140. In one embodiment, the central processing unit 010 integrates an RGMII (Reduced Gigabit Media Independent Interface) interface and is connected to the Ethernet controller 140 via a PCIe 2.0 x4 interface. The Ethernet controller 140 outputs a Gigabit Ethernet electrical interface (1000base-T). The Ethernet controller 140 is connected to multiple Ethernet port chips 150, which convert the digital signals output by the Ethernet controller 140 into analog signals that can be transmitted over physical media, and then into Gigabit Ethernet optical interfaces (1000base-X) for external output.

[0099] In this embodiment, an Ethernet controller 140 and multiple Ethernet port chips 150 are provided to offer multiple network interface types for the graphics processing module, thereby meeting the networking requirements of the graphics processing module.

[0100] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0101] Clock chip 160 is connected to central processing unit 010.

[0102] Specifically, to synchronize the various components within the graphics processing module, the module also includes a clock chip 160, which is connected to the central processing unit 010. The clock chip 160 receives a basic crystal oscillator signal and then uses an internal phase-locked loop (PLL) circuit to multiply and divide the frequency to generate a series of clock signals of different frequencies required by the graphics processing module. For example, the clock chip 160 provides the necessary reference clocks for the central processing unit 010, memory controller 120, Ethernet controller 140, and others.

[0103] In this embodiment, the clock chip 160 provides a reference clock for each component in the graphics processing module, enabling all components in the graphics processing module to work synchronously, thus improving the stability of the graphics processing module.

[0104] Continue to refer to Figure 2 In one embodiment, the graphics processing module further includes:

[0105] The VPX connector, which connects at least to the signal output circuit 050, the baseboard controller, the chiplet chipset 020, the Ethernet controller 140, and multiple Ethernet port chips 150, is used to provide an external interface for the graphics processing module.

[0106] Specifically, the graphics processing module provides an external interface through the VPX connector, as shown in the reference. Figure 3 In one embodiment, the graphics processing module provides one PCIe 3.0 x8 interface, one USB 3.0 interface, four USB 2.0 interfaces, one Gigabit Ethernet electrical interface (1000base-T), three Gigabit Ethernet optical interfaces (1000base-X), three HDMI 2.0 interfaces, a GPIO interface, two RS422 interfaces, an RS232 interface, two IPMI interfaces, and +12V and +3.3V power input interfaces via a VPX connector.

[0107] Specifically, combined Figure 2The PCIe 3.0 x8 interface is provided by the graphics card connector 030; the USB 3.0 and USB 2.0 interfaces are provided by the USB interface on the central processing unit 010; the Gigabit Ethernet electrical interface is provided by the Ethernet controller 140; the Gigabit Ethernet optical interface is provided by the Ethernet port chip 150; the HDMI 2.0 interface is provided by the signal output circuit 050; the GPIO interface is provided by the central processing unit 010; the RS422 interface is provided by the UART interface on the chipset 020 after conversion by the transceiver SIT3490; the RS232 interface is provided by the UART interface on the central processing unit 010 after conversion by the transceiver SIT3232EESE; the IPMI interface (not shown in the figure) is provided by the backplane management controller 100; the +12V power input interface is used to power the DC-DC power supply in the graphics processing module; and the +3.3V power input interface is used to power the backplane management controller 100. In this embodiment, based on the VPX connector, the graphics processing module is mounted on a standard 6U VPX architecture circuit board.

[0108] In one embodiment, the graphics processing module further includes:

[0109] Expand memory and connect to chipset 020.

[0110] Specifically, the chipset 020 is connected to an expansion memory. As an example, the expansion memory may include an mSATA disk, which is connected to the chipset 020 via a SATA 3.0 interface on the chipset 020 to provide expandable storage space for the graphics processing module.

[0111] Reference Figure 4 In one embodiment, a computer device is provided, the computer device including the graphics processing module described in any of the above embodiments.

[0112] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A graphics processing module, characterized in that, include: CPU; A chipset assembly connected to the central processing unit, wherein a first graphics processor is integrated in the chipset assembly; A graphics card connector is connected to the central processing unit, and the graphics card connector is equipped with a discrete graphics card including a second graphics processor; A signal output circuit is connected to the chipset and the graphics card connector. The signal output circuit includes a first display signal output path and a second display signal output path. The first display signal output path outputs a first display signal, and the second display signal output path outputs a second display signal. The first display signal is a display signal output by the first graphics processor, and the second display signal is a display signal output by the second graphics processor.

2. The graphics processing module according to claim 1, characterized in that, The signal output circuit includes at least one high-speed switch and at least one graphics signal converter. The first end of the graphics signal converter is connected to the graphics signal interface of the chipset. The second end of the graphics signal converter is connected to the first switching end of the high-speed switch. The second switching end of the high-speed switch is connected to the graphics card connector. The common end of the high-speed switch outputs the first display signal or the second display signal.

3. The graphics processing module according to claim 1, characterized in that, Also includes: The first firmware transmission circuit is connected to the central processing unit; The second firmware transmission circuit is connected to the chipset; The first firmware storage unit is connected to the first firmware transmission circuit and stores a first boot firmware for the first graphics processor and a second boot firmware for the second graphics processor. The second firmware storage unit is connected to the second firmware transmission circuit and stores a first initialization firmware for the first graphics processor and a second initialization firmware for the second graphics processor.

4. The graphics processing module according to claim 3, characterized in that, Also includes: The baseboard management controller is connected to the central processing unit, the signal output circuit, the first firmware transmission circuit, and the second firmware transmission circuit, respectively.

5. The graphics processing module according to claim 4, characterized in that, Also includes: Complex programmable logic devices are connected to the central processing unit and the baseboard management controller, respectively.

6. The graphics processing module according to claim 1, characterized in that, Also includes: Multiple memory controllers are connected to the central processing unit; wherein, the memory controllers are used to connect to a first dynamic random access memory, which serves as the system memory of the graphics processing module.

7. The graphics processing module according to claim 1, characterized in that, Also includes: A video memory controller is connected to the chipset; wherein the video memory controller is used to connect to a second dynamic random access memory, the second dynamic random access memory serving as the system video memory of the graphics processing module.

8. The graphics processing module according to claim 1, characterized in that, Also includes: Ethernet controller, connected to the central processing unit; Multiple Ethernet port chips are connected to the Ethernet controller.

9. The graphics processing module according to claim 1, characterized in that, Also includes: A clock chip is connected to the central processing unit.

10. A computer device, characterized in that, It includes the graphics processing module as described in any one of claims 1 to 9.

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