Circuits and integrated circuits

Abstract

The present disclosure relates to circuits and integrated circuits. A circuit includes a memory array including a plurality of main memory cells and a set of dummy memory cells. The set of dummy memory cells includes a dummy bit line and a timer dummy memory cell substantially identical to the memory cells and coupled to the dummy bit line. The set of dummy memory cells includes a modified dummy memory cell coupled to the dummy bit line and configured to output a detection signal indicating that a voltage on the dummy bit line has crossed a threshold.

Description

Technical Field

[0001] This disclosure relates to computer memory, and more specifically, to signal timing of memory. Background Technology

[0002] In some microcontroller systems, normally open memory (NOT) is used to ensure a smooth system wake-up. This memory remains in reserved mode for most of its operational lifetime. For low-power applications, keeping the memory's static power consumption low is beneficial.

[0003] All topics discussed in the Background section are not necessarily prior art, nor should they be considered prior art simply because they have been discussed in the Background section. Following these lines of thought, unless explicitly stated otherwise, any awareness of problems in the prior art discussed in the Background section, or problems related to such topics, should not be considered prior art. Rather, the discussion of any topic in the Background section should be considered as part of the inventor's method for addressing a particular problem, which in itself can be inventive. Utility Model Content

[0004] Embodiments of this disclosure provide a memory circuit including a memory cell array and a group of virtual bit cells, the virtual bit cells being substantially identical to the memory cells. One of the virtual bit cells is modified to function as a detection device to detect when a virtual bit line has discharged below a threshold. The detection device outputs a detection signal to a virtual bit line precharge circuit. The virtual bit line precharge circuit then outputs a sense amplifier enable signal, which enables the sense amplifier to read data from one of the memory cells.

[0005] In one embodiment, a circuit includes a memory array comprising a plurality of main memory cells and a group of virtual memory cells. The group of virtual memory cells includes: a virtual bit line; a timer virtual memory cell substantially identical to the memory cells and coupled to the virtual bit line; and a modified virtual memory cell coupled to the virtual bit line and configured to output a detection signal indicating that a voltage on the virtual bit line has exceeded a threshold.

[0006] In some examples, the timer virtual memory cell and the modified virtual memory cell include the same number of transistors.

[0007] In some examples, the timer virtual memory cell includes a first inverter and a second inverter cross-coupled together, wherein the modified virtual memory cell includes a third inverter and a fourth inverter, wherein the input of the third inverter is electrically isolated from the output of the fourth inverter.

[0008] In some examples, the third inverter is a detection device having an input coupled to a virtual bit line and an output that provides the detection signal.

[0009] In some examples, the timer virtual memory cell includes a first inverter and a second inverter cross-coupled together, and the modified virtual memory cell includes a third inverter and a fourth inverter, wherein the first power input of the fourth inverter is floating.

[0010] In some examples, the second power input of the fourth inverter is floating.

[0011] In some examples, the circuit includes a virtual bit line precharge circuit configured to precharge the virtual bit lines.

[0012] In some examples, the virtual bitline precharge circuit is configured to receive the detection signal.

[0013] In some examples, the circuit includes a sense amplifier coupled to a column of main memory cells and coupled to a virtual bit line precharge circuit, wherein the virtual bit line precharge circuit is configured to output a sense amplifier enable signal to the sense amplifier in response to receiving the detection signal.

[0014] In some examples, the circuitry includes: word lines coupled to rows of main memory cells; and virtual word lines coupled to timer virtual memory cells.

[0015] In one embodiment, a method includes: enabling a word line coupled to a selected memory cell in a memory cell array; and enabling a virtual word line coupled to a timer virtual memory cell in a group of virtual memory cells. The method includes: sensing, using modified virtual memory cells in the virtual memory cell array, that a virtual bit line coupled to the timer virtual memory cell and the modified virtual memory cell has crossed a threshold voltage. The method includes: in response to the virtual bit line crossing the threshold voltage, providing a sense amplifier enable signal to a sense amplifier coupled to the bit line coupled to the selected memory cell.

[0016] In some examples, the timer virtual memory cell is essentially the same as the memory cell.

[0017] In some examples, the method includes: reading data from a memory cell using a sense amplifier in response to receiving a sense amplifier enable signal.

[0018] In some examples, timer virtual memory cells and modified virtual memory cells are located in the column of virtual memory cells.

[0019] In some examples, the method includes: outputting a detection signal from an inverter of a modified virtual memory cell having an input coupled to the virtual bit line in response to the virtual bit line crossing a threshold voltage; receiving the detection signal using a virtual bit line precharge circuit; and outputting a sense amplifier enable signal from the virtual bit line precharge circuit to a sense amplifier in response to receiving the detection signal.

[0020] In some examples, the method includes keeping the power input of the second inverter of the modified virtual memory cell in a floating state.

[0021] In some examples, the method includes electrically isolating the input of the first inverter from the output of the second inverter of the modified virtual memory cell.

[0022] In one embodiment, an integrated circuit includes a microcontroller and normally open (NOT) circuitry. The NOT circuitry includes logic circuitry and memory circuitry. The logic circuitry includes a plurality of transistors having a first gate dielectric of a first thickness. The memory circuitry includes a plurality of memory cells, each memory cell including a plurality of transistors having a second gate dielectric of a second thickness greater than the first thickness. The memory circuitry includes a group of virtual memory cells, comprising a load memory cell substantially identical to the memory cell and a modified virtual memory cell. The modified virtual memory cell includes a detection device configured to output a detection signal in response to a voltage on a virtual bit line coupled to the timer virtual memory cell and the modified virtual memory cell exceeding a threshold voltage.

[0023] In some examples, the integrated circuit includes a microcontroller coupled to a normally open circuit, wherein the normally open circuit is configured to output an interrupt to wake up the microcontroller.

[0024] In some examples, the integrated circuit includes a radio device coupled to the microcontroller. Attached Figure Description

[0025] Figure 1 This is a block diagram of an integrated circuit according to one embodiment.

[0026] Figure 2 This is a schematic diagram of a memory circuit of an integrated circuit according to one embodiment.

[0027] Figure 3 This is a graph of signals related to a memory read operation according to one embodiment.

[0028] Figure 4A This is a schematic diagram of a timer virtual memory cell of a memory circuit according to one embodiment.

[0029] Figure 4B According to one embodiment Figure 4A The layout of the timer virtual memory unit.

[0030] Figure 5A This is a schematic diagram of a modified virtual memory cell according to one embodiment of a memory circuit.

[0031] Figure 5B According to one embodiment Figure 5A The layout of the modified virtual memory cells.

[0032] Figure 6 This is a schematic diagram of a modified virtual memory cell according to one embodiment of a memory circuit.

[0033] Figure 7 This is a flowchart of a method for operating a memory circuit according to one embodiment. Detailed Implementation

[0034] In the following description, various specific details are shown to enable a thorough understanding of the embodiments. Embodiments may be provided without one or more of these specific details or using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0035] Within the framework of this specification, references to "embodiment" or "an embodiment" mean that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in one embodiment," "in one embodiment," etc., that may appear at various points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific constructions, structures, or features may be combined in any suitable manner.

[0036] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more of these specific details or using other methods, components, materials, etc.

[0037] Unless the context otherwise requires, throughout the specification and the following claims, the word “comprising” and its variations, such as “including” and “contains”, shall be interpreted in an open-ended sense, meaning “including but not limited to”. Furthermore, unless the context expressly provides otherwise, “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable.

[0038] As used in this specification and the appended claims, unless otherwise expressly stated, the singular forms of “a,” “an,” and “the” include plural references. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or,” unless otherwise expressly stated.

[0039] As used in this article, "source / drain terminal" can refer to either the source terminal or the drain terminal of a transistor.

[0040] As used herein, the terms “bit cell” and “memory cell” are used interchangeably.

[0041] Figure 1 This is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes a normally open circuit 101 having a memory circuit 102, a controller 104, and a main radio device 106.

[0042] In one embodiment, integrated circuit 100 is a system-on-a-chip (SoC), but other types of integrated circuits may be used without departing from the scope of this disclosure. In one embodiment, integrated circuit 100 is installed in a device as part of an Internet of Things (IoT).

[0043] For most of its operational lifespan, integrated circuit 100 can be in sleep mode or standby mode. In sleep mode, controller 104 and main radio 106 are powered off. This is to ensure low power consumption of integrated circuit 100.

[0044] However, integrated circuit 100 includes normally open circuit 101. Normally open circuit 101 is a circuit that is always powered on or awake. Normally open circuit may include simple logic circuitry capable of performing basic control functions. However, the logic circuitry of normally open circuit 101 does not perform the control functions that microcontroller 104 can perform.

[0045] Normally open circuit 101 includes memory circuit 102. Memory circuit 102 includes an array of memory cells. Memory circuit 102 also includes peripheral circuitry, such as read control circuitry, access control circuitry, a decoder, a sense amplifier, and other circuitry for managing the operation of the memory cells.

[0046] In one embodiment, memory circuitry 102 includes an SRAM array. In one embodiment, each SRAM memory cell is a six-transistor memory cell, which includes a pair of cross-coupled inverters and two access transistors. While other blocks of integrated circuit 100 are asleep, the memory array operates primarily in a hold mode.

[0047] In one embodiment, since the SRAM array is a normally-on array, it is beneficial to reduce the power consumption of the memory cells in reserved mode. In particular, it is beneficial to reduce the leakage current of the memory cells. In one embodiment, the reduction of leakage current is achieved by implementing the transistors of the memory cells with a relatively large gate dielectric compared to other transistors in the peripheral circuit of the normally-on circuit 102. Thus, the normally-on circuit 101 includes peripheral transistors with thin gate dielectrics and memory cell transistors with gate dielectrics thicker than those of the peripheral transistors. In one embodiment, the thickness of the thicker gate dielectric can be greater than or equal to twice the thickness of the thinner gate dielectric. In one embodiment, an ultra-high threshold voltage transistor can be used to reduce leakage.

[0048] However, variations in manufacturing processes, using transistors with different gate dielectric thicknesses, can cause problems with memory read and write operations. For example, the self-time of an SRAM read operation can correspond to the time between the edge of the clock signal that initiates the read operation and the data read (corresponding to the completion of the read operation). For instance, when a read operation is to be performed, the rising edge of the clock signal can trigger the rising edge of the word line enable signal provided to the row of the selected memory cell. The true bit line and dummy bit line coupled to the memory cell can be pre-charged. Once the true bit line and dummy bit line have been charged to the desired voltage difference, the sense amplifier coupled to the true bit line and dummy bit line reads the data from the memory cell. More specifically, a sense amplifier enable signal is provided to the sense amplifier to trigger the data read.

[0049] One possible solution for generating the sense amplifier enable signal is to include multiple dummy memory cells adjacent to the memory cells of the main memory array, and to generate the sense amplifier enable signal by detecting the discharge of dummy bit lines coupled to the dummy memory cells. The dummy memory cells correspond to replicas of the main memory cells implemented with thicker gate oxide. The dummy memory cells are column-coupled to true dummy bit lines and one or more dummy word lines. A discharge detection circuit is implemented in the peripheral circuitry. The dummy word line goes high as the word line goes high, and either the true or dummy dummy bit line begins to discharge. More specifically, the dummy memory is pre-programmed to discharge either of these dummy bit lines, and a discharge detection circuit is placed for that dummy bit line. The discharge detection circuit detects when the dummy bit line has discharged to a selected threshold. When the dummy bit line has discharged to the selected threshold, the discharge detection circuit causes the sense amplifier enable signal to be output. At the end of the cycle, the dummy bit line is preset again to begin the next operation. Thus, one dummy bit line discharges while the other remains stable.

[0050] One problem with this potential solution is that the discharge detection circuitry is implemented using thin gate oxide transistors, while the virtual memory cells and main memory cells are implemented using thicker gate oxide transistors. Due to this process variation, incorrect timing of the sense amplifier enable signal is possible.

[0051] The embodiments of this disclosure overcome these drawbacks by implementing a discharge detection device within a virtual memory cell. More specifically, one virtual memory cell is modified to serve as a detection device for detecting discharges on virtual bit lines. Because the discharge detection device is implemented within the virtual memory cell, it is implemented using a transistor with a thicker gate oxide. As a result, the discharge detection device can trigger the sense amplifier enable signal in a manner substantially unaffected by process variations. Further details regarding the discharge detection device are provided below.

[0052] Figure 2 This is a schematic diagram of a memory circuit 102 according to one embodiment. The memory circuit 102 includes a memory array 110. The memory array 110 includes an array of SRAM bit cells (BCs) 112. For simplicity, Figure 2 Two columns of memory cells 112 are shown. Each column of memory cells 112 includes four memory cells. In practice, the memory array 110 may include multiple columns of memory cells 112. Each column of memory cells 112 may include multiple memory cells. As previously described, the memory cells 112 are implemented using transistors with thicker gate oxides.

[0053] Each column of memory cells 112 is coupled to a pair of bit lines. Or, in particular, each column of memory cells 112 is coupled to a true bit line (BLT) and a dummy bit line (BLF). Thus, each memory cell in a column is coupled to both the true bit line and the dummy bit line.

[0054] Each column of memory cells 112 is coupled to a column multiplexer 114. The column multiplexer 114 is used to select a column of memory cells for a read or write operation. Therefore, each column multiplexer 114 may include an access transistor or other gates or devices that enable the selection of a column of memory cells for a read or write operation.

[0055] Each row of memory cells is coupled to a word line (WL). Each word line enables the selection of a row of memory cells for a read or write operation. Therefore, the selected row and selected column correspond to the selected memory cell 112.

[0056] Each column is coupled to a sense amplifier (SA) 116. More specifically, the true bit line and dummy bit line of each column are coupled to the sense amplifier 116 via a column multiplexer 114.

[0057] In one embodiment, the true bit line and the dummy bit line are pre-charged to VDD prior to a read operation. During a read operation of the selected memory cell 112, the true bit line or dummy bit line is discharged based on the data in the memory cell to generate a differential voltage (the voltage difference between the BLT and BLF). It is beneficial to enable the sense amplifier 116 to read the data value Qi from the memory cell 112 once the true bit line or dummy bit line has discharged to a sufficient differential voltage. However, if the discharge time is too short, the differential voltage may not be large enough for a reliable read operation once the sense amplifier 116 is enabled. If the discharge time is too long, the differential voltage may be too large, resulting in unnecessary power consumption. Therefore, it is beneficial to control the timing of the sense amplifier enable signal SAEN to ensure that the differential voltage is within a selected range.

[0058] Memory circuitry 102 includes a plurality of virtual bit cells (DBCs) 113. The virtual bit cells 113 are arranged in a column. Each virtual bit cell 113 is coupled to a true virtual bit line (DBLT) and a dummy virtual bit line (DBLF). The true and dummy virtual bit lines are coupled to a virtual bit line precharge circuit 122. One or more virtual bit cells are coupled to a virtual word line (DWL). Virtual bit cells 113 are replicas of bit cells 112 and are implemented using thick gate oxide. Further details regarding virtual bit cells 113 will be described below.

[0059] The memory circuit 102 also includes peripheral circuitry. The peripheral circuitry includes a virtual bit line precharge circuit 122 and a row decoder 124. The peripheral circuitry is implemented using transistors with thin gate dielectrics. The virtual bit line precharge circuit 122 is coupled to the true virtual bit lines and the dummy virtual bit lines and is configured to precharge the true virtual bit lines and the dummy virtual bit lines and generate a sense amplifier enable signal. The row decoder 124 is coupled to the word lines and the virtual word lines and is configured to selectively enable the word lines and the virtual word lines.

[0060] The virtual bit cell 113 includes one or more discharge / timer virtual bit cells 113a. The timer bit cell 113a stores known data values ​​and is used to generate a sense amplifier enable signal, as will be described in more detail below. The timer virtual bit cell 113a is substantially the same as the bit cell 112 of the memory array 110.

[0061] This column of virtual bit cells includes virtual bit cell 113b. Virtual bit cell 113b is identical to timer virtual bit cell 113a. Virtual bit cell 113b is not used to store virtual data like timer virtual bit cell 113a. However, in one embodiment, all virtual bit cells 113b can be timer bit cells 113a. Virtual bit cell 113b can be referred to as a "load" virtual bit cell. One difference between load virtual bit cell 113b and timer virtual bit cell 113a is that the word line terminal (control gate of the access transistor) of load virtual bit cell 113b is connected to ground.

[0062] This column of virtual bit cells includes a modified virtual bit cell 113c. The modified virtual bit cell 113c also serves as a detection device 120. Except that some interconnects have been modified or removed to allow the modified analog bit cell 113c to be used as the detection device 120, the modified virtual bit cell 113c is identical to virtual bit cells 113a and 113b. The modified virtual bit cell 113c includes memory cell 112 and six transistors from the other virtual bit cells 113a and 113b. However, one or more interconnects have been modified. The detection device 120 is coupled to a virtual bit line precharge circuit 122 and provides a detection signal to the virtual bit line precharge circuit 122, as will be described in more detail below.

[0063] Figure 3 This is a graph 300 illustrating signals associated with a read operation of a memory cell according to one embodiment. Also refer to... Figure 2 The memory circuit 102 is used to describe the curve 300.

[0064] Graph 300 includes a clock signal CK and word line / virtual word line signals WL / DWL. To perform a read operation on the selected memory cell 112, the word line signals WL / DWL go high in response to the rising edge of the clock signal CK. Therefore, the selected word line WL and the virtual word line WL go high on the rising edge of the clock signal CK. Although Figure 2 Although not shown, memory circuit 102 may include a clock generator that generates a clock signal CK. Alternatively, the clock generator may be external to memory circuit 102.

[0065] When the virtual word line goes high, the timer virtual bit cell 113a is enabled. The virtual bit line begins to discharge, as shown in... Figure 3 As can be seen, the modified virtual bit unit 113c, used as the detection device 120, detects when the virtual bit line has discharged to a threshold. The detection device 120 outputs a detection signal indicating that the virtual bit line has discharged to the threshold.

[0066] The virtual bitline precharge circuit 122 receives a detection signal from the detection device 120. In response to the detection signal, the virtual bitline precharge circuit 122 outputs a sense amplifier enable signal SAEN after a selected delay. The sense amplifier enable signal is provided to the sense amplifier 116. The sense amplifier 116 reads the data value Qi from the selected memory cell 112.

[0067] Figure 4A This is a schematic diagram of a timer virtual bit unit 113a according to one embodiment. The memory unit 112 is substantially the same as the timer virtual bit unit 113a. The virtual bit unit 113a includes inverters 126 and 128 cross-coupled together. Specifically, the output of inverter 126 is coupled to the input of inverter 128. The output of inverter 128 is coupled to the input of inverter 126. Each of inverters 126 and 128 includes both a PMOS transistor and an NMOS transistor. Each inverter receives VDD at a high power supply terminal and ground at a low power supply terminal.

[0068] Virtual bit cell 113a includes an access transistor T1 coupled between the output of inverter 126 and the dummy virtual bit line DBLF. Virtual bit cell 113a also includes an access transistor T2 coupled between the output of inverter 128 and the true virtual bit line DBLT. Figure 4A In the example, the output of virtual bit cell 113a is the output of inverter 128. In other words, the output of inverter 128 is the real data storage node of virtual bit cell 113a.

[0069] Figure 4B According to one embodiment Figure 4AA simplified layout of the virtual bit unit 113a is shown. This layout illustrates four active regions A1-A4. These active regions correspond to the active regions of the semiconductor substrate. This layout also illustrates two gate bands G1 and G2. Gate bands G1 and G2 cover each of the active regions A1-A4. Each gate band corresponds to a gate metal covering the semiconductor substrate. A transistor is formed at each location where one of the gate bands covers one of the active regions. N-channel transistors are formed at active regions A1 and A4. P-channel transistors are formed at active regions A2 and A3.

[0070] The N-channel transistor N1 of inverter 126 is formed at the overlap of G1 and A1. The P-channel transistor P1 of inverter 126 is formed at the overlap of G1 and A2. The N-channel transistor N2 of inverter 128 is formed at the overlap of G2 and A4. The P-channel transistor P2 of inverter 128 is formed at the overlap of G2 and A3. Transistor T1 is formed at the overlap of G2 and A1. Transistor T2 is formed at the overlap of G1 and A4. The first P-channel dummy transistor D1 is formed at the overlap of G1 and A3. The second P-channel dummy transistor D2 is formed at the overlap of G2 and A2.

[0071] Metal tracks 140, 144, 150, 158, 164, 172, 176, 178, 182, and 184 are formed in the active region of the gate band. In practice, the metal tracks are formed in the interlayer dielectric layer above the substrate and the gate band.

[0072] Ground voltage is applied to metal track 140 via contact 141. Ground is applied to the source terminal of transistor N1 via contact 143. The drain terminals of transistors N1 and P1 are coupled together via metal track 144 and contact 145 to 147. More specifically, contact 145 connects metal track 144 to the drain terminal of transistor N1, contact 147 connects metal track 144 to the drain terminal of transistor P1, and contact 149 connects metal track 144 to the gate terminals of transistors N2 and P2. Therefore, metal track 144 corresponds to the output terminal of inverter 126 and the input terminal of inverter 128.

[0073] Metal track 150 receives VDD via contact 151. Then, VDD is applied to the source terminal of transistor P1 via contact 153, to the source terminal of transistor D1 via contact 155, and to the gate terminal of transistor D1 via contact 157.

[0074] The drain terminals of transistors N2 and P2, and the gate terminals of transistors P1 and N1, are coupled together in contacts 159, 161, and 163 via a metal track 158. More specifically, the metal track 158 is coupled to the gate terminals of transistors P1 and N1 via contact 159, to the drain terminal of transistor P2 via contact 161, and to the drain terminal of transistor N2 via contact 163.

[0075] Metal track 164 receives VDD via contact 164. VDD is supplied to the source terminal of transistor P2 via contact 171, to the source terminal of transistor D2 via contact 167, and to the gate terminal of transistor D2 via contact 169.

[0076] Metal track 172 receives ground voltage via contact 173. Ground voltage is applied to the source terminal of transistor N2 via contact 175.

[0077] Metal track 176 is coupled to the dummy bit line via contact 177. Metal track 176 is coupled to the source / drain terminals of transistor T1 via contact 191.

[0078] Metal track 178 is coupled to the virtual word line via contact 179. Metal track 178 is coupled to the gate of transistor T1 via contact 181.

[0079] Metal track 182 is coupled to the real / virtual bit line via contact 183. The source / drain terminals of transistor T2 are coupled to metal track 182 via contact 193.

[0080] Metal track 184 is coupled to the virtual word line via contact 185. Metal track 184 is coupled to the gate terminal of transistor T2 via contact 187.

[0081] Figure 4B Gate bands G1 and G2 are shown as essentially unbroken bands. However, in practice, various breaks exist in gate bands G1 and G2 to ensure that the gate terminals of various transistors are not shorted together. For example, gate band G1 is broken between active regions A2 and A3 and between active regions A3 and A4. As a result, the gate terminals of transistors P1 and D1 are not shorted together, and the gate terminals of transistors D1 and T2 are not shorted together. Gate band G2 is broken between active regions A1 and A2 and between active regions A2 and A3. As a result, the gate terminals of transistors T1 and D2 are not shorted together, and the gate terminals of transistors P2 and D2 are not shorted together.

[0082] Figure 5AThis is a schematic diagram of a modified virtual bit cell 113c corresponding to the detection device 120 according to one embodiment. The modified virtual bit cell 113c includes inverters 126 and 128 and transistors T1 and T2. However, the virtual bit cell 113c is modified from the virtual bit cell 113a in that the output of inverter 126 is not coupled to the input of inverter 128, and the output of inverter 128 is not coupled to the input of inverter 126.

[0083] Inverter 126 serves as the sensing device 120. Specifically, the input of inverter 126 receives the true / virtual bit line voltage as input. Initially, the true / virtual bit line is at VDD, and the output of inverter 126 is ground. As the true / virtual bit line discharges, the voltage eventually crosses a threshold, at which point the output of inverter 126 switches from ground to VDD. Therefore, the output of inverter 126 is a sensing signal. When the sensing signal goes high, after a selected delay, the sense amplifier enable signal also goes high. The value of this threshold can be selected based on the size and other characteristics of the transistors constituting inverter 126.

[0084] Modifications to the virtual bit cell 113c can be implemented by removing one or more contacts, or by modifying or removing one or more metal tracks. This allows for the removal of the cross coupling between inverters 126 and 128.

[0085] Figure 5B It's a modified layout of the virtual bit cell 113c. Besides obtaining... Figure 5A Aside from the modifications made to the virtual bit cell shown, the layout of virtual bit cell 113c is the same as... Figure 4B The layout of the virtual bit cell 113a is basically similar. Specifically, metal tracks 144 and 164 are modified so that contact 149 is now coupled to metal line 164 instead of metal line 144. As a result, the drain terminals of transistors N1 and P1 are no longer coupled to the gate terminals of transistors N2 and P2. Furthermore, the gate terminals of transistors N2 and P2 receive VDD via contact 149 and metal track 164.

[0086] The layout of metal line 158 has been modified relative to the virtual bit cell 113a. In particular, contact 159 has been removed. As a result, the drain terminals of transistors P2 and N2 are no longer coupled to the gate terminals of transistors P1 and N1. In other words, the output of inverter 128 is not coupled to the input of inverter 126.

[0087] Input contacts are added at the gates of transistors N1 and P1. These input contacts couple the true / virtual bit lines to the gates of transistors N1 and P1. In other words, the input of inverter 126 (i.e., the sensing device) is coupled to the true / virtual bit lines.

[0088] Output contacts have been added to metal track 144. The output contacts are coupled to the drain terminals of transistors P1 and N1 via metal track 144 and contacts 145 and 147. In other words, the output of inverter 126 is the output of sensing device 120. Inverter 128 acts as a dummy inverter.

[0089] Figure 6 This is a schematic diagram of a modified virtual bit cell 113c / detection device 120 according to one embodiment. The modified virtual bit cell 113c is substantially the same as virtual bit cell 113a, except that the power supply terminal of inverter 128 no longer receives VDD and ground. As a result, inverter 128 becomes a non-functional virtual inverter. Inverters 128 and 126 are cross-coupled, but since inverter 128 no longer receives VDD and ground, inverter 128 no longer has any effect on inverter 126. The input of inverter 126 is coupled to the true / virtual bit line and serves as the input of detection device 120. The output of inverter 126 provides the detection signal.

[0090] In one embodiment, in addition to the absence of contact 171 and contact 175, Figure 6 The layout of the modified virtual bit unit 113c and Figure 4B The layout of the virtual bit cell 113a is basically similar. As a result, the source terminal of transistor N2 of inverter 128 does not receive ground voltage, and the source terminal of transistor P2 of inverter 128 does not receive VDD.

[0091] Figure 7 This is a flowchart of a method 700 for operating memory circuitry according to one embodiment. Method 700 can utilize... Figures 1-6 The components, systems, and processes described. At 702, method 700 includes enabling a word line coupled to a selected memory cell in a memory cell array. At 704, method 700 includes enabling a virtual word line coupled to a timer virtual memory cell in a group of virtual memory cells. At 706, method 700 includes sensing, using a modified virtual memory cell in the virtual memory cell array, that a virtual bit line coupled to the timer virtual memory cell and the modified virtual memory cell has crossed a threshold voltage. At 708, method 700 includes providing a sense amplifier enable signal to a sense amplifier coupled to the bit line coupled to the selected memory cell in response to the virtual bit line crossing the threshold voltage.

[0092] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A circuit, characterized in that, The circuit includes: A memory array, comprising multiple main memory units; Virtual memory cell group, including: Virtual bit line; The timer virtual memory cell is essentially the same as the memory cell and is coupled to the virtual bit line; The modified virtual memory cell is coupled to a virtual bit line and configured to output a detection signal indicating that the voltage on the virtual bit line has exceeded a threshold.

2. The circuit according to claim 1, characterized in that, The timer virtual memory cell and the modified virtual memory cell both contain the same number of transistors.

3. The circuit according to claim 2, characterized in that, The timer virtual memory unit includes a first inverter and a second inverter cross-coupled together. The modified virtual memory unit includes a third inverter and a fourth inverter, wherein the input of the third inverter is electrically isolated from the output of the fourth inverter.

4. The circuit according to claim 3, characterized in that, The third inverter is a detection device, which has an input coupled to a virtual bit line and an output that provides the detection signal.

5. The circuit according to claim 2, characterized in that, The timer virtual memory cell includes a first inverter and a second inverter cross-coupled together. The modified virtual memory cell includes a third inverter and a fourth inverter, wherein the first power input of the fourth inverter is floating.

6. The circuit according to claim 5, characterized in that, The second power input terminal of the fourth inverter is floating.

7. The circuit according to claim 1, characterized in that, The circuit includes a virtual bitline precharge circuit configured to precharge virtual bitlines.

8. The circuit according to claim 7, characterized in that, The virtual bitline precharge circuit is configured to receive the detection signal.

9. The circuit according to claim 8, characterized in that, The circuit includes: a sense amplifier coupled to a column of a main memory cell and coupled to a virtual bit line precharge circuit, wherein the virtual bit line precharge circuit is configured to output a sense amplifier enable signal to the sense amplifier in response to receiving the detection signal.

10. The circuit according to claim 1, characterized in that, The circuit includes: Word lines are coupled to rows of main memory cells; and The virtual word line is coupled to the timer virtual memory unit.

11. An integrated circuit, characterized in that, The integrated circuit includes: microcontroller; Normally open circuit, including: A logic circuit comprising a plurality of transistors, the transistors having a first gate dielectric of a first thickness; Memory circuitry, including: Multiple memory cells, each memory cell including multiple transistors, the transistors having a second gate dielectric of a second thickness, the second thickness being greater than a first thickness; and The virtual memory cell group includes a load memory cell that is substantially the same as the memory cell and a modified virtual memory cell. The modified virtual memory cell includes a detection device configured to output a detection signal in response to a voltage on a virtual bit line coupled to the timer virtual memory cell and the modified virtual memory cell exceeding a threshold voltage.

12. The integrated circuit according to claim 11, characterized in that, The integrated circuit includes a microcontroller coupled to a normally open circuit, wherein the normally open circuit is configured to output an interrupt to wake up the microcontroller.

13. The integrated circuit according to claim 12, characterized in that, The integrated circuit includes a radio device coupled to the microcontroller.

Images