Memory device

Abstract

A memory device includes a memory array having a plurality of memory cells and a core voltage distribution network connected to the plurality of memory cells. Each memory cell includes a conductive layer over an active region and a first conductive layer connected to the conductive layer over the active region by a first via. The core voltage distribution network includes a second conductive layer including a second conductive layer island connected to the first conductive layer by a second via and a third conductive layer connected to the second conductive layer island by a third via.

Description

Technical Field

[0001] This disclosure relates to a memory device. Background Technology

[0002] Generally, a memory device includes an array of memory cells, such as a static random-access memory (SRAM) cell array. The memory device includes a main power supply voltage, such as a voltage drain-to-drain (VDD) or voltage collector-to-collector (VCC) power supply voltage, which powers the core circuitry (e.g., the memory array) and the input / output (I / O) circuitry of the memory device. The main power supply voltage provides the core power supply voltage, such as a core voltage drain-to-drain (CVDD) power supply voltage, which powers the core circuitry of the memory device, including the memory array.

[0003] To increase the density of memory cells in a memory array, manufacturers attempt to increase the number of word lines (WLs) in the memory array. However, as the number of WLs in the memory array increases, the voltage drop on the CVDD power line also increases, which in turn reduces the maximum voltage Vmax reaching the memory cell and lowers the read static noise margin (RSNM) of the memory cell. Utility Model Content

[0004] The embodiments disclosed herein provide a memory device. The memory device includes a memory array and a core voltage distribution network. The memory array has a plurality of memory cells, and each memory cell includes a conductive layer and a first conductive layer. The conductive layer is located above an active region. The first conductive layer is connected to the conductive layer located above the active region through a first via. The core voltage distribution network is connected to the memory cells, and the core voltage distribution network includes a second conductive layer and a third conductive layer. The second conductive layer includes a second conductive layer island connected to the first conductive layer through a second via. The third conductive layer is connected to the second conductive layer island through a third via.

[0005] The embodiments disclosed herein provide a memory device. The memory device includes a memory array having a plurality of memory cells located in a plurality of rows and columns, and each memory cell includes a conductive layer and a first conductive layer. The conductive layer is located above an active region. The first conductive layer is connected to the conductive layer through a first via. Each column of the memory array includes one of the memory cells, and that memory cell includes a second conductive layer island connected to the first conductive layer through a second via and a third conductive layer connected to the second conductive layer island through a third via.

[0006] The embodiments disclosed herein provide a memory device. The memory device includes a memory array and a core voltage distribution network. The memory array includes a plurality of memory cells, wherein each memory cell includes a conductive layer, a first via, and a first conductive layer. The conductive layer is located above an active region. The first via is located above the conductive layer. The first conductive layer is connected to the conductive layer through the first via. The core voltage distribution network is connected to the memory cells, wherein the core voltage distribution network includes a second via, a second conductive layer, and a dielectric layer. The second via is located above the first conductive layer. The second conductive layer is located above the first conductive layer and includes a second conductive layer island connected to the first conductive layer through the second via. The dielectric layer is located on the second conductive layer island. Attached Figure Description

[0007] The various embodiments of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Furthermore, the accompanying drawings are merely illustrative examples of embodiments of this disclosure and are intended to limit the scope of this disclosure.

[0008] Figure 1 A schematic diagram of a memory device including a memory array according to some embodiments is illustrated, the memory array including a plurality of memory cells connected to a core voltage distribution network (e.g., a CVDD power grid).

[0009] Figure 2 It is configured according to some embodiments. Figure 1 A schematic diagram of the SRAM cell in a memory device;

[0010] Figure 3 According to some embodiments Figure 2 A schematic diagram of the layout of the SRAM cells;

[0011] Figure 4 According to some embodiments Figure 2 A schematic diagram of the layout of another part of the SRAM cell, which includes a second conductive layer island connected to the CVDD power line in the first conductive layer;

[0012] Figure 5 According to some embodiments Figure 2 A schematic diagram of the layout of another part of the SRAM cell, which includes a second conductive layer island connected to the CVDD power line in the third conductive layer;

[0013] Figure 6 A schematic diagram of a memory array according to some embodiments is illustrated, the memory array including power supply voltage islands located in a second conductive layer, one of which appears every four rows in each column of the memory array;

[0014] Figure 7 A schematic diagram of a memory array comprising a plurality of memory cells and power supply voltage lines spanning the memory array (including between memory cells) according to some embodiments is illustrated.

[0015] Figure 8 A schematic diagram illustrating a method for manufacturing a memory device according to some embodiments is shown;

[0016] Figure 9 Exemplary block diagrams illustrating computer systems configured to provide the currently disclosed apparatus (including electronic devices and semiconductor devices) and methods according to some embodiments; and

[0017] Figure 10 This is a block diagram of a semiconductor device manufacturing system and a related semiconductor device manufacturing process according to some embodiments.

[0018] [Symbol Explanation]

[0019] 20,342: Memory device

[0020] 22,200,230: Memory array

[0021] 24,232: Memory units

[0022] 26: Core Voltage Distribution Network

[0023] 28: Line decoder circuit

[0024] 30: Column decoder circuit

[0025] 32: I / O circuit

[0026] 34: Control Circuit

[0027] 36a, 36n: Row lines

[0028] 38a, 38n: Column lines

[0029] 40, 42, 46, 48, 50: Conductive paths

[0030] 44: IO Path

[0031] 80: SRAM cell / memory cell

[0032] 82, 84: Inverters

[0033] 86,88,90,92: Transistor pairs / transistors

[0034] 94, 96: Transistor

[0035] 100, 166, 186: Layout

[0036] 102, 104, 106, 108: Active Zone

[0037] 110, 118, 124, 132, 138, 146, 150, 158: Conductive layers

[0038] 112, 126, 140, 152: Gate

[0039] 114: Bitline

[0040] 116,122,130,136,144,148,156,160,170,174,178,182,184,190,194,198,210a,210b,210c,210d,210e,216a,216b,216c,216d,216e,216f,216g,216h,216i,216j,216k,216l,242: Through holes

[0041] 120, 162, 180, 218a, 218b, 218c, 218d: Character lines

[0042] 128, 154, 192, 196, 214a, 214b, 214c, 214d, 214e: Reference lines

[0043] 134, 188, 208a, 208b, 208c, 208d: Power cord

[0044] 142: Complementary bit line

[0045] 168: Second conductive layer island

[0046] 172, 176: Reference Line Island

[0047] 202a, 202b, 202c, 202d, 202e: Power supply voltage islands

[0048] 204a, 204b, 204c, 204d: Rows / Memory Units

[0049] 206a, 206b, 206c, 206d: Column / Memory Units

[0050] 212a, 212b, 212c, 212d, 212e, 212f, 212g, 212h, 212i, 212j, 212k, 212l: Reference voltage islands

[0051] 234a, 234b, 234c: Power supply voltage lines

[0052] 236a, 236b: lines

[0053] 238: column

[0054] 240: Voltage line

[0055] 250,252,254,256,258,260,262,264,266: Steps 300,322: System

[0056] 302: Processor

[0057] 304: Storage Media

[0058] 306: Instruction

[0059] 308: Manufacturing Tools

[0060] 310: Bus

[0061] 312: I / O Interface

[0062] 314: Network Interface

[0063] 316: Network

[0064] 318: Database

[0065] 320:UI

[0066] 324: Design Company

[0067] 326: Covered Room

[0068] 328: Manufacturing Plant

[0069] 330: Semiconductor Device Design Layout Diagram / Layout Diagram

[0070] 332: Data Preparation

[0071] 334: Mask Manufacturing

[0072] 336: Mask

[0073] 338: Wafer

[0074] 340: Wafer Manufacturing

[0075] M0, M1: Metal layers

[0076] Q, QB: Nodes

[0077] X, Y: Direction / Axis Detailed Implementation

[0078] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed, nor is it intended to limit the relationship between the various embodiments and / or configurations described.

[0079] Additionally, for ease of description, spatially relative terms (e.g., "below," "under," "lower," "above," "upper," and the like) may be used herein to describe the relationship between one component or feature and another, as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and thus the spatially relative descriptive terms used herein may be interpreted accordingly.

[0080] In general, in circuit design, a power grid refers to a network of power lines and reference lines that span an integrated circuit (IC) or printed circuit board (PCB). The power grid ensures stable and efficient power distribution to the various components and subsystems within the circuit. The design purpose of a power grid is to minimize voltage drops, reduce noise, and maintain consistent power delivery throughout the circuit.

[0081] In an SRAM memory device, the CVDD power supply voltage is provided by power supply voltage lines located at the top and bottom edges of the memory array. These power supply voltage lines are formed in a second conductive layer (e.g., metal 1 (M1) layer) and connected to power supply voltage lines formed in a first conductive layer (e.g., metal 0 (M0) layer). The power supply voltage lines in the first conductive layer span the memory array and connect to each memory cell in the memory array. Conversely, reference voltage lines form a reference grid in a third conductive layer (e.g., metal 2 (M2) layer), which spans the memory array and connects to each memory cell through vias and the second conductive layer. Therefore, when the number of WLs is increased to increase the density of memory cells in the memory array, the current-resistance (IR) voltage drop in the power supply voltage lines of the first conductive layer reduces the maximum voltage Vmax of the memory cell and decreases the RSNM of the memory cell, while the reference grid does not cause a decrease in the maximum voltage Vmax or a decay in the RSNM of the memory cell.

[0082] The embodiments disclosed herein provide a memory device including a CVDD power grid. The power grid includes a second conductive layer (e.g., layer M1) having second conductive layer islands connected to a first conductive layer (e.g., layer M0) via vias. The first conductive layer is connected to memory cells in the memory device. A third conductive layer (e.g., layer M2) is connected to the second conductive layer islands via another via to form the CVDD power grid, thereby increasing the maximum voltage Vmax of the memory cells and improving the RSNM of the memory cells.

[0083] In some embodiments, each memory cell includes a second conductive layer island connected to a first conductive layer via a via, and a third conductive layer connected to the second conductive layer island via another via. In some embodiments, the memory device includes a memory array comprising memory cells located in multiple rows and multiple columns, with each column of memory cells comprising one memory cell per 2×N rows, where N is a positive integer, wherein the memory cell includes a second conductive layer island connected to the first conductive layer via a via, and a third conductive layer connected to the second conductive layer island via another via. In some embodiments, the memory array includes word lines in the second conductive layer such that increasing N reduces the number of second conductive layer islands, thereby increasing the power distribution network resistance and increasing the word line area, and thus reducing the word line resistance and capacitance.

[0084] The disclosed embodiments also include a memory device comprising a memory array and a core voltage distribution network. The memory array includes a plurality of memory cells located in a plurality of rows and columns, wherein each memory cell is located on a conductive layer above an active region and a first conductive layer connected to the conductive layer via vias. The core voltage distribution network includes a second conductive layer comprising at least one core voltage distribution line located between the plurality of rows of memory cells in the memory array and connected to the first conductive layer via at least one via. In some embodiments, the at least one core voltage distribution line includes a plurality of core voltage distribution lines located at the top of the memory array, the bottom of the memory array, and between the top and bottom of the memory array, and each core voltage distribution line is connected to the first conductive layer via at least one via. This core voltage distribution network increases the maximum voltage Vmax of the memory cells and improves the RSNM of the memory cells.

[0085] The embodiments disclosed herein also include a method of manufacturing a memory device. The method includes forming a plurality of memory cells in a memory array and forming a core voltage distribution network connected to the plurality of memory cells. Forming each memory cell includes forming a conductive layer over an active region, forming a first via over the conductive layer, and forming a first conductive layer over the conductive layer connected to the conductive layer via the first via. Forming the core voltage distribution network includes forming a second via over the first conductive layer, forming a second conductive layer island over the first conductive layer connected to the first conductive layer via the second via, forming a third via over the second conductive layer island, and forming a third conductive layer over the second conductive layer island connected to the second conductive layer island via the third via.

[0086] Figure 1 A schematic diagram of a memory device 20 according to some embodiments is illustrated. The memory device includes a memory array 22, which includes a plurality of memory cells 24 connected to a core voltage distribution network 26 (e.g., a CVDD power grid). The plurality of memory cells 24 are arranged in multiple rows and columns in an xy grid. In some embodiments, the plurality of memory cells 24 are SRAM cells. In some embodiments, the memory device 20 is an electronic device, one or more semiconductor devices, and / or one or more integrated circuit devices.

[0087] The memory device 20 includes a memory array 22, a row decoder circuit 28, a column decoder circuit 30, an I / O circuit 32, and a control circuit 34. The row decoder circuit 28 is electrically connected to the memory array 22 via row lines 36a-36n extending along the x-direction. The column decoder circuit 30 is electrically connected to the memory array 22 via column lines 38a-38n extending along the y-direction. Multiple rows extend along the x-axis of the xy grid of the memory array 22, and multiple columns extend along the y-axis.

[0088] The I / O circuit 32 is electrically connected to the memory array 22 via conductive paths 40 and 42. The I / O circuit 32 includes input circuitry, output circuitry, and sensing circuitry, configured to store data in and sense data from the memory cells 24. The I / O circuitry receives input data and outputs output data via I / O path 44.

[0089] Control circuit 34 is electrically connected to row decoder circuit 28 and column decoder circuit 30 via conductive paths 46 and 48, and electrically connected to I / O circuit 32 via conductive path 50. Row decoder circuit 28 receives and decodes row addresses, and column decoder circuit 30 receives and decodes column addresses. In addition, control circuit 34 provides instructions to row decoder circuit 28, column decoder circuit 30, and I / O circuit 32 to control the operation of memory device 20.

[0090] Figure 2 It is configured according to some embodiments. Figure 1 A schematic diagram of an SRAM cell 80 in a memory device. The SRAM cell 80 is a six-transistor (6T) SRAM cell. In some embodiments, the SRAM cell 80 is located in... Figure 1 In the memory device 20. In some embodiments, the SRAM cell 80 is located in Figure 1 In the memory array 22 shown. In some embodiments, the SRAM cell 80 is similar to Figure 1 The memory cell 24 is located in the memory cell. In other embodiments, the SRAM cell 80 includes more or fewer than 6 transistors, such as 4, 8, or 10 transistors.

[0091] SRAM cell 80 includes two cross-coupled inverters 82 and 84. The first inverter 82 includes a first PMOS / NMOS transistor pair 86 and 88, and the second inverter 84 includes a second PMOS / NMOS transistor pair 90 and 92. SRAM cell 80 also includes a left transfer gate transistor 94 and a right transfer gate transistor 96.

[0092] Each inverter 82 and 84 is powered, with the first terminals of the left pull-up transistor 86 and the right pull-up transistor 90 electrically connected to the core voltage supply CVDD, and the first terminals of the left pull-down transistor 88 and the right pull-down transistor 92 electrically connected to the reference voltage VSS, for example, ground. A single bit of data is stored as the voltage at node Q in SRAM cell 80 and can be read via the bit line (BL) through the left transfer gate transistor 94, which controls access to node Q. A node (Q bar, QB) stores the complement of the value at node Q; therefore, if node Q is high, node QB is low, and vice versa. Node QB can be read via the complementary bit line (BLB) through the right transfer gate transistor 96, which controls access to node QB.

[0093] The gate of the left transmission gate transistor 94 is coupled to the word line (WL). The first source / drain (S / D) terminal of the left transmission gate transistor 94 is coupled to the bit line (BL), and the second S / D terminal of the left transmission gate transistor 94 is coupled to the left pull-up transistor 86 and the left pull-down transistor 88 located at node Q, and the right pull-up transistor 90 and the right pull-down transistor 92 located at the gate.

[0094] In addition, the gate of the right transfer gate transistor 96 is coupled to the word line (WL). The first S / D terminal of the right transfer gate transistor 96 is coupled to the complementary bit line (BLB), and the second S / D terminal of the right transfer gate transistor 96 is coupled to the second terminal of the right pull-up transistor 90 located at node QB, the right pull-down transistor 92, and the left pull-up transistor 86 and the left pull-down transistor 88 located at the gate.

[0095] Figure 3 According to some embodiments Figure 2 A schematic diagram of the layout 100 of the 6T SRAM cell 80. The layout 100 includes layers adjacent to a first conductive layer, which is a first metal layer M0.

[0096] Layout 100 includes transistors 86, 88, 90, 92, 94, and 96 of SRAM cell 80. Layout 100 includes active regions 102, 104, 106, and 108. The left transmission gate transistor 94 is arranged such that a conductive layer 110 (e.g., a metal over-diffusion (MD) layer) is disposed on the first active region 102 on one side of the gate 112 of the left transmission gate transistor 94. Bit lines (BL) 114 in the first conductive layer contact the conductive layer 110 through a first via 116, such that the bit lines (BL) 114 are connected to the first active region 102 through the first via 116 and the conductive layer 110. Another conductive layer 118 (e.g., a metal over-diffusion (MD) layer) is disposed on the first active region 102 and the second active region 104 on the other side of the gate 112 of the left transmission gate transistor 94. The gate 112 of the left transmission gate transistor 94 is connected to the word line (WL) 120 in the first conductive layer through a second via 122. In some embodiments, one or more dielectric layers (not shown for clarity) are formed on the conductive layers (e.g., conductive layers 110 and 118) and on the gate (e.g., gate 112). Vias (e.g., first via 116 and second via 122) are formed through the dielectric layers. A first conductive layer (e.g., bit line (BL) 114 and word line (WL) 120) is formed on one or more dielectric layers such that the conductive layer is electrically connected to the first conductive layer through the vias.

[0097] The left-pull-down transistor 88 is configured such that a conductive layer 124 (e.g., a metal overdiffusion (MD) layer) is disposed on a first active region 102 on one side of the gate 126, and a reference line 128 in the first conductive layer is connected to the conductive layer 124 through a third via 130. The other side of the gate 126 includes a conductive layer 118 disposed on the first active region 102 and the second active region 104. The left-pull-up transistor 86 is configured such that a conductive layer 132 (e.g., a metal overdiffusion (MD) layer) is disposed on the second active region 104 on one side of the gate 126, and a CVDD power line 134 in the first conductive layer is connected to the conductive layer 132 through a fourth via 136. The other side of the gate 126 includes a conductive layer 118 disposed on the first active region 102 and the second active region 104. The gate 126 of both the left-pull-down transistor 88 and the left-pull-up transistor 86 spans the first active region 102 and the second active region 104. In some embodiments, one or more dielectric layers (not shown for clarity) are formed on the conductive layers (e.g., conductive layers 124 and 132) and on the gate (e.g., gate 126). Vias (e.g., third via 130 and fourth via 136) are formed through the dielectric layers. A first conductive layer (e.g., reference line 128 and CVDD power line 134) is formed on the one or more dielectric layers, such that the conductive layers are electrically connected to the first conductive layer through the vias.

[0098] The right transmission gate transistor 96 is configured such that a conductive layer 138 (e.g., a metal overdiffusion (MD) layer) is disposed on a fourth active region 108 on one side of the gate 140 of the right transmission gate transistor 96. A complementary bit line (BLB) 142 in the first conductive layer contacts the conductive layer 138 through a fifth via 144, such that the complementary bit line (BLB) 142 is connected to the fourth active region 108 through the fifth via 144 and the conductive layer 138. Another conductive layer 146 (e.g., a metal overdiffusion (MD) layer) is disposed on the fourth active region 108 and the third active region 106 on the other side of the gate 140 of the right transmission gate transistor 96. The gate 140 of the right transmission gate transistor 96 is connected to a WL 162 in the first conductive layer through a sixth via 148. In some embodiments, one or more dielectric layers (not shown for clarity) are disposed on the conductive layers (e.g., conductive layers 138 and 146) and on the gate (e.g., gate 140). Vias (e.g., fifth via 144 and sixth via 148) are formed through the dielectric layer. First conductive layers (e.g., complementary bit lines (BLB) 142 and word lines (WL) 162) are formed on one or more dielectric layers, such that the conductive layers are electrically connected to the first conductive layers through the vias.

[0099] The right-pull-down transistor 92 is configured such that a conductive layer 150 (e.g., a metal overdiffusion (MD) layer) is disposed on a fourth active region 108 on one side of the gate 152, and a reference line 154 in the first conductive layer is connected to the conductive layer 150 through a seventh via 156. The other side of the gate 152 includes a conductive layer 146 disposed on the third active region 106 and the fourth active region 108. The right-pull-up transistor 90 is configured such that a conductive layer 158 (e.g., a metal overdiffusion (MD) layer) is disposed on a third active region 106 on one side of the gate 152, and a CVDD power line 134 is disposed on the third active region 106 on one side of the gate 152. The other side of the gate 152 includes a conductive layer 146 disposed on the third active region 106 and the fourth active region 108. The gate 152 of both the right-pull-down transistor 92 and the right-pull-up transistor 90 spans the third active region 106 and the fourth active region 108. In some embodiments, one or more dielectric layers (not shown for clarity) are formed on conductive layers (e.g., conductive layers 150 and 158) and on a gate (e.g., gate 152). Vias (e.g., seventh via 156 and eighth via 160) are formed through the dielectric layers. First conductive layers (e.g., reference line 154 and CVDD power line 134) are formed on one or more dielectric layers such that the conductive layers are electrically connected to the first conductive layers through the vias.

[0100] The conductive layer 118 is electrically connected to the gate 152 of the right pull-down transistor 92 and the right pull-up transistor 90, and the conductive layer 146 is electrically connected to the gate 126 of the left pull-down transistor 88 and the left pull-up transistor 86.

[0101] Figure 4 According to some embodiments Figure 2 A schematic diagram of the layout 166 of an SRAM cell 80 is shown, which includes a second conductive layer island 168 connected to a CVDD power line 134 in a first conductive layer via a ninth via 170. The layout 166 includes a first conductive layer (i.e., a first metal layer M0) and a second conductive layer (i.e., a second metal layer M1). The footprint of the second conductive layer island 168 is located between the footprint of the first conductive layer bit line (BL) 114 and the footprint of the first conductive layer complementary bit line (BLB) 142. The second conductive layer island 168 is connected to a third conductive layer (i.e., a third metal layer M2) to form a CVDD power grid, thereby increasing the maximum voltage Vmax of the memory cell and improving the RSNM of the memory cell. In some embodiments, one or more dielectric layers (not shown for clarity) are disposed on the first conductive layer (e.g., the CVDD power line 134). Vias (e.g., the ninth via 170) are formed through the dielectric layers. A second conductive layer island (e.g., second conductive layer island 168) is formed on one or more dielectric layers, such that the first conductive layer is electrically connected to the second conductive layer island through a via.

[0102] Layout 166 includes reference lines 128 and 154 located in a first conductive layer. Reference line 128 is connected to reference line island 172 in a second conductive layer via a tenth via 174, and reference line 154 is connected to reference line island 176 in the second conductive layer via an eleventh via 178. Reference line island 176 is connected to a third conductive layer (i.e., a third metal layer M2) to form a VSS reference grid. In some embodiments, one or more dielectric layers (not shown for clarity) are formed on the first conductive layer (e.g., reference lines 128 and 154). Vias (e.g., tenth via 174 and eleventh via 178) are formed through one or more dielectric layers. Second conductive layer islands (e.g., reference line islands 172 and 176) are formed on one or more dielectric layers, such that the first conductive layer is electrically connected to the second conductive layer islands through the vias.

[0103] Layout 166 includes WL 120 and WL 162 located in a first conductive layer. Character line 120 in the first conductive layer is connected to character line 180 in a second conductive layer via a twelfth via 182, and character line 162 in the first conductive layer is connected to character line 180 in the second conductive layer via a thirteenth via 184. In some embodiments, one or more dielectric layers (not shown for clarity) are formed on the first conductive layer (e.g., WL 120 and 162). Vias (e.g., twelfth via 182 and thirteenth via 184) are formed through one or more dielectric layers. A second conductive layer (e.g., character line (WL) 180) is formed on one or more dielectric layers such that the first conductive layer is electrically connected to the second conductive layer through the vias.

[0104] Figure 5 According to some embodiments Figure 2 A schematic diagram of the layout 186 of an SRAM cell 80 is shown, which includes a second conductive layer island 168 connected to a CVDD power line 188 in a third conductive layer. The layout 186 includes a second conductive layer (i.e., a second metal layer M1) and a third conductive layer (i.e., a third metal layer M2). The second conductive layer island 168 is connected to the CVDD power line 188 in the third conductive layer through a fourteenth via 190 to form a CVDD power grid, thereby increasing the maximum voltage Vmax of the memory cell and improving the RSNM of the memory cell. In some embodiments, one or more dielectric layers (not shown for clarity) are disposed on the second conductive layer (e.g., the second conductive layer island 168). Vias (e.g., the fourteenth via 190) are formed through one or more dielectric layers. A third conductive layer (e.g., the CVDD power line 188) is formed on one or more dielectric layers, such that the second conductive layer island is electrically connected to the third conductive layer through the vias.

[0105] Layout 186 includes reference line islands 172 and 176 in a second conductive layer, with reference line island 172 connected to VSS reference line 192 in a third conductive layer via a fifteenth via 194, and reference line island 176 connected to VSS reference line 192 in the third conductive layer via a fifteenth via 194. The footprint of the second conductive layer island 168 is located between the footprints of VSS reference line 192 and VSS reference line 196. Furthermore, layout 186 includes a word line (WL) 180 in the second conductive layer. In some embodiments, one or more dielectric layers (not shown for clarity) are disposed on the second conductive layer (e.g., reference line islands 172 and 176 and word line (WL) 180). Vias (e.g., fifteenth via 194 and sixteenth via 198) are formed through the one or more dielectric layers. A third conductive layer (e.g., VSS reference lines 192 and 196) is formed on one or more dielectric layers, such that the second conductive layer is electrically connected to the third conductive layer through vias.

[0106] Figure 6 A schematic diagram of a memory array 200 according to some embodiments is illustrated. The memory array 200 includes power supply voltage islands 202a-202e located in a second conductive layer, one island appearing every four rows in each column of the memory array 200. The memory array 200 includes memory cells 204a-204d located in multiple rows and memory cells 206a-206d located in multiple columns. In some embodiments, the second conductive layer is a second metal layer M1. In some embodiments, the memory array 200 and... Figure 1 The memory array 22 is similar.

[0107] The memory array 200 includes CVDD power lines 208a-208d in a third conductive layer. Each CVDD power line 208a-208d in the third conductive layer is connected to at least one power voltage island 202a-202e in a second conductive layer. CVDD power line 208a is connected to power voltage island 202a in row (0) 204a through a first via 210a, CVDD power line 208b is connected to power voltage island 202b in row (1) 204b through a second via 210b, CVDD power line 208c is connected to power voltage island 202c in row (2) 204c through a third via 210c, CVDD power line 208d is connected to power voltage island 202d in row (3) 204d through a fourth via 210d, and CVDD power line 208d is connected to power voltage island 202e through a fifth via 210e. In some embodiments, the third conductive layer is a third metal layer M2.

[0108] The memory array 200 includes reference voltage islands 212a-212l in a second conductive layer and reference lines 214a-214e in a third conductive layer. Each reference line 214a-214e in the third conductive layer is connected to at least one reference voltage island 212a-212l in the second conductive layer. Reference lines 214a are connected to reference voltage islands 212a and 212b via a sixth via 216a and a seventh via 216b, respectively. Reference lines 214b are connected to reference voltage islands 212c, 212d, and 212e via an eighth via 216c, a ninth via 216d, and a tenth via 216e, respectively. Reference lines 214c are connected to reference voltage islands 212f and 212g via an eleventh via 216f and a twelfth via 216g, respectively. Reference line 214d is connected to reference voltage islands 212h, 212i, and 212j via the thirteenth via 216h, the fourteenth via 216i, and the fifteenth via 216j, respectively. Reference line 214e is connected to reference voltage islands 212k and 212l via the sixteenth via 216k and the seventeenth via 216l, respectively.

[0109] The memory array 200 includes word lines (WL) 218a-218d located in a second conductive layer. One word line (WL) 218a-218d is located in each row 204a-204d. Word lines (WL) 218a-218d are formed around each power supply voltage island 202a-202e and around each reference voltage island 212a-212l. In some embodiments, each column of memory cells 206a-206d includes one memory cell, and the memory cell includes a power supply voltage island in the second conductive layer (e.g., connected to one of the power supply voltage islands 202a-202e of the first conductive layer). The second conductive layer is connected to the first conductive layer (e.g., metal layer M0), i.e., connected to the memory cell, and further connected to a CVDD power line (e.g., one of the CVDD power lines 208a-208d) in a third conductive layer, once every 2×N rows, where N is a positive integer. In some embodiments, N equals 2.

[0110] The memory array 200 includes WL 218a-218d in the second conductive layer; therefore, increasing N reduces word line resistance and capacitance while increasing core voltage distribution network resistance. Furthermore, the relationship between word line resistance and capacitance and core voltage distribution network resistance can be optimized by changing N.

[0111] Figure 7 A schematic diagram of a memory array 230, comprising a plurality of memory cells 232 and power voltage lines 234a-234c spanning the memory array 230 (including between memory cells 232), is illustrated according to some embodiments. The power voltage lines 234a-234c are core voltage distribution lines in a second conductive layer (i.e., a second metal layer M1). The memory array 230 includes memory cells 232 in a plurality of rows 236a and 236b and a plurality of columns (e.g., column 238). In some embodiments, the memory array 230 and... Figure 1 The memory array 22 shown is similar. In some embodiments, memory cells 232 are similar to... Figure 1 The memory cell 24 shown is similar.

[0112] Memory cell 232 and Figure 2 Memory unit 80 and Figures 3 to 5The memory cell layouts 100, 166, and 186 are similar. Each memory cell 232 includes a conductive layer located above the active region. CVDD voltage lines 240 in the first conductive layer (first metal layer M0) are connected to power supply voltage lines 234a-234c and the conductive layer of the memory cell 232 through vias 242. The memory cell 232 receives the CVDD core voltage from the power supply voltage lines 234a-234c through the CVDD voltage lines 240 connected to the conductive layer of the memory cell 232. Due to the presence of one or more additional power supply voltage lines 234a-234c, the resistance from the power supply voltage lines 234a-234c through the CVDD voltage lines 240 to the memory cell 232 is reduced, thereby increasing the maximum voltage Vmax of the memory cell 232 and improving the RSNM of the memory cell 232. In some embodiments, power supply line 234a is located at the top of memory array 230, power supply line 234c is located at the bottom of memory array 230, and power supply line 234b is located in the middle of memory array 230.

[0113] In some embodiments, power supply voltage lines 234a-234c (also referred to as core voltage distribution lines) are located between memory cells 232 in the memory array 230 and connected to the CVDD voltage line 240 through vias 242. In some embodiments, power supply voltage lines 234a-234c are located between every other row of memory cells 232 in the memory array 230 and connected to the CVDD voltage line 240 through vias 242.

[0114] Figure 8 A schematic diagram illustrating a method for manufacturing a memory device according to some embodiments is shown. In step 250, the method includes forming a plurality of memory cells in a memory array, wherein forming each memory cell includes: in step 252, forming a conductive layer over an active region; in step 254, forming a first via over the conductive layer; and in step 256, forming a first conductive layer over the conductive layer connected to the conductive layer through the first via.

[0115] The method continues, and in step 258, a core voltage distribution network is formed connecting to a plurality of memory cells, wherein forming the core voltage distribution network includes: in step 260, forming a second via above a first conductive layer; in step 262, forming a second conductive layer island above the first conductive layer that is connected to the first conductive layer through the second via; in step 264, forming a third via above the second conductive layer island; and in step 266, forming a third conductive layer above the second conductive layer that is connected to the second conductive layer island through the third via.

[0116] In some embodiments, forming each memory cell includes forming a core voltage distribution network in each memory cell, including: forming a second via above a first conductive layer; forming a second conductive layer island above the first conductive layer and connected to the first conductive layer through the second via; forming a third via above the second conductive layer island; and forming a third conductive layer above the second conductive layer and connected to the second conductive layer island through the third via.

[0117] In some embodiments, forming a plurality of memory cells in a memory array includes forming a plurality of memory cells in multiple rows and multiple columns; and forming memory cells in each column, wherein each memory cell includes a second conductive layer island connected to a first conductive layer via a second conductive layer island, and the memory cells appear once every 2×N rows, where N is a positive integer.

[0118] In some embodiments, forming a second conductive layer island includes forming a footprint of the second conductive layer island in the memory cell, the footprint of the second conductive layer island being located between the footprint of the first conductive layer bit line (BL) in the memory cell and the footprint of the complementary bit line (BLB) in the first conductive memory cell.

[0119] In some embodiments, forming a second conductive layer island includes forming a footprint of the second conductive layer island in the memory cell, the footprint of the second conductive layer island being located between the footprint of the first VSS line in the memory cell and the footprint of the second VSS line in the memory cell.

[0120] Figure 9 Exemplary block diagrams are illustrated of a computer system 300 configured to provide the currently disclosed apparatus (including electronic devices and semiconductor devices) and methods according to some embodiments. Part or all of the design, layout, and fabrication of the semiconductor device (also referred to as a semiconductor circuit) may be performed by or by means of the computer system 300. Furthermore, part or all of the design, layout, and fabrication of the apparatus (including electronic devices) may be performed by or by means of the computer system 300. In some embodiments, the computer system 300 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor device is an IC.

[0121] In some embodiments, system 300 is a general-purpose computing device including processor 302 and nontransitory computer-readable storage medium 304. The computer-readable storage medium 304 may encode (e.g., store) computer program code, such as executable instructions 306. Processor 302 executes instructions 306 to provide (at least partially) design tools to implement some or all of the functions of system 300, such as pre-placement simulation, post-placement simulation, routing, rerouting, and final fabrication placement. Furthermore, system 300 includes fabrication tools 308 for further placement and physical implementation of the design and fabrication of semiconductor devices. In some embodiments, processor 302 executes instructions 306 to provide (at least partially) design tools to implement some or all of the functions of system 300. In some embodiments, system 300 includes a commercial router. In some embodiments, system 300 includes an automatic place and route (APR) system.

[0122] Processor 302 is electrically coupled to computer-readable storage medium 304 via bus 310 and to I / O interface 312 via bus 310. Network interface 314 is also electrically connected to processor 302 via bus 310. Network interface 314 is connected to network 316, allowing processor 302 and computer-readable storage medium 304 to be connected to external components via network 316. Processor 302 is configured to execute computer program code or instructions 306 encoded in computer-readable storage medium 304 to cause system 300 to perform some or all of its functions, such as providing other functions of the currently disclosed semiconductor apparatus and methods and system 300. In some embodiments, processor 302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0123] In some embodiments, the computer-readable storage medium 304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, device, or apparatus. The computer-readable storage medium 304 may include semiconductor or solid-state memory, magnetic tape, removable disk, random-access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 304 may include compact disk read-only memory (CD-ROM), compact disk read / write memory (CD-R / W), and / or digital video disc (DVD).

[0124] In some embodiments, a computer may read computer program code or instructions 306 stored on storage medium 304 and configure system 300 to perform some or all of its functions. In some embodiments, a computer may read information stored on storage medium 304 that helps to perform some or all of the functions of system 300. In some embodiments, a computer may read database 318 stored on storage medium 304, database 318 including one or more of a component library, a digital circuit unit library, and other databases.

[0125] System 300 includes an I / O interface 312 coupled to external circuitry. In some embodiments, the I / O interface 312 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touchscreen, and / or a cursor direction key configured to communicate messages and commands to processor 302.

[0126] Network interface 314 is coupled to processor 302 and allows system 300 to communicate with network 316, which is connected to one or more other computer systems. Network interface 314 may include: a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In some embodiments, some or all of the functions of system 300 may be performed in two or more systems similar to system 300.

[0127] System 300 is configured to receive information via I / O interface 312. The information received via I / O interface 312 includes one or more of the following: instructions, data, design rules, component and cell libraries, and / or other parameters processed by processor 302. The information is transmitted to processor 302 via bus 310. Furthermore, system 300 is configured to receive information related to the user interface (UI) via I / O interface 312. UI information may be used as UI 320 and stored in computer-readable storage media 304.

[0128] In some embodiments, some or all of the functions of system 300 are implemented by a standalone software application executed by a processor. In some embodiments, some or all of the functions of system 300 are implemented as part of a software application that is an additional software application. In some embodiments, some or all of the functions of system 300 are implemented as a plug-in of a software application. In some embodiments, at least one function of system 300 is implemented as part of a software application that is an EDA tool. In some embodiments, some or all of the functions of system 300 are implemented as part of a software application used by system 300. In some embodiments, a tool is used to generate layout diagrams, such as VIRTUOSO provided by CADENCE DESIGN SYSTEMS, Inc., or other suitable layout generation tools.

[0129] In some embodiments, routing, layout, and other processing are implemented using the functionality of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs (e.g., digital video discs or digital multifunction discs (DVDs)), magnetic disks (e.g., hard disks), semiconductor memory (e.g., ROM, RAM), and memory cards.

[0130] As described above, embodiments of system 300 include manufacturing tools 308 configured to implement the manufacturing process of system 300. For example, based on the final layout, a lithography mask can be generated that can be used by manufacturing tools 308 to manufacture semiconductor devices.

[0131] Further integration Figure 10 The disclosed embodiments of device manufacturing, Figure 10 This is a block diagram of a semiconductor device manufacturing system 322 and its associated semiconductor device manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 322 is used to manufacture one or more semiconductor masks and / or at least one component in a semiconductor device layer.

[0132] exist Figure 10In this system, semiconductor device manufacturing system 322 includes companies (e.g., design firm 324, mask room 326, and semiconductor device manufacturing plant / fabrication plant (“Fab”) 328) that communicate with each other throughout the design, development, and manufacturing cycles, and / or services related to the manufacture of semiconductor devices (e.g., the semiconductor devices described herein). The companies in system 322 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each company interacts with one or more other companies and provides services to and / or receives services from one or more other companies. In some embodiments, two or more of design firm 324, mask room 326, and semiconductor device manufacturing plant 328 are owned by a larger company. In some embodiments, two or more of design firm 324, mask room 326, and semiconductor device manufacturing plant 328 coexist in a shared facility and use shared resources.

[0133] Design company (or design team) 324 generates a semiconductor device design layout 330. The semiconductor device design layout 330 includes various geometric patterns, or a semiconductor device layout designed for a semiconductor device. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the semiconductor structure to be manufactured. The layers combine to form various semiconductor device characteristics. For example, a portion of the semiconductor device design layout 330 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or areas, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and pad openings. Design company 324 implements a design process to generate the semiconductor device design layout 330. The semiconductor device design layout 330 is presented in one or more data files containing geometric pattern information. In some embodiments, the design process includes one or more of the following: analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design (including power via design), power voltage rail design, reference voltage rail design, place and route procedure, and physical place and route design.

[0134] Masking chamber 326 includes data preparation 332 and mask fabrication 334. Masking chamber 326 uses a semiconductor device design layout 330 to fabricate one or more masks 336 for configuration on various layers of a semiconductor device or semiconductor structure. Masking chamber 326 performs mask data preparation 332, in which the semiconductor device design layout 330 is converted into a representative data file (RDF). Mask data preparation 332 provides the RDF to mask fabrication 334. Mask fabrication 334 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (photomask) 336 or a semiconductor wafer 338. The design layout 330 is controlled by mask data preparation 332 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device manufacturer 328. Figure 10 In this design, mask data preparation 332 and mask manufacturing 334 are shown as separate elements. In some embodiments, mask data preparation 332 and mask manufacturing 334 may be collectively referred to as mask data preparation.

[0135] In some embodiments, mask data preparation 332 includes optical proximity correction (OPC) and uses lithography enhancement techniques to compensate for image errors, which may be caused by diffraction, interference, and other process effects. OPC adjusts the semiconductor device design layout diagram 330. In some embodiments, mask data preparation 332 includes further resolution enhancement techniques (RET), such as off-axis emission, sub-resolution auxiliary patterning, phase-shift masking, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, and OPC is treated as an inverse imaging problem.

[0136] In some embodiments, mask data preparation 332 includes a mask rule checker (MRC) that examines a semiconductor device design layout 330, which has been processed in OPC using a set of mask creation rules that include specific geometric and / or connectivity constraints to ensure sufficient margins to accommodate variations during semiconductor manufacturing. In some embodiments, the MRC modifies the semiconductor device design layout 330 to compensate for constraints during mask manufacturing 334, thereby undoing some modifications performed by the OPC to satisfy the mask creation rules.

[0137] In some embodiments, mask data preparation 332 includes lithography process checking (LPC) and simulating the processes to be performed by the semiconductor device manufacturing plant 328. Process parameters in the LPC simulation may include parameters related to various processes in the semiconductor device manufacturing cycle, parameters related to the tools configured in the semiconductor device manufacturing process, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, or combinations thereof. In some embodiments, after establishing a simulated manufacturing apparatus using LPC, if the shape of the simulated apparatus is not close enough to meet design rules, OPC and / or MRC need to be repeated to further refine the semiconductor device design layout 330.

[0138] For clarity, the foregoing description of mask data preparation 332 has been simplified. In some embodiments, data preparation 332 includes additional functions, such as logic operations (LOPs), to modify the semiconductor device design layout 330 according to manufacturing rules. Furthermore, the processes applied to the semiconductor device design layout 330 during data preparation 332 can be performed in a variety of different sequences.

[0139] After mask data preparation 332 and during mask manufacturing 334, a mask 336 or a set of masks 336 is manufactured based on a modified semiconductor device design layout 330. In some embodiments, mask manufacturing 334 includes performing one or more lithography exposures based on the semiconductor device design layout 330. In some embodiments, a pattern is formed on the mask (photomask or photomask) 336 using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified semiconductor device design layout 330. The mask 336 can be formed using a variety of techniques. In some embodiments, the mask 336 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (e.g., ultraviolet (UV) beams) configured to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and pass through the transparent areas. In one example, the binary mask version of mask 336 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 336 is formed using a phase-shifting technique. In the phase-shift mask (PSM) version of mask 336, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 334 can be configured in a variety of processes. For example, such a mask can be configured in an ion implantation process to form various doped regions in a semiconductor wafer 338, configured in an etching process to form various etched regions in a semiconductor wafer 338, and / or configured in other suitable processes.

[0140] Semiconductor device manufacturing plant 328 includes wafer fabrication 340. Semiconductor device manufacturing plant 328 is a semiconductor device manufacturing enterprise and includes one or more manufacturing facilities configured to manufacture various different semiconductor device products. In some embodiments, semiconductor device manufacturing plant 328 is a semiconductor foundry. For example, one manufacturing facility may be configured for front-end of line (FEOL) processes to manufacture multiple semiconductor device products, while a second manufacturing facility may provide BEOL (interconnection and packaging) manufacturing for the semiconductor device products, and a third manufacturing plant may provide other services to the foundry.

[0141] Semiconductor device fabrication plant 328 uses a mask 336, manufactured by mask chamber 326, to fabricate the semiconductor structure or semiconductor device 342 disclosed herein. Therefore, semiconductor device fabrication plant 328 uses semiconductor device design layout 330 at least indirectly to fabricate the semiconductor structure or semiconductor device 342 disclosed herein. Furthermore, semiconductor wafer 338 includes a silicon substrate or other suitable substrate on which a material layer is formed, and semiconductor wafer 338 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps). In some embodiments, semiconductor wafer 338 is fabricated by semiconductor device fabrication plant 328 using mask 336 to form the semiconductor structure or semiconductor device 342 disclosed herein. In some embodiments, semiconductor device fabrication includes performing one or more lithography exposures at least indirectly based on semiconductor device design layout 330.

[0142] Therefore, embodiments of this disclosure provide a memory device including a power grid using a second conductive layer island (e.g., in layer M1) connected via vias to a first conductive layer (e.g., layer M0), which is connected to memory cells within the memory device. A third conductive layer (e.g., layer M2) is connected to the second conductive layer island via another via to form the power grid, thereby increasing the maximum voltage Vmax of the memory cells and improving the RSNM of the memory cells.

[0143] In some embodiments, the memory device includes a memory array comprising memory cells located in multiple rows and multiple columns. Each column of memory cells includes a power grid memory cell comprising a second conductive layer island connected to a first conductive layer via a via, and a third conductive layer connected to the second conductive layer island via another via. In some embodiments, each column of the memory array includes one power grid memory cell, occurring once every 2×N rows, where N is a positive integer. In some embodiments, the memory array includes multiple word lines located in a second conductive layer, such that increasing N reduces word line resistance and capacitance and increases core voltage distribution network resistance.

[0144] The disclosed embodiments also include a memory device comprising a memory array and a core voltage distribution network. The memory array includes memory cells located in multiple rows and columns, wherein each memory cell includes a conductive layer above an active region and a first conductive layer connected to the conductive layer. The core voltage distribution network includes a second conductive layer comprising at least one core voltage distribution line located between the multiple rows of memory cells in the memory array and connected to the first conductive layer. The core voltage distribution network increases the maximum voltage Vmax of the memory cells and improves the RSNM of the memory cells.

[0145] The embodiments disclosed herein also include a method of manufacturing a memory device. The method includes forming a plurality of memory cells in a memory array and forming a core voltage distribution network connected to the plurality of memory cells. Forming each memory cell includes forming a conductive layer over an active region, forming a first via over the conductive layer, and forming a first conductive layer connected to the conductive layer through the first via in the conductive layer. Forming the core voltage distribution network includes forming a second via over the first conductive layer, forming a second conductive layer island connected to the first conductive layer through the second via over the first conductive layer, forming a third via over the second conductive layer island, and forming a third conductive layer connected to the second conductive layer island through the third via over the second conductive layer.

[0146] According to some embodiments, a memory device includes a memory array having a plurality of memory cells and a core voltage distribution network connected to the plurality of memory cells. Each memory cell includes a conductive layer located above an active region and a first conductive layer connected to the conductive layer located above the active region through a first via. The core voltage distribution network includes a second conductive layer and a third conductive layer, the second conductive layer including a second conductive layer island connected to the first conductive layer through a second via, and the third conductive layer connected to the second conductive layer island through a third via. In some embodiments, each memory cell includes a second conductive layer island and a third conductive layer; the second conductive layer island is connected to the first conductive layer through a second via, and the third conductive layer is connected to the second conductive layer island through a third via. In some embodiments, the memory array includes memory cells located in a plurality of rows and a plurality of columns, and each column includes one of the memory cells, the memory cell including a second conductive layer island connected to the first conductive layer through a second via and a third conductive layer connected to the second conductive layer island through a third via, appearing once every 2×N rows, where N is a positive integer. In some embodiments, the memory array includes a plurality of word lines located in a second conductive layer, such that increasing N reduces word line resistance and capacitance and increases core voltage distribution network resistance. In some embodiments, the memory array includes a plurality of word lines located in a second conductive layer, such that changing N optimizes the relationship between word line resistance and capacitance and core voltage distribution network resistance. In some embodiments, the memory array includes memory cells located in a plurality of rows and a plurality of columns, and each column includes a memory cell appearing once every four rows, the memory cell including a second conductive layer island connected to a first conductive layer through a second via and a third conductive layer connected to the second conductive layer island through a third via. In some embodiments, the footprint of the second conductive layer island in one of the memory cells is located between the footprint of the first conductive layer bit line in that memory cell and the footprint of the complementary bit line of the first conductive layer in that memory cell. In some embodiments, the footprint of the second conductive layer island in one of the memory cells is located between the footprint of the first VSS line in that memory cell and the footprint of the second VSS line in that memory cell. In some embodiments, each memory cell is a static random access memory (SRAM) cell. In some embodiments, each memory cell is a six-transistor SRAM cell.

[0147] According to a further embodiment, the memory device includes a memory array having a plurality of memory cells located in a plurality of rows and columns. Each memory cell includes a conductive layer located above an active region and a first conductive layer connected to the conductive layer through a first via. Each column of the memory array includes one of the memory cells, the memory cell including a second conductive layer island connected to the first conductive layer through a second via and a third conductive layer connected to the second conductive layer island through a third via. In some embodiments, each column includes one of the memory cells and appears once every 2×N rows, where N is a positive integer. In some embodiments, the memory array includes a plurality of word lines located in the second conductive layer, such that increasing N reduces word line resistance and capacitance and increases core voltage distribution network resistance. In some embodiments, N is 2. In some embodiments, the footprint of the second conductive layer island in one of the memory cells is located between the footprint of the first conductive layer bit line in that memory cell and the footprint of the complementary bit of the first conductive layer in that memory cell. In some embodiments, the area occupied by the second conductive layer island in one of the memory cells is located between the area occupied by the first VSS line in that memory cell and the area occupied by the second VSS line in that memory cell.

[0148] According to a further embodiment of this disclosure, a memory device includes a memory array having a plurality of memory cells located in a plurality of rows and a plurality of memory cells located in a plurality of columns, and a core voltage distribution network. Each memory cell includes a conductive layer located above an active region and a first conductive layer connected to the conductive layer through a first via, wherein the first conductive layer is configured to receive a core voltage. The core voltage distribution network includes a second conductive layer, the second conductive layer including at least one core voltage distribution line located between the rows of memory cells in the memory array and connected to the first conductive layer through at least one second via.

[0149] Further according to embodiments of the present disclosure, a method of manufacturing a memory device includes forming a plurality of memory cells in a memory array and forming a core voltage distribution network connected to the plurality of memory cells. Forming each memory cell includes forming a conductive layer over an active region; forming a first via over the conductive layer; and forming a first conductive layer over the conductive layer connected to the conductive layer through the first via. Further, forming the core voltage distribution network includes forming a second via over the first conductive layer; forming a second conductive layer island over the first conductive layer connected to the first conductive layer through the second via; forming a third via over the second conductive layer island; and forming a third conductive layer over the second conductive layer connected to the second conductive layer island through the third via. In some embodiments, forming each memory cell includes forming a core voltage distribution network in each memory cell, including: forming a second via over the first conductive layer; forming a second conductive layer island over the first conductive layer and connecting the second conductive layer island to the first conductive layer through the second via; forming a third via over the second conductive layer; and forming a third conductive layer over the second conductive layer and connecting the third conductive layer to the second conductive layer island through the third via. In some embodiments, forming memory cells in a memory array includes memory cells located in multiple rows and multiple columns, and one of forming memory cells in each column. The memory cell includes a second conductive layer island connected to a first conductive layer via a second via and a third conductive layer connected to the second conductive layer island via a third via, occurring once every 2×N rows, where N is a positive integer. In some embodiments, forming a second conductive layer island includes forming a region in a first memory cell between a region occupied by a first conductive layer bit line in one of the memory cells and a region occupied by a complementary bit line of the first conductive layer in the other of the memory cells; or forming a region in a second memory cell between a region occupied by a first VSS line in one of the memory cells and a region occupied by a second VSS line in the other of the memory cells.

[0150] This disclosure provides a memory device. The memory device includes a memory array and a core voltage distribution network. The memory array includes a plurality of memory cells, wherein each memory cell includes a conductive layer, a first via, and a first conductive layer. The conductive layer is located above an active region. The first via is located above the conductive layer. The first conductive layer is connected to the conductive layer through the first via. The core voltage distribution network is connected to the memory cells, wherein the core voltage distribution network includes a second via, a second conductive layer, and a dielectric layer. The second via is located above the first conductive layer. The second conductive layer is located above the first conductive layer and includes a second conductive layer island connected to the first conductive layer through the second via. The dielectric layer is located on the second conductive layer island. In some embodiments, the core voltage distribution network further includes a third via and a third conductive layer. The third via is located above the second conductive layer island. The third conductive layer is located above the second conductive layer and connected to the second conductive layer island through the third via. The occupancy region of the second conductive layer island in one of the memory cells is located between the occupancy region of the first conductive layer bit line in that memory cell and the occupancy region of the complementary bit of the first conductive layer in that memory cell.

[0151] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can simply use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, include: A memory array having multiple memory cells, wherein each memory cell includes: A conductive layer is located above an active region; and A first conductive layer is connected to the conductive layer located above the active region through a first via; and A core voltage distribution network is connected to the plurality of memory cells, wherein the core voltage distribution network includes: A second conductive layer, including a second conductive layer island connected to the first conductive layer through a second via; and A third conductive layer is connected to the second conductive layer island through a third through-hole.

2. The memory device as claimed in claim 1, characterized in that, Each memory unit includes: The second conductive layer island is connected to the first conductive layer through the second through-hole; and The third conductive layer is connected to the second conductive layer island through the third through-hole.

3. The memory device as claimed in claim 1, characterized in that, The memory array includes a plurality of memory cells located in a plurality of rows and a plurality of columns, and each column includes one of the plurality of memory cells appearing once every four rows. The plurality of memory cells includes a second conductive layer island connected to the first conductive layer through the second via and a third conductive layer connected to the second conductive layer island through the third via.

4. The memory device as claimed in claim 1, characterized in that, A occupies a region of the second conductive layer island in one of the plurality of memory cells, located between a occupies a region of a first conductive layer bit line in one of the plurality of memory cells and a occupies a region of a first conductive layer complementary bit line in one of the plurality of memory cells.

5. The memory device as claimed in claim 1, characterized in that, A portion of the second conductive layer island in one of the plurality of memory cells is located between a portion of a first VSS line in one of the plurality of memory cells and a portion of a second VSS line in one of the plurality of memory cells.

6. A memory device, characterized in that, include: A memory array having multiple memory cells located in multiple rows and multiple columns, each memory cell comprising: A conductive layer is located above an active region; as well as A first conductive layer is connected to the conductive layer through a first through-hole. Each column of the memory array includes one of the plurality of memory cells, and the plurality of memory cells includes a second conductive layer island connected to the first conductive layer through a second via and a third conductive layer connected to the second conductive layer island through a third via.

7. The memory device as claimed in claim 6, characterized in that, Each column includes one of the plurality of memory units and appears once every 2×N rows, where N is a positive integer.

8. The memory device as claimed in claim 7, characterized in that, The memory array includes multiple word lines located in a second conductive layer, such that increasing N reduces word line resistance and capacitance and increases core voltage distribution network resistance.

9. A memory device, characterized in that, include: A memory array comprising a plurality of memory cells, wherein each memory cell includes: A conductive layer is located above an active region; A first via is located above the conductive layer; and A first conductive layer, connected to the conductive layer through the first via; and A core voltage distribution network is connected to the plurality of memory cells, wherein the core voltage distribution network includes: A second through-hole is located above the first conductive layer; A second conductive layer, located above the first conductive layer, and including a second conductive layer island connected to the first conductive layer through the second via; and A dielectric layer is located on the island of the second conductive layer.

10. The memory device as claimed in claim 9, characterized in that, The core voltage distribution network also includes: A third via is located above the second conductive layer island; and A third conductive layer is located above the second conductive layer and is connected to the second conductive layer island through the third through-hole. In one of the plurality of memory cells, a occupies a region of the second conductive layer island, which is located between a occupies a region of a first conductive layer bit line in the plurality of memory cells and a occupies a region of a complementary bit of the first conductive layer in the plurality of memory cells.

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