A debug board that can debug NAND Flash from different manufacturers
Patent Information
- Application Number
- CN202522389434.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-10-09
- Estimated Expiration
- 2035-11-11
AI Technical Summary
每一种NAND都要进行打板验证，导致控制器、SDRAM等大量使用，增加研发的成本
[0012]本实用新型的有益效果：本实用新型将控制器、SDRAM、电源芯片等核心且昂贵的部件全部集成在主板上，使其成为一个可重复使用的通用硬件平台，将被测NAND Flash设置于副板上，在调试不同厂商的NAND Flash时，仅需制作和更换集成了特定NAND Flash颗粒的、结构相对简单的副板即可。这极大地减少了对控制器、SDRAM等核心器件的重复采购和贴装，从硬件层面直接降低了研发的物料成本。主板可以重复使用，研发过程中无需为每一种NAND Flash都进行完整SSD的打板、焊接和测试。副板的设计相对简单，打板周期更短，调试团队可以快速获得多款不同厂商NAND Flash的调试样板，实现并行调试。这使得从硬件准备到固件适配的整个开发流程得以大幅提速，有效缩短了产品的上市时间。副板设计具备高度的灵活性。副板上最多可以放置16颗NAND Flash颗粒，并且可以选择贴满16颗NAND Flash颗粒，或者只贴其中几颗，来配置NAND副板的总容量。在副板上为每颗NANDFlash颗粒配备了MUX芯片（信号驱动/中继芯片），用于增强控制器和NAND Flash颗粒间的信号质量，有效补偿了信号在传输过程中的损耗，确保了高速数据传输的稳定性和可靠性，为准确调试提供了硬件保障。设计了分布式的温度监控系统。主板上布置温度传感器监控控制器和SDRAM的温度。NAND Flash副板上还放置有一颗温度传感器U1，通过I2C接口经高速连接器接到主板的控制器上，实现对NAND Flash工作温度的实时监测。当温度超过阈值时，系统能自动触发温控策略（如降速、停止业务），有效保护了NAND Flash颗粒和整个SSD的安全，延长了器件寿命，提高了产品的可靠性。
Smart Images
Figure CN224841279U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip testing, specifically a debugging board that can debug NAND Flash from different manufacturers. Background Technology
[0002] Due to the limitations of NAND flash production capacity, performance, and price, SSDs need to be as compatible as possible with NAND flash from different manufacturers without changing other hardware. This necessitates adaptation for multiple manufacturers' NAND flash during the development phase. Each type of NAND flash requires PCB fabrication and verification, leading to the extensive use of controllers, SDRAM, and other components, increasing R&D costs. A method is needed where only the NAND flash needs to be replaced, while other components can be reused. This would reduce R&D costs and save time. Utility Model Content
[0003] To address the shortcomings of existing technologies, this invention provides a debugging board capable of debugging NAND Flash from different manufacturers. The NAND Flash under test is separated from other components, with the NAND Flash under test placed on a secondary board and the controller, SDRAM, and other components placed on the main board. The main board and the secondary board are connected by a connector. During the SSD development phase, when it is necessary to adapt to NAND Flash from different manufacturers, the debugging and development of NAND Flash from different manufacturers can be achieved by replacing the NAND Flash secondary board. This allows for reuse of the main board and rapid switching between different manufacturers' NAND Flash.
[0004] To solve the aforementioned technical problem, the present invention adopts the following technical solution: a debugging board capable of debugging NAND Flash from different manufacturers, comprising a main board and a sub-board. The main board is equipped with a controller and connector I, while the sub-board is equipped with the NAND Flash under test and connector II. Connector I is connected to the controller, and connector II is connected to the NAND Flash under test. Connector I and connector II are plugged together to realize data communication between the controller and the NAND Flash under test. The controller has 8 or 16 channels. When the number of channels is 8, the controller connects to the NAND Flash under test through one connector I and one connector II. When the number of channels is 16, the controller connects to the NAND Flash under test through two connectors I and two connectors II. Each channel has 8 CEs, and each CE is connected to the NAND Flash under test through connectors I and II.
[0005] Furthermore, each NAND Flash chip has two sets of independent I / O interfaces, which can be connected to the same channel or two different channels.
[0006] Furthermore, when the number of channels is 8, the sub-board adopts a 2-channel-2-NAND flash topology. One channel connects to a set of IO interfaces of the NAND Flash U1 and U2 under test, and the other channel connects to another set of IO interfaces of the NAND Flash U1 and U2 under test. U1 and U2 are mounted face-to-face, on the TOP and Bottom layers of the PCB, respectively.
[0007] Furthermore, when the number of channels is 16, the sub-board adopts a 2-channel-4-NAND flash topology. One channel connects to a set of IO interfaces of the NAND Flash U1, U2, U3, and U4 under test, and the other channel connects to another set of IO interfaces of the NAND Flash U1, U2, U3, and U4 under test. U1 and U3, and U2 and U4 are respectively mounted in a face-to-face manner, on the TOP and Bottom layers of the PCB.
[0008] Furthermore, the motherboard is equipped with temperature sensors U2 and U3 for monitoring the temperature of the SDRAM and the controller; the sub-board is equipped with temperature sensor U1 for monitoring the operating temperature of the NAND Flash under test. Temperature sensor U1 is connected to the controller via I2C interface, connector I, and connector II in sequence.
[0009] Furthermore, a multiplexer is also provided on the sub-board, and connector II is connected to the NAND Flash under test through the multiplexer.
[0010] Furthermore, two pins are selected from connector I and connector II as capacity adjustment pins. The capacity adjustment pin of connector I is connected to the GPIO pin of the controller, and the capacity adjustment pin of connector II is connected to the pull-up resistor and the pull-down resistor.
[0011] Furthermore, both the motherboard and the sub-board are 7mm thick.
[0012] The beneficial effects of this invention are as follows: This invention integrates all core and expensive components such as the controller, SDRAM, and power supply chip onto the motherboard, making it a reusable and universal hardware platform. The NAND Flash under test is placed on the secondary board. When debugging NAND Flash from different manufacturers, only a relatively simple secondary board integrating specific NAND Flash chips needs to be made and replaced. This greatly reduces the repeated procurement and mounting of core components such as the controller and SDRAM, directly reducing the material costs of R&D from the hardware level. The motherboard can be reused, eliminating the need for complete SSD board making, soldering, and testing for every type of NAND Flash during the R&D process. The secondary board design is relatively simple, with a shorter board making cycle. The debugging team can quickly obtain debugging samples of multiple NAND Flash from different manufacturers, enabling parallel debugging. This significantly accelerates the entire development process from hardware preparation to firmware adaptation, effectively shortening the product launch time. The secondary board design offers high flexibility. Up to 16 NAND Flash chips can be placed on the secondary board, and it can be configured with either all 16 NAND Flash chips or only a few chips, to adjust the total capacity of the NAND secondary board. Each NAND Flash chip on the secondary board is equipped with a MUX chip (signal driver / relay chip) to enhance the signal quality between the controller and the NAND Flash chip, effectively compensating for signal loss during transmission, ensuring the stability and reliability of high-speed data transmission, and providing hardware support for accurate debugging. A distributed temperature monitoring system was designed. Temperature sensors are placed on the main board to monitor the temperature of the controller and SDRAM. A temperature sensor U1 is also placed on the NAND Flash secondary board, which is connected to the main board controller via an I2C interface and a high-speed connector to realize real-time monitoring of the NAND Flash operating temperature. When the temperature exceeds the threshold, the system can automatically trigger temperature control strategies (such as speed reduction, service interruption), effectively protecting the NAND Flash chip and the entire SSD, extending device life, and improving product reliability. Attached Figure Description
[0013] Figure 1 This is a schematic diagram of the component distribution on the top surface of the motherboard in Example 1; Figure 2 This is a schematic diagram of the component distribution on the bottom side of the motherboard in Example 1; Figure 3 This is a schematic diagram of the device distribution on the TOP surface of the sub-board in Example 1; Figure 4 This is a schematic diagram of the device distribution on the bottom surface of the sub-board in Example 1; Figure 5This is a schematic diagram of the channel distribution between the motherboard and connector I in Example 1; Figure 6 This is a schematic diagram of the NAND Flash connection topology in Example 1; Figure 7 This is a schematic diagram of the NAND Channel distribution on the secondary board in Example 1; Figure 8 This is a schematic diagram of the channel distribution between the motherboard and connector I in Example 2; Figure 9 This is a schematic diagram of the NAND Flash connection topology in Example 2; Figure 10 This is a schematic diagram of the NAND Channel distribution on the sub-board in Example 2. Detailed Implementation
[0014] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.
[0015] Example 1 This embodiment discloses a debugging board capable of debugging NAND Flash from different manufacturers, including a main board and a secondary board, such as... Figure 1 , 2 As shown, the motherboard contains a controller, SRAM, and connector I, as follows. Figure 3 , 4 As shown, the sub-board has connector II and the NAND Flash under test. Connector I is connected to the controller, and connector II is connected to the NAND Flash under test. Connectors I and II are plugged together to achieve data communication between the controller and the NAND Flash under test. In this embodiment, the controller has 16 channels. The main board has two connectors I, and the sub-board has two connectors II. The controller connects to the NAND Flash under test through two connectors I and two connectors II. Specifically, the controller's 16 channels are Channels 0 to 15. Each channel is independent and does not affect each other. These 16 channels are divided into two parts: Channels 0 to 7 are the first part, and Channels 8 to 15 are the second part. Figure 5As shown, Channels 0-7 communicate with the NAND Flash on the secondary board through one set of connectors (connector I and connector II), while Channels 8-15 communicate with the NAND Flash on the secondary board through another set of connectors (another set of connectors I and connector II). Each Channel of the controller has 8 CEs, all connected to the NAND Flash on the secondary board via high-speed connectors, used to select different targets for the NAND Flash chips. Within each Channel, different targets of the NAND Flash chips share the same signals IO0-7, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, and RE_N. The different targets of the NAND Flash chips are selected through the CE0-7 signals within the Channel.
[0016] Each NAND Flash chip has two sets of I / O interfaces, which are independent of each other. They can be connected to the same channel or to two different channels. This embodiment uses a topology where the two sets of I / O for one NAND Flash chip are connected to different channels, i.e., a 2-channel-2-NAND chip topology. Figure 6 As shown, the topology of the 2-Channel-2 NAND flash chips is as follows: Channel N is connected to one set of I / O for each of NAND Flash chips U1 and U2, and Channel N+1 is connected to another set of I / O for U1 and U2. U1 and U2 are mounted face-to-face, on the TOP and Bottom layers of the PCB, respectively. Figure 7 This diagram illustrates the channel logic distribution between connector II and NAND Flash chips on the secondary board (only the top side is shown). The secondary board contains 16 NAND Flash chips, with channels CH0-15 connected to them via two connector IIs. Each high-speed connector corresponds to 8 channels, connecting to 8 NAND Flash chips. Channels 0-7 are connected to the same connector II, connecting to the 4 NAND Flash chips on the top side and the 4 NAND Flash chips on the bottom side, respectively. Channels 8-15 are connected to another connector II, connecting to the 4 NAND Flash chips on the top side and the 4 NAND Flash chips on the bottom side, respectively, thus implementing the 2-channel-2-NAND-chip topology.
[0017] To ensure the normal operation of NAND Flash debugging, a power chip is also provided on the motherboard. In addition to powering the devices on the motherboard, the power chip also powers the devices on the NAND Flash sub-board through connector I and connector II.
[0018] The motherboard also has two temperature sensors, U2 and U3, which monitor the temperature of the SDRAM and the controller, respectively. The SDRAM and the controller have their own normal operating range. When the temperature approaches or exceeds the device temperature threshold, the SSD will take corresponding temperature control measures to slow down the debugging process. If the temperature continues to rise, the debugging process will stop.
[0019] The secondary board also features a multiplexer (MUX). The signals from the NAND Flash chips are connected to connector II via the MUX, and then communicate with the motherboard controller via connectors II and I. Because the traces between the secondary board's NAND Flash chips and the motherboard controller are too long and pass through connectors, resulting in significant signal attenuation, a multiplexer (MUX) chip was added to enhance the signal quality between the controller and the NAND Flash chips.
[0020] The secondary board can accommodate up to 16 NAND Flash chips, each using one MUX chip. The secondary board can be configured with either all 16 chips or only a few, allowing for different capacity settings such as 2T / 4T / 8T / 16T. To facilitate capacity adjustment, two pins from connectors I and II are selected as capacity adjustment pins. The capacity adjustment pin of connector I connects to the controller's GPIO pins, while the capacity adjustment pin of connector II connects to pull-up and pull-down resistors, enabling four combinations: 00, 01, 10, and 11, each corresponding to a different capacity setting on the secondary board. 00 represents a 2T capacity, while 01, 10, and 11 correspond to 4T, 8T, and 16T capacities, respectively. Upon power-on, the controller identifies different values (00-11) on the two GPIO pins and switches the corresponding firmware to match the different capacity settings of the NAND Flash secondary board.
[0021] A temperature sensor U1 is also placed on the NAND Flash secondary board, which is connected to the main board controller via I2C interface (U.2 connector), connector I, and connector II. The controller can monitor the operating temperature of the NAND Flash chips on the secondary board in real time. When the NAND Flash operating temperature exceeds the threshold of the SSD, a temperature control strategy is implemented to slow down the debugging process. If the temperature continues to rise, the debugging process will be stopped.
[0022] Considering the size limitations of the slots on the server, and the fact that the maximum thickness of a typical 2.5-inch SSD is 15mm, the motherboard of this SSD is designed to be 7mm thick, and the secondary board is designed to be 7mm thick. This way, when the secondary board is attached to the motherboard, the overall thickness of the expanded SSD will not exceed 15mm.
[0023] Example 2 This embodiment discloses a debug board capable of debugging NAND Flash from different manufacturers, including a main board and a secondary board. The main board has a controller, SRAM, and connector I, while the secondary board has connector II and the NAND Flash under test. Connector I is connected to the controller, and connector II is connected to the NAND Flash under test. Connectors I and II are plugged together to achieve data communication between the controller and the NAND Flash under test. In this embodiment, the controller has 8 channels. The main board has one connector I, and the secondary board has one connector II. The controller connects to the NAND Flash under test through one connector I and one connector II. Specifically, the controller's 8 channels are Channels 0 to 7, as shown below. Figure 8 As shown, Channels 0-7 communicate with the NAND Flash on the secondary board via a set of connectors (one connector I and one connector II). Each Channel of the controller has eight CEs, all connected to the NAND Flash on the secondary board via high-speed connectors, used to select different targets for the NAND Flash chips. Within each Channel, different targets of the NAND Flash chips share the same signals IO0-7, WE, CLE, ALE, WP, DQS_P, DQS_N, RE_P, and RE_N. The different targets of the NAND Flash chips are selected through the CE0-7 signals within the Channel.
[0024] In this embodiment, the NAND Flash secondary board adopts a 2-Channel-4 NAND chip topology, such as... Figure 9 As shown: Each NAND Flash chip has two sets of I / O interfaces, which are independent of each other. They can be connected to the same channel or to two different channels. This design uses a topology where the two sets of I / O for a single NAND Flash chip are connected to different channels. For example... Figure 9 In the configuration, Channel N is connected to one set of I / O pins for each of the NAND Flash chips U1, U2, U3, and U4, and Channel N+1 is connected to another set of I / O pins for U1, U2, U3, and U4. U1 and U3, and U2 and U4 are mounted in a face-to-face configuration.
[0025] Figure 10 This is the channel logic distribution between the high-speed connector and the NAND Flash chips on the NAND Flash sub-board (only the top side is shown). There are a total of 16 NAND Flash chips on the sub-board, and CH0~7 are connected to the 16 NAND chips through the high-speed connector.
[0026] This embodiment also includes a power chip, a temperature sensor, and a multiplexer, and the capacity of the sub-board can be adjusted. The specific implementation method is the same as in Embodiment 1, and will not be repeated here.
[0027] The above description is only the basic principle and preferred embodiment of this utility model. Any improvements and substitutions made by those skilled in the art based on this utility model shall fall within the protection scope of this utility model.
Claims
1. A debugging board capable of debugging NAND Flash from different manufacturers, characterized in that: The system includes a main board and a sub-board. The main board has a controller and connector I, while the sub-board has the NAND Flash under test and connector II. Connector I is connected to the controller, and connector II is connected to the NAND Flash under test. Connectors I and II are plugged together to enable data communication between the controller and the NAND Flash under test. The controller has 8 or 16 channels. When there are 8 channels, the controller connects to the NAND Flash under test through one connector I and one connector II. When there are 16 channels, the controller connects to the NAND Flash under test through two connectors I and two connectors II. Each channel has 8 CEs, and each CE is connected to the NAND Flash under test through connectors I and II.
2. The debugging board for debugging NAND Flash from different manufacturers according to claim 1, characterized in that: Each NAND Flash chip has two sets of independent I / O interfaces, which can be connected to the same channel or two different channels.
3. The debugging board for debugging NAND Flash from different manufacturers according to claim 2, characterized in that: When the controller has 8 channels, the sub-board adopts a 2-channel-2-NAND flash topology. One channel connects to a set of IO interfaces of the NAND Flash U1 and U2 under test, and the other channel connects to another set of IO interfaces of the NAND Flash U1 and U2 under test. U1 and U2 are mounted face-to-face, on the TOP and Bottom layers of the PCB, respectively.
4. The debug board for debugging NAND Flash from different manufacturers according to claim 2, characterized in that: When the number of channels of the controller is 16, the sub-board adopts a 2-channel-4-NAND flash topology. One channel is connected to a set of IO interfaces of the NAND Flash U1, U2, U3, and U4 under test, and the other channel is connected to another set of IO interfaces of the NAND Flash U1, U2, U3, and U4 under test. U1 and U3, and U2 and U4 are respectively mounted in a face-to-face manner, on the TOP and Bottom layers of the PCB.
5. The debugging board for debugging NAND Flash from different manufacturers according to claim 1, characterized in that: The motherboard has temperature sensors U2 and U3 for monitoring the temperature of the SDRAM and the controller; the sub-board has a temperature sensor U1 for monitoring the operating temperature of the NAND Flash being tested. Temperature sensor U1 is connected to the controller via an I2C interface, connector I, and connector II in sequence.
6. The debug board for debugging NAND Flash from different manufacturers according to claim 1, characterized in that: The sub-board is also equipped with a multiplexer, and connector II is connected to the NAND Flash under test through the multiplexer.
7. The debug board for debugging NAND Flash from different manufacturers according to claim 1, characterized in that: Select two pins from connector I and connector II as capacity adjustment pins. Connect the capacity adjustment pin of connector I to the GPIO pin of the controller, and connect the capacity adjustment pin of connector II to the pull-up resistor and pull-down resistor.
8. The debug board for debugging NAND Flash from different manufacturers according to claim 1, characterized in that: Both the motherboard and the sub-board are 7mm thick.