Interdigital electrode enhanced multilayer ceramic capacitor

Abstract

This utility model relates to the technical field of capacitors, and particularly to an interdigitated electrode-reinforced multilayer ceramic capacitor, comprising a dielectric layer, a first inner electrode, a second inner electrode, a package shell, and an outer electrode. The first and second inner electrodes are arranged in an interdigitated pattern within the dielectric layer. The package shell surrounds the outer ring of the dielectric layer. Outer electrodes are disposed at both ends of the dielectric layer. A through-ceramic pillar is disposed within the dielectric layer. Heat dissipation channels are formed on the surface of the dielectric layer. A thermoforming element is disposed on the outer surface of the package shell. This interdigitated electrode-reinforced multilayer ceramic capacitor improves the capacitance, high-frequency performance, or response sensitivity of the capacitor by increasing the electrode surface area and the uniformity of the electric field distribution. Through three-dimensional structural design and material optimization, it has advantages such as compact structure, good heat dissipation performance, large capacitance, and long service life.

Description

Technical Field

[0001] This utility model relates to the field of capacitor-related technology, and in particular to an interdigitated electrode-enhanced multilayer ceramic capacitor. Background Technology

[0002] In electronic devices, capacitors are widely used as fundamental components in filtering, coupling, and energy storage. Traditional capacitors, such as multilayer ceramic capacitors, have advantages such as small size and good stability, but their parallel plate electrode structure has problems such as limited effective area and large electrode spacing, which makes it difficult to further increase capacitance. Moreover, in harsh environments such as high frequency, high temperature, and high current, they are prone to defects such as poor heat dissipation, high equivalent series resistance and inductance, and weak pulse resistance. At the same time, when the number of electrode layers is increased, the dielectric layer is prone to delamination and cracking, resulting in low material utilization and limiting the reliability of capacitors in high-performance applications. In addition, other types of capacitors such as electrolytic capacitors and film capacitors also have common problems such as low capacitance density, poor high-frequency characteristics, or insufficient temperature stability. Therefore, there is a need for an interdigitated electrode reinforced multilayer ceramic capacitor.

[0003] Existing capacitors, especially traditional multilayer ceramic capacitors, have an unreasonable internal structure design, insufficient bonding between electrodes and ceramic layers, and large distances between electrodes, resulting in limited capacitance, poor heat dissipation, and easy overheating during long-term operation, which affects stability and lifespan. They also have weak resistance to high-frequency pulses and are easily broken down. The planar electrodes have long current paths, high equivalent series resistance and equivalent series inductance, which limit the filtering effect in high-frequency applications. Furthermore, they have low material utilization and large size. Utility Model Content

[0004] The purpose of this invention is to provide an interdigitated electrode-enhanced multilayer ceramic capacitor to solve the problems of insufficient effective area and poor heat dissipation performance of the parallel plate electrode structure of traditional multilayer ceramic capacitors mentioned in the background art, which leads to limited capacitance and stability.

[0005] To achieve the above objectives, this utility model provides the following technical solution: an interdigitated electrode enhanced multilayer ceramic capacitor, comprising a dielectric layer, a first inner electrode, a second inner electrode, a package shell, and an outer electrode. The first and second inner electrodes are distributed in an interdigitated pattern within the dielectric layer. The outer ring of the dielectric layer is wrapped with the package shell. The two ends of the dielectric layer are provided with outer electrodes. A through ceramic pillar is provided inside the dielectric layer. A heat dissipation channel is formed on the surface of the dielectric layer. A heat fusion element is provided on the outer surface of the package shell.

[0006] Preferably, the first inner electrode and the second inner electrode form an interdigitated inner electrode, and the first inner electrode and the second inner electrode are arranged in an interdigitated staggered manner, with an interdigitated width of 5-10 μm, a spacing of 3-5 μm, and a height of 10-20 μm.

[0007] Preferably, the dielectric layer is made of barium titanate-strontium titanate composite ceramic material, and multiple layers are stacked alternately, and the encapsulation shell is made of ceramic-metal composite substrate material.

[0008] Preferably, the external electrode includes an electroplated copper layer, an electroless nickel plating layer, and an electroplated tin layer, wherein the electroplated copper layer has a thickness of 2-5 μm, the electroless nickel plating layer has a thickness of 1-3 μm, and the electroplated tin layer has a thickness of 3-8 μm.

[0009] Preferably, the ceramic column has a diameter of 0.3 to 0.8 mm and is made of Al2O3 and ZrO2 materials.

[0010] Preferably, the heat dissipation channel has a diameter of 50-100 μm and is filled with graphene nanosheets.

[0011] Preferably, a glass powder transition layer with a thickness of 1-2 μm is provided between the dielectric layer and the first inner electrode and the second inner electrode, respectively.

[0012] Compared with existing technologies, the beneficial effects of this invention are as follows: By adopting an interdigitated internal electrode structure, the effective surface area of ​​the electrodes is effectively increased, resulting in a 40%–60% increase in capacitance per unit volume compared to traditional parallel plate structures. The internally placed ceramic pillars significantly enhance the bonding force between the dielectric layer and the electrodes, preventing delamination and cracking. In terms of heat dissipation, the internally placed heat dissipation channels filled with graphene nanosheets, combined with a ceramic-metal composite encapsulation shell, improve thermal conductivity and significantly enhance the stability of the capacitor under high load conditions. In terms of electrical performance, the optimized electrode layout and composite dielectric material result in an equivalent series resistance (ESR) of ≤5mΩ at 1MHz high frequency, which is significantly better than similar products (ESR≥15mΩ). At the same time, the trapezoidal transition region design at the ends of the interdigitated fingers effectively reduces current density concentration and enhances anti-pulse capability. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the overall structure of this utility model.

[0014] In the figure: 1. Dielectric layer; 2. First inner electrode; 3. Second inner electrode; 4. Encapsulation shell; 5. Outer electrode; 51. Electroplated copper layer; 52. Electroless nickel plating layer; 53. Electroplated tin layer; 6. Ceramic pillar; 7. Heat dissipation channel; 8. Hot melt component. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0016] Please see Figure 1 This utility model provides a technical solution: an interdigitated electrode reinforced multilayer ceramic capacitor, comprising a dielectric layer 1, a first inner electrode 2, a second inner electrode 3, a package shell 4, and an outer electrode 5. The first inner electrode 2 and the second inner electrode 3 are distributed in an interdigitated pattern within the dielectric layer 1. The package shell 4 surrounds the outer ring of the dielectric layer 1. The outer electrodes 5 are disposed at both ends of the dielectric layer 1. A through ceramic pillar 6 is disposed inside the dielectric layer 1. A heat dissipation channel 7 is formed on the surface of the dielectric layer 1. A heat-fusion element 8 is disposed on the outer surface of the package shell 4. The outer electrode 5 is a surface-mount lead. The interdigitated ends of the first inner electrode 2 and the second inner electrode 3 converge and extend to the two ends of the dielectric layer 1. During the electrical lead-out stage, the inner electrodes are interconnected across layers through laser drilling and metallized through-hole processes to form a low-impedance three-dimensional conductive path, which is finally connected to the composite outer electrode 5 at both ends of the capacitor. When the capacitor is mounted on the circuit board through a surface mount, the tin layer of the outer electrode 5 forms a metallurgical bond with the PCB pad at high temperature. At the same time, the hot melt component 8 on the surface of the package 4 generates a mechanical locking force after cooling, ensuring the reliability of the device under vibration environment.

[0017] Furthermore, the first inner electrode 2 and the second inner electrode 3 constitute interdigitated inner electrodes, and the first inner electrode 2 and the second inner electrode 3 are arranged in an interdigitated staggered manner. The width of the interdigitated electrodes is 5-10 μm, the spacing is 3-5 μm, and the height is 10-20 μm. The first inner electrode 2 and the second inner electrode 3 are made of copper-nickel alloy (Cu-Ni, mass ratio 8:2) to form the interdigitated shape. The interdigitated inner electrodes of adjacent layers are staggered in the stacking direction to increase the effective overlapping area, and the width is 0.1-0.5 mm and the spacing is 0.05-0.2 mm.

[0018] Furthermore, the dielectric layer 1 is made of barium titanate-strontium titanate composite ceramic material, and multiple layers are stacked alternately. The encapsulation shell 4 is made of ceramic-metal composite substrate material. Through the setting of dielectric layer 1, the dielectric layer 1 adopts barium titanate-strontium titanate composite ceramic (dielectric constant >3000 and low dielectric loss <0.02), and is doped with lanthanum oxide (0.5-1.5wt%) to improve temperature stability. The outer shell encapsulation 4 adopts ceramic-metal composite substrate AlN / Al2O3, which has both high thermal conductivity (150 W / m·K) and mechanical strength (bending strength >300 MPa).

[0019] Furthermore, the external electrode 5 includes an electroplated copper layer 51, an electroless nickel plating layer 52, and an electroplated tin layer 53. The electroplated copper layer 51 has a thickness of 2-5 μm, the electroless nickel plating layer 52 has a thickness of 1-3 μm, and the electroplated tin layer 53 has a thickness of 3-8 μm. Through the setting of the external electrode 5, the external electrode 5 adopts a three-layer structure of copper (Cu) / nickel (Ni) / tin (Sn). The bottom Cu layer reduces the contact resistance, the middle Ni layer blocks diffusion, and the top Sn layer improves solderability.

[0020] Furthermore, the ceramic pillar 6 has a diameter of 0.3 to 0.8 mm and is made of Al2O3 and ZrO2 materials. The ceramic pillar 6 is set to reinforce the multilayer ceramic pillar 6. The through ceramic pillar 6 (0.3 to 0.8 mm in diameter) in the laminate enhances the bonding force between the dielectric layer 1 and the interdigitated inner electrode and prevents delamination cracking.

[0021] Furthermore, the heat dissipation channel 7 has a diameter of 50-100μm and is filled with graphene nanosheets. Through the setting of heat dissipation channel 7, the thermal conductivity is increased to 200W / (m·K) by the graphene filling channel, the junction temperature is reduced by less than 20℃, and the heat dissipation efficiency is greatly improved. Alternatively, the nanocomposite dielectric material BaTiO3 / epoxy resin can be used as filler, the dielectric constant is increased to more than 100, and partial discharge is suppressed at the same time.

[0022] Furthermore, a glass powder transition layer with a thickness of 1-2 μm is provided between the dielectric layer 1 and the first inner electrode 2 and the second inner electrode 3, respectively. By providing a glass powder (B2O3-SiO2-ZnO) transition layer with a thickness of 1-2 μm between the ceramic dielectric layer and the inner electrode, the interfacial bonding strength is improved.

[0023] Working principle: First, in the manufacturing stage, barium titanate-based nanopowder slurry is formed into a 10-20μm thick green ceramic sheet using a casting process to form the base material of dielectric layer 1. Then, using nano-silver paste printing technology, three-dimensional interdigitated electrode patterns are precisely printed on the dielectric layer to form the first inner electrode 2 and the second inner electrode 3. The interdigitated width is controlled at 5-10μm and the spacing is 3-5μm. The alternating finger structure significantly increases the effective electrode area. During lamination and sintering, the green ceramic sheet with printed electrodes is subjected to a pressure of 100MPa. After stacking 200 layers, the material is hot-compressed and then co-fired at 1200℃ for 2 hours in a nitrogen atmosphere to form a complete ceramic dielectric laminate. At this stage, the internally placed through-ceramic pillars 6, with a diameter of 0.3–0.8 mm, are made of Al₂O₃ or ZrO₂ and work together with the alternately stacked dielectric layers to enhance structural stability. Simultaneously, heat dissipation channels 7 with a diameter of 50–100 μm are opened on the surface of dielectric layer 1 and filled with graphene nanosheets to improve thermal conductivity. In terms of electrical connection, the first internal electrode 2 and the second internal electrode 3 extend to both ends of the capacitor. At the end, a three-dimensional conductive path is formed by connecting cross-layer electrodes through laser drilling and metallized through-holes. The outer electrode 5 adopts a three-layer composite structure, including an electroplated copper layer 51 with a thickness of 2-5 μm to reduce contact resistance, an electroless nickel plating layer 52 with a thickness of 1-3 μm to block diffusion, and an electroplated tin layer 53 with a thickness of 3-8 μm to improve solderability. During operation, when an external voltage is applied to the outer electrode 5, current flows through the three-dimensional interdigitated electrode structure to form a uniform electric field in the dielectric layer 1. Due to the interdigitated staggered arrangement design, the effective area per unit volume is greatly increased, sealing... The housing 4 is made of ceramic-metal composite substrate material, and the outer surface hot-melt component 8 is fixed to the equipment substrate by hot-melt process. Combined with the graphene filling material of heat dissipation channel 7, efficient thermal management is achieved, reducing the junction temperature by less than 20°C. At the same time, the 1-2μm glass powder transition layer set between the dielectric layer and the inner electrode optimizes the interface bonding strength. Combined with the trapezoidal transition area design at the end of the interdigital fingers, the current density concentration is reduced. Ultimately, the capacitor achieves a synergistic effect of high capacity, high stability and excellent heat dissipation performance with an equivalent series resistance (ESR) of ≤5mΩ at a high frequency of 1MHz.

[0024] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A multilayer ceramic capacitor with interdigitated electrode reinforcement, characterized in that: The package includes a dielectric layer (1), a first inner electrode (2), a second inner electrode (3), a package housing (4), and an outer electrode (5). The first inner electrode (2) and the second inner electrode (3) are distributed in an interdigitated manner inside the dielectric layer (1). The package housing (4) surrounds the outer ring of the dielectric layer (1). The outer electrodes (5) are provided at both ends of the dielectric layer (1). A through ceramic pillar (6) is provided inside the dielectric layer (1). A heat dissipation channel (7) is provided on the surface of the dielectric layer (1). A heat fusion element (8) is provided on the outer surface of the package housing (4).

2. The interdigitated electrode reinforced multilayer ceramic capacitor according to claim 1, characterized in that: The first inner electrode (2) and the second inner electrode (3) form an interdigitated inner electrode, and the first inner electrode (2) and the second inner electrode (3) are arranged in an interdigitated pattern with a width of 5-10 μm, a spacing of 3-5 μm, and a height of 10-20 μm.

3. The interdigitated electrode reinforced multilayer ceramic capacitor according to claim 1, characterized in that: The dielectric layer (1) is made of barium titanate-strontium titanate composite ceramic material, and multiple layers are stacked alternately. The encapsulation shell (4) is made of ceramic-metal composite substrate material.

4. The interdigitated electrode reinforced multilayer ceramic capacitor according to claim 1, characterized in that: The external electrode (5) includes an electroplated copper layer (51), an electroless nickel plating layer (52), and an electroplated tin layer (53). The electroplated copper layer (51) has a thickness of 2-5 μm, the electroless nickel plating layer (52) has a thickness of 1-3 μm, and the electroplated tin layer (53) has a thickness of 3-8 μm.

5. The interdigitated electrode reinforced multilayer ceramic capacitor according to claim 1, characterized in that: The ceramic column (6) has a diameter of 0.3 to 0.8 mm and is made of Al2O3 and ZrO2 materials.

6. The interdigitated electrode reinforced multilayer ceramic capacitor according to claim 1, characterized in that: The heat dissipation channel (7) has a diameter of 50-100 μm and is filled with graphene nanosheets.

7. The interdigitated electrode reinforced multilayer ceramic capacitor according to claim 1, characterized in that: A glass powder transition layer with a thickness of 1-2 μm is provided between the dielectric layer (1) and the first inner electrode (2) and the second inner electrode (3).

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