DC-to-DC input overvoltage protection circuit

Abstract

The utility model relates to integrated circuit technical field, concretely is a kind of DC conversion DC input overvoltage protection circuit, it can avoid important circuit and component of rear stage not to be damaged by external overvoltage influence, the 1 foot of voltage stabilizing chip U1 is connected 12V power supply and capacitor C1 one end, the 2 foot of voltage stabilizing chip U1 is connected inductance one end and diode D1 cathode, the 4 foot of voltage stabilizing chip U1 is connected capacitor C2 one end, resistance R2 one end, triode Q1 emitter, resistance R5 one end, the source end of PMOS tube Q2 and inductance L1 other end, triode Q1 collector connection resistance R3 one end, resistance R2 one end, the grid end of PMOS tube Q2, triode Q1 base connection resistance R4 one end, resistance R4 other end connection diode DW1 cathode and resistance R5 other end, the drain end of PMOS tube Q2 is connected capacitor C3 one end and exports 5V voltage, capacitor C1 other end, the 3 foot and 5 foot of voltage stabilizing chip U1, diode D1 anode, capacitor C2 other end, resistance R3 other end, diode DW1 anode, capacitor C3 other end are all grounded.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit technology, specifically to a DC-to-DC input overvoltage protection circuit. Background Technology

[0002] The DC-to-DC converter circuit is used in our company's Buck converter circuits. This converter circuit transforms high voltage into low voltage, such as 12V to 5V or 12V to 3.3V, using PWM voltage modulation, inductor energy storage, and diode freewheeling to achieve the set voltage output. Therefore, in the DC-to-DC converter circuit, when the PWM conversion chip is short-circuited, the output voltage will become high. This high voltage can damage the subsequent circuitry due to overvoltage.

[0003] Most electronic products use a simple protection system like a TVS (Transient Voltage Suppressor) to suppress high-energy surges from external sources. While these systems can handle high power (up to kilowatts), the suppression time is very short. If components fail or the operating voltage remains above normal for an extended period, the protection becomes inadequate. Power supply protection is paramount, and good power supply protection is indispensable. A good power supply protects critical downstream circuits and components from damage caused by external overvoltage. Summary of the Invention

[0004] To solve the above-mentioned technical problems, this utility model provides a DC-to-DC input overvoltage protection circuit, which can prevent important downstream circuits and components from being damaged by external overvoltage, reduce maintenance costs, and improve maintenance efficiency.

[0005] The technical solution is as follows: A DC-to-DC input overvoltage protection circuit includes a voltage regulator chip U1. The voltage regulator chip U1 has pin 1 connected to a 12V power supply and one end of capacitor C1; pin 2 connected to one end of an inductor and the cathode of diode D1; pin 4 connected to one end of capacitor C2, one end of resistor R2, the emitter of transistor Q1, one end of resistor R5, the source of PMOS transistor Q2, and the other end of inductor L1; and the collector of transistor Q1 is connected to... One end of resistor R3, one end of resistor R2, and the gate terminal of PMOS transistor Q2 are connected to one end of resistor R4. The other end of resistor R4 is connected to the cathode of diode DW1 and the other end of resistor R5. The drain terminal of PMOS transistor Q2 is connected to one end of capacitor C3 and outputs a 5V voltage. The other end of capacitor C1, pins 3 and 5 of voltage regulator chip U1, the anode of diode D1, the other end of capacitor C2, the other end of resistor R3, the anode of diode DW1, and the other end of capacitor C3 are all grounded.

[0006] By adopting this utility model, an overvoltage protection circuit is added. A PMOS transistor is used to control the output voltage. When the circuit outputs 5V normally, the PMOS transistor is turned on, and the 5V voltage supplies power to the subsequent circuit. When the output voltage exceeds the limit, the PMOS transistor is turned off, and the overvoltage stops supplying power to the subsequent circuit, thereby achieving the circuit protection function. This prevents important subsequent circuits and components from being damaged by external overvoltage, reduces maintenance costs, reduces the time spent troubleshooting, and greatly improves maintenance efficiency. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the circuit under normal operating conditions of this utility model; Figure 2 This is a schematic diagram of the circuit under abnormal conditions of this utility model. Detailed Implementation

[0008] See Figure 1 As shown, a DC-to-DC input overvoltage protection circuit includes a voltage regulator chip U1, model LM2576-5V. Pin 1 of the voltage regulator chip U1 is connected to a 12V power supply and one end of capacitor C1. Pin 2 of the voltage regulator chip U1 is connected to one end of an inductor and the cathode of diode D1. Pin 4 of the voltage regulator chip U1 is connected to one end of capacitor C2, one end of resistor R2, the emitter of transistor Q1, one end of resistor R5, the source of PMOS transistor Q2, and the other end of inductor L1. The collector of transistor Q1 is connected to... Connect one end of resistor R3, one end of resistor R2, and the gate of PMOS transistor Q2. Connect the base of transistor Q1 to one end of resistor R4. Connect the other end of resistor R4 to the cathode of diode DW1 and the other end of resistor R5. Connect the drain of PMOS transistor Q2 to one end of capacitor C3 to output a 5V voltage. The other end of capacitor C1, pins 3 and 5 of voltage regulator chip U1, the anode of diode D1, the other end of capacitor C2, the other end of resistor R3, the anode of diode DW1, and the other end of capacitor C3 are all grounded. The working principle is as follows: Under normal operating conditions, the 12V power supply is stepped down to 5V by voltage regulator chip U1 at high frequency. At this time, transistor Q1 is cut off, and the voltage at point A is the voltage divider of resistors R2 and R3, approximately 0.87V. PMOS transistor Q2's Vgs < -4V, so PMOS transistor Q2 is turned on, and the 5V output is normal.

[0009] See Figure 2 As described above, due to certain circumstances, such as a short circuit in the voltage regulator chip U1, or other reasons, the +5V voltage unexpectedly rises. For example, the voltage at point B rises to 5.5V, while point A, limited by diode DW1, remains at 5.1V. Since Ve > Vb, transistor Q1 conducts. After transistor Q1 conducts, the voltage at point C approaches 5.5V. The gate voltage of PMOS transistor Q2 is close to the voltage at point B (5.5V), so PMOS transistor Q2 turns off, thus stopping the voltage output to VCC and achieving overvoltage protection.

[0010] In this application, diode D1, capacitor C1, capacitor C2, voltage regulator chip U1, and inductor L1 constitute a step-down circuit to realize the function of converting 12V voltage to 5V voltage, with an output voltage of 5V and a maximum load current of I=3A.

[0011] Resistors R2, R3, R4, and R5, transistor Q1, PMOS transistor Q2, and diode DW1 constitute an overvoltage protection circuit to achieve overvoltage protection for the circuit. The overvoltage protection point is 5.5V.

Claims

1. A DC-to-DC input overvoltage protection circuit, comprising a voltage regulator chip U1, characterized in that, Pin 1 of the voltage regulator chip U1 is connected to a 12V power supply and one end of capacitor C1. Pin 2 of the voltage regulator chip U1 is connected to one end of an inductor and the cathode of diode D1. Pin 4 of the voltage regulator chip U1 is connected to one end of capacitor C2, one end of resistor R2, the emitter of transistor Q1, one end of resistor R5, the source of PMOS transistor Q2, and the other end of inductor L1. The collector of transistor Q1 is connected to one end of resistor R3, one end of resistor R2, and the gate of PMOS transistor Q2. The base of transistor Q1 is connected to one end of resistor R4. The other end of resistor R4 is connected to the cathode of diode DW1 and the other end of resistor R5. The drain of PMOS transistor Q2 is connected to one end of capacitor C3 and outputs a 5V voltage. The other end of capacitor C1, pins 3 and 5 of voltage regulator chip U1, the anode of diode D1, the other end of capacitor C2, the other end of resistor R3, the anode of diode DW1, and the other end of capacitor C3 are all grounded.

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