An IGBT protection circuit

Abstract

The disclosure provides an IGBT protection circuit, a voltage detection unit is connected with the collector of upper and lower IGBTs, used for detecting the collector voltage of the upper and lower IGBTs and outputting the collector voltage to a fault detection unit; the fault detection unit is used for receiving the collector voltage output by the voltage detection unit, comparing the collector voltage with a reference voltage, and switching the control signal output to the drive protection unit from high level to low level in the case that the collector voltage is greater than the reference voltage; a signal processing unit is used for receiving the drive signal of the upper and lower IGBTs output by a processor, performing dead zone control on the drive signal, obtaining the processed drive signal, and outputting the processed drive signal to the drive protection unit; the drive protection unit is connected with the gate of the upper and lower IGBTs, used for performing logical AND operation on the control signal and the processed drive signal, and driving the upper and lower IGBTs according to the operation result. The embodiment of the disclosure can realize fast and reliable drive protection for IGBT devices.

Description

Technical Field

[0001] This disclosure relates to the field of power electronic device protection technology, and in particular to an IGBT protection circuit. Background Technology

[0002] Currently, it is impossible to achieve fast and reliable drive protection for Insulated Gate Bipolar Transistors (IGBTs) in related technologies. On the one hand, software protection methods based on microcontroller units (MCUs) / field-programmable gate arrays (FPGAs) cannot guarantee the reliability of drive protection. On the other hand, hardware protection methods based on optocoupler interlocks cannot achieve fast protection of IGBT devices due to their limited response time, and their detection mechanism is simple and prone to false triggering under complex operating conditions. Summary of the Invention

[0003] This disclosure provides an IGBT protection circuit that enables fast and reliable drive protection for IGBT devices.

[0004] In a first aspect, this disclosure provides an IGBT protection circuit, which includes: a voltage detection unit, a fault detection unit, a signal processing unit, and a drive protection unit; the voltage detection unit is connected to the collectors of the upper and lower IGBT transistors, and is used to detect the collector voltages of the upper and lower IGBT transistors, and output the collector voltages to the fault detection unit; the fault detection unit is used to receive the collector voltages output by the voltage detection unit, compare the collector voltages with a reference voltage, and, if the collector voltages are greater than the reference voltages, switch the control signal output to the drive protection unit from a high level to a low level; the signal processing unit is used to receive... The processor outputs drive signals for the upper and lower IGBT transistors. Dead-time control is applied to these drive signals to obtain a processed drive signal, which is then output to the drive protection unit. Specifically, if the dead time of the drive signal is greater than or equal to a preset time, the processed drive signal has the same dead time as the original drive signal; if the dead time of the drive signal is less than the preset time, the dead time of the processed drive signal is the preset time. The drive protection unit is connected to the gates of the upper and lower IGBT transistors and performs a logical AND operation on the control signal and the processed drive signal, driving the upper and lower IGBT transistors based on the operation result.

[0005] In one optional implementation, the signal processing unit includes: an enhancement module, an inversion module, a delay module, and an interlock module; the driving signal includes a first driving signal for controlling the upper IGBT and a second driving signal for controlling the lower IGBT; the enhancement module is used to enhance the first driving signal and the second driving signal to obtain a first enhanced driving signal and a second enhanced driving signal, and output them to the delay module; the inversion module is used to invert the first driving signal and the second driving signal to obtain a first inverted driving signal and a second inverted driving signal, and output them to the interlock module; the delay module is used to delay the first enhanced driving signal by a preset time to obtain a first delayed driving signal, and then delay the second enhanced driving signal... The signal is delayed by the preset time to obtain a second delayed drive signal, and the first delayed drive signal and the second delayed drive signal are output to the interlock module; the preset time is not greater than the preset dead time when the processor normally transmits waves; the interlock module is used to perform a logical AND operation on the first reverse drive signal and the second delayed drive signal to obtain a processed second drive signal, and to perform a logical AND operation on the second reverse drive signal and the first delayed drive signal to obtain a processed first drive signal; wherein, the processed drive signal includes the processed first drive signal and the processed second drive signal, the processed first drive signal is used to control the upper IGBT, and the processed second drive signal is used to control the lower IGBT.

[0006] In one optional implementation, the delay module includes: a first delay module for outputting the first delay drive signal, and a second delay module for outputting the second delay drive signal; the first delay module includes a first resistor, a second resistor, a third resistor, a first diode, a second diode, and a first capacitor; a first end of the first resistor and a first end of the second resistor are connected to the signal output terminal of the first enhancement drive signal of the enhancement module, and a second end of the first resistor is connected to the cathode of the second diode; the second end of the second resistor, the first end of the third resistor, the first end of the first capacitor, the anode of the first diode, and the anode of the second diode are connected to the signal output terminal of the first delay drive signal of the first delay module; the third resistor... The second terminal is grounded to the second terminal of the first capacitor; the cathode of the first diode is connected to the positive terminal of the power supply; the second delay module includes a fourth resistor, a fifth resistor, a sixth resistor, a third diode, a fourth diode, and a second capacitor; the first terminals of the fourth resistor and the fifth resistor are connected to the signal output terminal of the second enhancement drive signal of the enhancement module, and the second terminal of the fourth resistor is connected to the cathode of the fourth diode; the second terminal of the fifth resistor, the first terminal of the sixth resistor, the first terminal of the second capacitor, the anode of the third diode, and the anode of the fourth diode are connected to the signal output terminal of the second delay drive signal of the second delay module; the second terminal of the sixth resistor is grounded to the second terminal of the second capacitor; the cathode of the third diode is connected to the positive terminal of the power supply.

[0007] In one optional implementation, the enhancement module includes a first AND gate and a second AND gate; the processor outputs the first driving signal via a first signal output terminal and the second driving signal via a second signal output terminal; the input terminal of the first AND gate is connected to the first signal output terminal of the processor, and the output terminal of the first AND gate is connected to the delay module for outputting the first enhanced driving signal; the input terminal of the second AND gate is connected to the second signal output terminal of the processor, and the output terminal of the second AND gate is connected to the delay module for outputting the second enhanced driving signal.

[0008] In one optional implementation, the inverting module includes a first NOT gate and a second NOT gate; the input of the first NOT gate is connected to the first signal output of the processor, and the output of the first NOT gate is connected to the interlock module for outputting the first inverting drive signal; the input of the second NOT gate is connected to the second signal output of the processor, and the output of the second NOT gate is connected to the interlock module for outputting the second inverting drive signal.

[0009] In one optional implementation, the interlock module includes a third AND gate and a fourth AND gate; the input of the third AND gate is connected to the signal output of the second inverted drive signal of the inverting module and the signal output of the first delayed drive signal of the delay module, and the output of the third AND gate is connected to the drive protection unit for outputting the processed first drive signal; the input of the fourth AND gate is connected to the signal output of the first inverted drive signal of the inverting module and the signal output of the second delayed drive signal of the delay module, and the output of the fourth AND gate is connected to the drive protection unit for outputting the processed second drive signal.

[0010] In one optional implementation, the drive protection unit includes a fifth AND gate and a sixth AND gate; the input of the fifth AND gate is connected to the first signal output of the fault detection unit and the signal output of the processed first drive signal of the interlock module, and the output of the fifth AND gate is connected to the gate of the upper IGBT; wherein, the first signal output of the fault detection unit is used to output a control signal characterizing the comparison relationship between the collector voltage of the upper IGBT and the reference voltage; the input of the sixth AND gate is connected to the second signal output of the fault detection unit and the signal output of the processed second drive signal of the interlock module, and the output of the sixth AND gate is connected to the gate of the lower IGBT; wherein, the second signal output of the fault detection unit is used to output a control signal characterizing the comparison relationship between the collector voltage of the lower IGBT and the reference voltage.

[0011] In one optional implementation, the collector voltage includes a first collector voltage of the upper IGBT and a second collector voltage of the lower IGBT; the voltage detection unit includes a first detection module and a second detection module; the first detection module includes a fifth diode, a seventh resistor, an eighth resistor, a third capacitor, and a fourth capacitor; the first terminal of the seventh resistor is connected to the anode of the fifth diode and is connected to the collector of the upper IGBT through the eighth resistor, and the second terminal of the seventh resistor and the first terminal of the fourth capacitor are connected to the output terminal of the first collector voltage of the first detection module; the cathode of the fifth diode is connected to the positive terminal of the power supply and the first terminal of the third capacitor, and the second terminals of the third capacitor and the second terminal of the fourth capacitor are grounded; the second detection module includes a sixth diode, a ninth resistor, a tenth resistor, a fifth capacitor, and a sixth capacitor; the first terminal of the ninth resistor is connected to the anode of the sixth diode and is connected to the collector of the lower IGBT through the tenth resistor, and the second terminal of the ninth resistor and the first terminal of the sixth capacitor are connected to the output terminal of the second collector voltage of the second detection module; the cathode of the sixth diode is connected to the positive terminal of the power supply and the first terminal of the fifth capacitor, and the second terminals of the fifth capacitor and the second terminal of the sixth capacitor are grounded.

[0012] In one optional implementation, the first detection module further includes a first switching transistor, and the second detection module further includes a second switching transistor; the drain of the first switching transistor is connected to the output terminal of the first collector voltage of the first detection module, the source of the first switching transistor is grounded, and the gate of the first switching transistor is used to input a detection control signal to control the conduction state of the first switching transistor; the drain of the second switching transistor is connected to the output terminal of the second collector voltage of the second detection module, the source of the second switching transistor is grounded, and the gate of the second switching transistor is used to input the detection control signal to control the conduction state of the second switching transistor.

[0013] In one optional implementation, the fault detection unit includes a first comparator, a second comparator, a first filter module, and a second filter module. The first input terminal of the first comparator is used to input the reference voltage, and the second input terminal of the first comparator is connected to the output terminal of the first collector voltage of the first detection module for inputting the first collector voltage. The output terminal of the first comparator outputs a first control signal to the drive protection unit through the first filter module. The first input terminal of the second comparator is used to input the reference voltage, and the second input terminal of the second comparator is connected to the output terminal of the second collector voltage of the second detection module for inputting the second collector voltage. The output terminal of the second comparator outputs a second control signal to the drive protection unit through the second filter module. The first control signal is low when the first collector voltage is greater than the reference voltage, and the second control signal is low when the second collector voltage is greater than the reference voltage.

[0014] The IGBT protection circuit provided in this embodiment can detect the collector voltage of the IGBT upper and lower transistors through a voltage detection unit; determine whether the collector voltage is greater than a reference voltage through a fault detection unit, and generate a corresponding control signal to the drive protection unit. When the collector voltage is greater than the reference voltage, the control signal switches from high to low level; the signal processing unit performs dead-time control on the drive signals of the IGBT upper and lower transistors output by the processor, so that even when the processor experiences a waveform abnormality, the signal processing unit can still output a processed drive signal with a certain dead time; finally, the drive protection unit performs a logical AND operation on the processed drive signal generated by the signal processing unit and the control signal generated by the fault detection unit, and drives the IGBT upper and lower transistors according to the operation result. Therefore, the IGBT protection circuit provided in this embodiment can achieve two levels of fast drive protection for IGBTs, namely collector overvoltage protection and waveform abnormality protection, improving the reliability of drive protection for IGBT devices.

[0015] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a schematic diagram of the structure of an IGBT protection circuit provided in an embodiment of the present disclosure;

[0018] Figure 2 This is a schematic diagram of the signal processing unit.

[0019] Figure 3 This is a schematic diagram of the signals generated by the signal processing unit when the processor is transmitting signals normally.

[0020] Figure 4 This is a schematic diagram of the signals generated by the signal processing unit when the processor emits abnormal signals.

[0021] Figure 5 This is a schematic diagram of the signal processing unit.

[0022] Figure 6 This is a schematic diagram of the drive protection unit.

[0023] Figure 7 This is a schematic diagram of the voltage detection unit.

[0024] Figure 8 This is a schematic diagram of the fault detection unit.

[0025] Figure 9 This is a schematic diagram of the structure of an IGBT protection circuit provided in an embodiment of this disclosure. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0027] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0028] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0030] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0031] For IGBT drive protection, MCU / FPGA-based protection methods cannot guarantee reliable drive protection due to the inability to ensure the stability of the software program. Hardware protection methods based on optocoupler interlocks suffer from long response times, hindering rapid IGBT protection, and their simplistic detection mechanisms are prone to false triggering under complex operating conditions. Therefore, existing IGBT drive protection methods fail to provide reliable and rapid drive protection for IGBTs.

[0032] This disclosure provides an IGBT protection circuit that can detect the collector voltage of the upper and lower IGBT transistors through a voltage detection unit; determine whether the collector voltage is greater than a reference voltage through a fault detection unit, thereby generating a corresponding control signal to the drive protection unit, and when the collector voltage is greater than the reference voltage, the control signal switches from a high level to a low level; thereby, the signal processing unit performs dead-time control on the drive signals of the upper and lower IGBT transistors output by the processor, so that when the processor emits abnormal signals, the signal processing unit can also output a processed drive signal with a certain dead time; finally, the drive protection unit performs a logical AND operation on the processed drive signal generated by the signal processing unit and the control signal generated by the fault detection unit, thereby driving the upper and lower IGBT transistors according to the operation result.

[0033] Therefore, the IGBT protection circuit provided in this embodiment can achieve two levels of fast drive protection for IGBTs, namely collector overvoltage protection and ripple abnormality protection, and improve the reliability of drive protection for IGBT devices.

[0034] Figure 1 This is a schematic diagram of an IGBT protection circuit provided in an embodiment of the present disclosure, with reference to... Figure 1 The IGBT protection circuit includes: a voltage detection unit 10, a fault detection unit 11, a signal processing unit 12, and a drive protection unit 13.

[0035] The voltage detection unit 10 is connected to the collector of the upper and lower IGBT transistors and is used to detect the collector voltage, Vce voltage, of the upper and lower IGBT transistors and output the collector voltage to the fault detection unit 11.

[0036] The fault detection unit 11 is used to receive the collector voltage output by the voltage detection unit 10, compare the collector voltage with the reference voltage, and switch the control signal output to the drive protection unit 13 from high level to low level when the collector voltage is greater than the reference voltage.

[0037] It should be noted that the reference voltage is the fault detection threshold for the upper and lower IGBT transistors. When an IGBT device experiences a short circuit, it enters a desaturation state, and the collector voltage Vce of the upper and lower IGBT transistors rises. Therefore, after the Vce voltage detected by the fault detection unit 11 exceeds its set reference voltage Vref, a low-level control signal is output to the drive protection unit 13 to stop the drive protection unit 13 from generating signals, thereby protecting the upper and lower IGBT transistors.

[0038] Correspondingly, when the short-circuit fault of the IGBT device is cleared, if the collector voltage of the upper and lower IGBT transistors is not greater than the reference voltage, the fault detection unit 11 can output a high-level control signal to enable the drive protection unit 13 to continue to generate waves, that is, to drive the upper and lower IGBT transistors according to the preset conduction logic.

[0039] The signal processing unit 12 receives the drive signals for the IGBT upper and lower transistors output by the processor, performs dead-time control on the drive signals to obtain the processed drive signal, and outputs the processed drive signal to the drive protection unit 13. Furthermore, if the dead time of the drive signal is greater than or equal to a preset time, the processed drive signal has the same dead time as the drive signal; if the dead time of the drive signal is less than the preset time, the dead time of the processed drive signal is the preset time.

[0040] Therefore, it can be seen that the signal processing unit 12 can perform dead-time control on the drive signal output by the processor. Thus, in the event of an abnormal processor waveform, the dead time of the drive signal is abnormal. If the IGBT upper and lower transistors are driven according to the original drive signal, the IGBT upper and lower transistors may conduct simultaneously. However, the dead time of the drive signal generated by the signal processing unit 12 in this embodiment can be maintained at a preset time, thereby preventing the IGBT upper and lower transistors from conducting simultaneously. When the processor is transmitting a normal waveform, the dead time of its drive signal is greater than the preset time. Correspondingly, the dead time of the drive signal generated by the signal processing unit 12 remains consistent with the dead time of the drive signal issued by the processor, that is, the conduction control of the IGBT upper and lower transistors is performed according to the dead time of the drive signal issued by the processor.

[0041] The drive protection unit 13 is connected to the gates of the upper and lower IGBT transistors and is used to perform a logical AND operation on the control signal and the processed drive signal, and drive the upper and lower IGBT transistors according to the operation result.

[0042] Since the drive protection unit 13 drives and protects the IGBT upper and lower transistors through the logical AND operation result of the control signal and the processed drive signal, when the control signal is low, the drive protection unit 13 will not output drive signals to the IGBT upper and lower transistors. However, when the control signal is high, the drive protection unit 13 will output the processed drive signals to the IGBT upper and lower transistors, controlling them to conduct according to a preset timing sequence.

[0043] The IGBT protection circuit provided in this embodiment can detect the collector voltage of the IGBT upper and lower transistors through a voltage detection unit; determine whether the collector voltage is greater than a reference voltage through a fault detection unit, and generate a corresponding control signal to the drive protection unit. When the collector voltage is greater than the reference voltage, the control signal switches from high to low level; the signal processing unit performs dead-time control on the drive signals of the IGBT upper and lower transistors output by the processor, so that even when the processor experiences a waveform abnormality, the signal processing unit can still output a processed drive signal with a certain dead time; finally, the drive protection unit performs a logical AND operation on the processed drive signal generated by the signal processing unit and the control signal generated by the fault detection unit, and drives the IGBT upper and lower transistors according to the operation result. Therefore, the IGBT protection circuit provided in this embodiment can achieve two levels of drive protection for the IGBT, namely collector overvoltage protection and waveform abnormality protection, thereby improving the reliability of drive protection for the IGBT device.

[0044] In one alternative implementation, to achieve dead-time control of the drive signal, the signal processing unit includes: an enhancement module, an inversion module, a delay module, and an interlock module.

[0045] Figure 2 A schematic diagram of the signal processing unit is shown, with reference to... Figure 2 The signal processing unit 12 includes an enhancement module 121, an inversion module 122, a delay module 123, and an interlock module 124.

[0046] The drive signals include a first drive signal EPWM1 ​​for controlling the upper IGBT and a second drive signal EPWM2 for controlling the lower IGBT. The upper and lower IGBTs are connected in series between the positive and negative terminals of the bus, with the upper IGBT connected to the positive terminal and the lower IGBT connected to the negative terminal.

[0047] The enhancement module 121 is used to enhance the first drive signal EPWM1 ​​and the second drive signal EPWM2 to obtain a first enhanced drive signal and a second enhanced drive signal, which are then output to the delay module 123. The enhancement process enhances the signal driving capability of the first drive signal EPWM1 ​​and the second drive signal EPWM2.

[0048] The inversion module 122 is used to invert the first drive signal EPWM1 ​​and the second drive signal EPWM2 to obtain the first inverted drive signal EPWM1_NOT and the second inverted drive signal EPWM2_NOT, and output them to the interlock module 124.

[0049] The delay module 123 is used to delay the first enhanced drive signal for a preset time to obtain the first delayed drive signal EPWM1_Delay, and to delay the second enhanced drive signal for a preset time to obtain the second delayed drive signal EPWM2_Delay. The first delayed drive signal EPWM1_Delay and the second delayed drive signal EPWM2_Delay are then output to the interlock module 124. Furthermore, this preset time is not greater than the preset dead time during normal waveform generation by the processor. It should be noted that this preset time must also be greater than the minimum dead time required by the IGBT upper and lower transistors.

[0050] The interlock module 124 is used to perform a logical AND operation on the first reverse drive signal EPWM1_Delay and the second delayed drive signal EPWM2_Delay to obtain the processed second drive signal, and to perform a logical AND operation on the second reverse drive signal EPWM2_NOT and the first delayed drive signal EPWM1_Delay to obtain the processed first drive signal.

[0051] The processed drive signals include a processed first drive signal and a processed second drive signal. The processed first drive signal is used to control the upper IGBT, and the processed second drive signal is used to control the lower IGBT.

[0052] For example, Figure 3 This diagram illustrates the signals generated by the signal processing unit when the processor is transmitting signals normally. Figure 4 This diagram illustrates the signal generated by the signal processing unit when the processor emits abnormal signals.

[0053] Assuming the processor's default dead time during normal waveform transmission is 2.5µs, the default time must not exceed this default dead time, such as setting the default time to 2µs.

[0054] Reference Figure 3 During normal processor waveform transmission, the first enhanced drive signal EPWM_1 and the second enhanced drive signal EPWM_2 are delayed by 2µs after passing through the delay module, resulting in the first delayed drive signal EPWM1_Delay and the second delayed drive signal EPWM2_Delay. The interlock module performs a logical AND operation on the first inverse drive signal EPWM1_NOT and the second delayed drive signal EPWM2_Delay to obtain the processed second drive signal, and then performs a logical AND operation on the second inverse drive signal EPWM2_NOT and the first delayed drive signal EPWM1_Delay to obtain the processed first drive signal. Since the preset time must be less than or equal to the preset dead time during normal processor waveform transmission, the dead time of the processed first and processed second drive signals obtained by the interlock module's logical AND operation remains unchanged at 2.5µs.

[0055] Reference Figure 4 When the processor emits abnormal signals, if the dead time of the first and second drive signals is less than 2µs, the logic AND operation of the interlock module will ensure that the dead time of the processed first and second drive signals remains at 2µs, thereby preventing the IGBT upper and lower transistors from shooting through.

[0056] Furthermore, Figure 5 A schematic diagram of the signal processing unit is shown. (Refer to...) Figure 5 In one optional implementation, the delay module 123 includes: a first delay module 1231 for outputting a first delay drive signal, and a second delay module 1232 for outputting a second delay drive signal.

[0057] The first delay module 1231 includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, and a first capacitor C1.

[0058] Specifically, the first end of the first resistor R1 and the first end of the second resistor R2 are connected to the signal output terminal of the first enhanced drive signal of the enhancement module 121, and the second end of the first resistor R1 is connected to the cathode of the second diode D2.

[0059] The second end of the second resistor R2, the first end of the third resistor R3, the first end of the first capacitor C1, the anode of the first diode D1, and the anode of the second diode D2 are connected to the signal output terminal of the first delay drive signal of the first delay module 1231; the second end of the third resistor R3 and the second end of the first capacitor C1 are grounded; the cathode of the first diode D1 is connected to the positive terminal of the power supply.

[0060] For example, when the first enhanced drive signal is high, the first capacitor C1 is charged through the second resistor R2 and the third resistor R3, thus delaying the first enhanced drive signal for a preset time. Specifically, the preset time can be adjusted by changing the resistance values ​​of the second and third resistors and the capacitance value of the first capacitor. When the first enhanced drive signal is low, the second diode D2 is turned on, causing the first resistor R1 and the second resistor R2 to be connected in parallel, thereby reducing the discharge resistance of the first capacitor C1 and accelerating the discharge speed of the first capacitor C1, that is, realizing the slow charging and fast discharging of the first capacitor C1.

[0061] Furthermore, the second delay module 1232 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third diode D3, a fourth diode D4, and a second capacitor C2.

[0062] The first end of the fourth resistor R4 and the first end of the fifth resistor R5 are connected to the signal output terminal of the second enhanced drive signal of the enhancement module 121, and the second end of the fourth resistor R4 is connected to the cathode of the fourth diode D4.

[0063] The second terminal of the fifth resistor R5, the first terminal of the sixth resistor R6, the first terminal of the second capacitor C2, the anode of the third diode D3, and the anode of the fourth diode D4 are connected to the signal output terminal of the second delay drive signal of the second delay module 1232. The second terminal of the sixth resistor R6 and the second terminal of the second capacitor are grounded, and the cathode of the third diode D3 is connected to the positive terminal of the power supply.

[0064] For example, when the second enhanced drive signal is high, the second capacitor C2 is charged through the fifth resistor R5 and the sixth resistor R6, thus delaying the second enhanced drive signal for a preset time. Specifically, the preset time can be adjusted by changing the resistance values ​​of the fifth resistor R5, the sixth resistor R6, and the capacitance value of the second capacitor C2. When the second enhanced drive signal is low, the fourth diode D4 is turned on, causing the fourth resistor R4 to be connected in parallel with the fifth resistor R5, thereby reducing the discharge resistance of the second capacitor C2 and accelerating the discharge speed of the second capacitor C2, thus achieving slow charging and fast discharging of the second capacitor C2.

[0065] Therefore, it can be seen that by setting various resistors and capacitors in the delay module in this embodiment, the first enhanced drive signal and the second enhanced drive signal can be accurately delayed by a preset time to obtain the first delayed drive signal EPWM1_Delay and the second delayed drive signal EPWM2_Delay.

[0066] Further, continue to refer to Figure 5 In one optional implementation, to enhance the processing of the first driving signal and the second driving signal, the enhancement module 121 includes a first AND gate U1 and a second AND gate U3. The processor outputs the first driving signal EPWM1 ​​through the first signal output terminal and the second driving signal EPWM2 through the second signal output terminal.

[0067] Correspondingly, the input of the first AND gate U1 is connected to the first signal output of the processor, and the output of the first AND gate U1 is connected to the delay module 123 for outputting a first enhanced drive signal. The input of the second AND gate U3 is connected to the second signal output of the processor, and the output of the second AND gate U3 is connected to the delay module 123 for outputting a second enhanced drive signal.

[0068] In this embodiment of the disclosure, since both input terminals of the first AND gate and the second AND gate are used to input the first driving signal and the second driving signal, the driving signal can be enhanced based on the hardware characteristics of the first AND gate and the second AND gate themselves, such as the push-pull structure of the AND gate output stage, thereby outputting the first enhanced driving signal and the second enhanced driving signal to the delay module 123.

[0069] Further, continue to refer to Figure 5 In order to enable the inverting module to quickly perform inverting operations on the first driving signal and the second driving signal, in one optional implementation, the inverting module 122 includes a first NOT gate U2 and a second NOT gate U4.

[0070] The input of the first NOT gate U2 is connected to the first signal output of the processor, and the output of the first NOT gate is connected to the interlock module 124 to output the first inverting drive signal EPWM1_NOT to the interlock module 124. The input of the second NOT gate U4 is connected to the second signal output of the processor, and the output of the second NOT gate is connected to the interlock module 124 to output the second inverting drive signal EPWM2_NOT to the interlock module 124.

[0071] Therefore, the first drive signal output by the processor can be simultaneously input to the first AND gate and the first NOT gate, allowing the first AND gate and the first NOT gate to perform enhancement and inversion processing respectively. Similarly, the second drive signal output by the processor can be simultaneously input to the second AND gate and the second NOT gate, allowing the second AND gate and the second NOT gate to perform enhancement and inversion processing respectively.

[0072] Further, continue to refer to Figure 5 The interlock module 124 includes a third AND gate U5 and a fourth AND gate U6. The input of the third AND gate U5 is connected to the signal output of the second inverted drive signal of the inverting module 122 and the signal output of the first delayed drive signal of the delay module 123. The output of the third AND gate U5 is connected to the drive protection unit 13 and is used to output the processed first drive signal to the drive protection unit 13.

[0073] The input of the fourth AND gate U6 is connected to the signal output of the first inverted drive signal of the inverting module 122 and the signal output of the second delayed drive signal of the delay module 123. The output of the fourth AND gate U6 is connected to the drive protection unit 13 and is used to output the processed second drive signal to the drive protection unit 13.

[0074] The inversion module in this embodiment can perform a logical AND operation on the first delayed drive signal and the second inverted drive signal through the third AND gate U5 to obtain the processed first drive signal, and can perform a logical AND operation on the second delayed drive signal and the first inverted drive signal through the fourth AND gate U6 to obtain the processed second drive signal.

[0075] Figure 6 This is a schematic diagram of the drive protection unit, referencing... Figure 6 The drive protection unit 13 includes a fifth AND gate U7 and a sixth AND gate U8.

[0076] The input of the fifth AND gate U7 is connected to the first signal output of the fault detection unit 11 and the signal output of the processed first drive signal of the interlock module 124. The output of the fifth AND gate U7 is connected to the gate of the IGBT upper transistor. The first signal output of the fault detection unit is used to output a control signal characterizing the comparison relationship between the collector voltage of the IGBT upper transistor and the reference voltage.

[0077] In other words, the fifth AND gate U7 receives the processed first drive signal output by the interlock module 124 and the control signal output by the fault detection unit 11, which represents the comparison relationship between the collector voltage of the IGBT upper transistor and the reference voltage. By performing a logical AND operation on the two, it drives the IGBT upper transistor according to the operation result.

[0078] The input of the sixth AND gate U8 is connected to the second signal output of the fault detection unit 11 and the signal output of the processed second drive signal of the interlock module 124. The output of the sixth AND gate U8 is connected to the gate of the lower IGBT. The second signal output of the fault detection unit 11 is used to output a control signal that characterizes the comparison relationship between the collector voltage of the lower IGBT and the reference voltage.

[0079] In other words, the sixth AND gate U8 receives the processed second drive signal output by the interlock module 124 and the control signal output by the fault detection unit 11, which represents the comparison relationship between the collector voltage of the lower IGBT and the reference voltage. By performing a logical AND operation on the two signals, it drives the lower IGBT based on the operation result.

[0080] Therefore, the drive protection unit in this embodiment of the present disclosure performs a logical AND operation on the processed first drive signal and the control signal corresponding to the upper IGBT based on the fifth AND gate, and performs a logical AND operation on the processed second drive signal and the control signal corresponding to the lower IGBT based on the sixth AND gate, thereby enabling drive protection for the upper and lower IGBTs.

[0081] Furthermore, Figure 7 This is a schematic diagram of the voltage detection unit. (Refer to...) Figure 7 In one optional implementation, the voltage detection unit 10 includes a first detection module 101 and a second detection module 102. The first detection module 101 includes a fifth diode D5, a seventh resistor R7, an eighth resistor R8, a third capacitor C3, and a fourth capacitor C4. The second detection module 102 includes a sixth diode D6, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, and a sixth capacitor C6.

[0082] In this circuit, the first terminal of the seventh resistor R7 is connected to the anode of the fifth diode D5, and is connected to the collector of the IGBT upper transistor Q3 through the eighth resistor R8. The second terminal of the seventh resistor R7 and the first terminal of the fourth capacitor C4 are connected to the output terminal of the first collector voltage of the first detection module 101. The cathode of the fifth diode D5 is connected to the positive terminal of the power supply and the first terminal of the third capacitor C3. The second terminals of the third capacitor C3 and the second terminal of the fourth capacitor C4 are grounded.

[0083] Specifically, the first detection module can acquire and output the first collector voltage Vce_OV1 of the IGBT upper transistor. When a short circuit occurs, the IGBT enters a desaturation state, the collector voltage of the IGBT upper transistor rises, and the voltage change time of the first collector voltage Vce_OV1 output by the first detection module can be adjusted by the resistance value of the seventh resistor R7 and the capacitance value of the fourth capacitor C4.

[0084] Furthermore, the first end of the ninth resistor R9 is connected to the anode of the sixth diode D6, and is connected to the collector of the IGBT lower transistor Q4 through the tenth resistor R10. The second end of the ninth resistor R9 and the first end of the sixth capacitor C6 are connected to the output terminal of the second collector voltage of the second detection module 102. The cathode of the sixth diode D6 is connected to the positive terminal of the power supply and the first end of the fifth capacitor C5. The second ends of the fifth capacitor C5 and the second ends of the sixth capacitor C6 are grounded.

[0085] Specifically, the second detection module can acquire and output the second collector voltage Vce_OV2 of the IGBT lower transistor. When a short circuit occurs, the IGBT enters a desaturation state, and the collector voltage of the IGBT lower transistor rises. The voltage change time of the second collector voltage Vce_OV2 output by the second detection module can be adjusted by the resistance value of the ninth resistor R9 and the capacitance value of the sixth capacitor C6.

[0086] Continue to refer to Figure 7 In one optional implementation, the first detection module 101 further includes a first switch Q1, and the second detection module 102 further includes a second switch Q2.

[0087] In this configuration, the drain of the first switching transistor Q1 is connected to the output terminal of the first collector voltage of the first detection module 101, the source of the first switching transistor Q1 is grounded, and the gate of the first switching transistor Q1 is used to input a detection control signal to control the conduction state of the first switching transistor Q1. Similarly, the drain of the second switching transistor Q2 is connected to the output terminal of the second collector voltage of the second detection module 102, the source of the second switching transistor Q2 is grounded, and the gate of the second switching transistor Q2 is used to input a detection control signal to control the conduction state of the second switching transistor Q2.

[0088] When the first switch Q1 and the second switch Q2 are turned off, the voltage detection function of the first detection module 101 and the second detection module 102 is activated, and the first detection module 101 and the second detection module 102 can output the detected first collector voltage and the second collector voltage to the fault detection unit. When the detection control signal controls the first switch Q1 and the second switch Q2 to be turned on, the output collector voltage of the first detection module and the second detection module can be clamped to zero, thereby turning off the voltage detection function of the first detection module 101 and the second detection module 102.

[0089] Therefore, by setting a first switching transistor in the first detection module and a second switching transistor in the second detection module, the voltage detection function of the voltage detection unit can be flexibly controlled to turn on and off.

[0090] Figure 8 This is a structural diagram of the fault detection unit, referencing... Figure 8 In one optional implementation, the fault detection unit 11 includes a first comparator U9, a second comparator U10, a first filtering module 112, and a second filtering module 113.

[0091] The first input terminal of the first comparator U9 is used to input the reference voltage Vref. The second input terminal of the first comparator U9 is connected to the output terminal of the first collector voltage of the first detection module 101 and is used to input the first collector voltage Vce_OV1. The first control signal output by the output terminal of the first comparator U9 is filtered by the first filter module 112 and then output to the drive protection unit 13.

[0092] The first input terminal of the second comparator U10 is used to input the reference voltage Vref. The second input terminal of the second comparator U10 is connected to the output terminal of the second collector voltage of the second detection module 102 and is used to input the second collector voltage Vce_OV2. The second control signal output by the output terminal of the second comparator U10 is filtered by the second filter module 113 and then output to the drive protection unit 13.

[0093] Specifically, when the first collector voltage is greater than the reference voltage, the first control signal output by the first comparator U9 is low; when the first collector voltage is less than or equal to the reference voltage, the first control signal output by the first comparator U9 is high. When the second collector voltage is greater than the reference voltage, the second control signal output by the second comparator U10 is low; when the second collector voltage is less than or equal to the reference voltage, the second control signal output by the second comparator U10 is high.

[0094] Therefore, by setting a first comparator and a second comparator in the fault detection unit, overvoltage detection of the first collector voltage and the second collector voltage can be achieved. Furthermore, by filtering the first control signal output from the first comparator through a first filtering module before outputting it to the drive protection unit, and filtering the second control signal output from the second comparator through a second filtering module before outputting it to the drive protection unit, the accuracy of the control signals output to the drive protection unit can be further improved, enabling the drive protection unit to perform collector overvoltage protection on the upper and lower IGBTs based on these control signals.

[0095] Further, continue to refer to Figure 8The first filter module 112 includes an eleventh resistor R11 and a seventh capacitor C7. The second filter module 113 includes a twelfth resistor R12 and an eighth capacitor C8.

[0096] Among them, the first end of the eleventh resistor R11 and the first end of the seventh capacitor C7 are connected to the drive protection unit, the second end of the eleventh resistor R11 is connected to the output of the first comparator, and the second end of the seventh capacitor C7 is grounded.

[0097] The first end of the twelfth resistor R12 and the first end of the eighth capacitor C8 are connected to the drive protection unit. The second end of the twelfth resistor R12 is connected to the output of the second comparator. The second end of the eighth capacitor C8 is grounded.

[0098] The RC filter structure composed of the eleventh resistor R11 and the seventh capacitor C7 can filter the first control signal output from the first comparator. The RC filter structure composed of the twelfth resistor R12 and the eighth capacitor C8 can filter the second control signal output from the second comparator.

[0099] For ease of understanding, Figure 9 This is a schematic diagram of an IGBT protection circuit provided in an embodiment of the present disclosure, with reference to... Figure 9 The IGBT protection circuit includes a voltage detection unit, a fault detection unit, a signal processing unit, and a drive protection unit.

[0100] The signal processing unit includes an enhancement module, an inverting module, a delay module, and an interlocking module. The delay module includes a first delay module and a second delay module. The first delay module includes a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, a second diode D2, and a first capacitor C1. The second delay module includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third diode D3, a fourth diode D4, and a second capacitor C2. The enhancement module includes a first AND gate U1 and a second AND gate U3. The inverting module includes a first NOT gate U2 and a second NOT gate U4. The interlocking module includes a third AND gate U5 and a fourth AND gate U6.

[0101] The drive protection unit includes a fifth AND gate U7 and a sixth AND gate U8. The voltage detection unit includes a first detection module and a second detection module. The first detection module includes a fifth diode D5, a seventh resistor R7, an eighth resistor R8, a third capacitor C3, and a fourth capacitor C4. The second detection module includes a sixth diode D6, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, and a sixth capacitor C6.

[0102] The fault detection unit includes a first comparator U9, a second comparator U10, a first filter module, and a second filter module. The first filter module includes an eleventh resistor R11 and a seventh capacitor C7. The second filter module includes a twelfth resistor R12 and an eighth capacitor C8.

[0103] Specifically, the MCU outputs a first drive signal EPWM1 ​​to the first AND gate U1 and the first NOT gate U2. The first AND gate U1 outputs a first enhanced drive signal to the first delay module, and the first delay module outputs a first delayed drive signal EPWM1_Delay to the third AND gate U5. The first NOT gate U2 outputs a first inverted drive signal EPWM1_NOT to the fourth AND gate U6.

[0104] The MCU outputs the second drive signal EPWM2 to the second AND gate U3 and the second NOT gate U4. The second AND gate U3 outputs the second enhanced drive signal to the second delay module, which then outputs the second delayed drive signal EPWM2_Delay to the fourth AND gate U6. The second NOT gate U4 outputs the second inverted drive signal EPWM2_NOT to the third AND gate U5.

[0105] Furthermore, the third AND gate U5 and the fourth AND gate U6 output the processed first drive signal, and the processed second drive signal is sent to the fifth AND gate U7 and the sixth AND gate U8, respectively. The voltage detection unit acquires the first collector voltage Vce_OV1 of the upper IGBT Q3 and the second collector voltage Vce_OV2 of the lower IGBT Q4, thereby inputting the first collector voltage Vce_OV1 to the first comparator U9 for overvoltage detection, and inputting the second collector voltage Vce_OV2 to the second comparator U10 for overvoltage detection.

[0106] The first comparator U9 and the second comparator U10 compare the first collector voltage Vce_OV1 and the second collector voltage Vce_OV2 with the reference voltage Vref to obtain the control signal, and output it to the fifth AND gate U7 and the sixth AND gate U8 after RC filtering. Then, the fifth AND gate U7 and the sixth AND gate U8 perform a logical AND operation on the received control signal and the delayed drive signal, and drive the IGBT upper and lower transistors according to the operation result.

[0107] It should be noted that the specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An IGBT protection circuit, characterized in that, include: Voltage detection unit, fault detection unit, signal processing unit, and drive protection unit; The voltage detection unit is connected to the collector of the upper and lower IGBT transistors and is used to detect the collector voltage of the upper and lower IGBT transistors and output the collector voltage to the fault detection unit. The fault detection unit is used to receive the collector voltage output by the voltage detection unit, compare the collector voltage with a reference voltage, and switch the control signal output to the drive protection unit from high level to low level when the collector voltage is greater than the reference voltage. The signal processing unit is configured to receive the drive signals for the upper and lower IGBT transistors output by the processor, perform dead-time control on the drive signals to obtain a processed drive signal, and output the processed drive signal to the drive protection unit; wherein, when the dead time of the drive signal is greater than or equal to a preset time, the processed drive signal is consistent with the dead time of the drive signal; when the dead time of the drive signal is less than the preset time, the dead time of the processed drive signal is the preset time. The drive protection unit is connected to the gate of the upper and lower IGBT transistors and is used to perform a logical AND operation on the control signal and the processed drive signal, and drive the upper and lower IGBT transistors according to the operation result.

2. The IGBT protection circuit according to claim 1, characterized in that, The signal processing unit includes an enhancement module, an inversion module, a delay module, and an interlock module; the driving signals include a first driving signal for controlling the upper IGBT and a second driving signal for controlling the lower IGBT. The enhancement module is used to enhance the first driving signal and the second driving signal to obtain a first enhanced driving signal and a second enhanced driving signal, and output them to the delay module. The inversion module is used to invert the first driving signal and the second driving signal to obtain a first inverted driving signal and a second inverted driving signal, and output them to the interlock module. The delay module is used to delay the first enhanced drive signal by the preset time to obtain a first delayed drive signal, delay the second enhanced drive signal by the preset time to obtain a second delayed drive signal, and output the first delayed drive signal and the second delayed drive signal to the interlock module; the preset time is not greater than the preset dead time when the processor normally transmits waves; The interlock module is used to perform a logical AND operation on the first reverse drive signal and the second delayed drive signal to obtain a processed second drive signal, and to perform a logical AND operation on the second reverse drive signal and the first delayed drive signal to obtain a processed first drive signal. The processed drive signal includes a processed first drive signal and a processed second drive signal. The processed first drive signal is used to control the upper IGBT, and the processed second drive signal is used to control the lower IGBT.

3. The IGBT protection circuit according to claim 2, characterized in that, The delay module includes: a first delay module for outputting the first delay drive signal, and a second delay module for outputting the second delay drive signal; The first delay module includes a first resistor, a second resistor, a third resistor, a first diode, a second diode, and a first capacitor; The first end of the first resistor and the first end of the second resistor are connected to the signal output terminal of the first enhancement drive signal of the enhancement module, and the second end of the first resistor is connected to the cathode of the second diode; The second end of the second resistor, the first end of the third resistor, the first end of the first capacitor, the anode of the first diode, and the anode of the second diode are connected to the signal output terminal of the first delay drive signal of the first delay module; the second end of the third resistor and the second end of the first capacitor are grounded; the cathode of the first diode is connected to the positive terminal of the power supply. The second delay module includes a fourth resistor, a fifth resistor, a sixth resistor, a third diode, a fourth diode, and a second capacitor; The first end of the fourth resistor and the first end of the fifth resistor are connected to the signal output terminal of the second enhancement drive signal of the enhancement module, and the second end of the fourth resistor is connected to the cathode of the fourth diode; The second end of the fifth resistor, the first end of the sixth resistor, the first end of the second capacitor, the anode of the third diode, and the anode of the fourth diode are connected to the signal output terminal of the second delay drive signal of the second delay module; the second end of the sixth resistor and the second end of the second capacitor are grounded; the cathode of the third diode is connected to the positive terminal of the power supply.

4. The IGBT protection circuit according to claim 2, characterized in that, The enhancement module includes a first AND gate and a second AND gate; the processor outputs the first driving signal through a first signal output terminal and the second driving signal through a second signal output terminal. The input of the first AND gate is connected to the first signal output of the processor, and the output of the first AND gate is connected to the delay module for outputting the first enhanced drive signal; The input of the second AND gate is connected to the second signal output of the processor, and the output of the second AND gate is connected to the delay module for outputting the second enhanced drive signal.

5. The IGBT protection circuit according to claim 4, characterized in that, The inverting module includes a first NOT gate and a second NOT gate; The input terminal of the first NOT gate is connected to the first signal output terminal of the processor, and the output terminal of the first NOT gate is connected to the interlock module for outputting the first reverse drive signal; The input of the second NOT gate is connected to the second signal output of the processor, and the output of the second NOT gate is connected to the interlock module for outputting the second inverted drive signal.

6. The IGBT protection circuit according to claim 2, characterized in that, The interlock module includes a third AND gate and a fourth AND gate; The input terminal of the third AND gate is connected to the signal output terminal of the second inverted drive signal of the inverting module and the signal output terminal of the first delayed drive signal of the delay module. The output terminal of the third AND gate is connected to the drive protection unit and is used to output the processed first drive signal. The input terminal of the fourth AND gate is connected to the signal output terminal of the first inverted drive signal of the inverting module and the signal output terminal of the second delayed drive signal of the delay module. The output terminal of the fourth AND gate is connected to the drive protection unit and is used to output the processed second drive signal.

7. The IGBT protection circuit according to claim 2, characterized in that, The drive protection unit includes a fifth AND gate and a sixth AND gate; The input terminal of the fifth AND gate is connected to the first signal output terminal of the fault detection unit and the signal output terminal of the processed first drive signal of the interlock module, and the output terminal of the fifth AND gate is connected to the gate of the IGBT upper transistor; wherein, the first signal output terminal of the fault detection unit is used to output a control signal characterizing the comparison relationship between the collector voltage of the IGBT upper transistor and the reference voltage. The input terminal of the sixth AND gate is connected to the second signal output terminal of the fault detection unit and the signal output terminal of the processed second drive signal of the interlock module. The output terminal of the sixth AND gate is connected to the gate of the lower IGBT. The second signal output terminal of the fault detection unit is used to output a control signal characterizing the comparison relationship between the collector voltage of the lower IGBT and the reference voltage.

8. The IGBT protection circuit according to any one of claims 1-7, characterized in that, The collector voltage includes the first collector voltage of the upper IGBT and the second collector voltage of the lower IGBT; the voltage detection unit includes a first detection module and a second detection module; the first detection module includes a fifth diode, a seventh resistor, an eighth resistor, a third capacitor, and a fourth capacitor; The first end of the seventh resistor is connected to the anode of the fifth diode and is connected to the collector of the IGBT via the eighth resistor. The second end of the seventh resistor and the first end of the fourth capacitor are connected to the output terminal of the first collector voltage of the first detection module. The cathode of the fifth diode is connected to the positive terminal of the power supply and the first terminal of the third capacitor, while the second terminal of the third capacitor and the second terminal of the fourth capacitor are grounded. The second detection module includes a sixth diode, a ninth resistor, a tenth resistor, a fifth capacitor, and a sixth capacitor; The first end of the ninth resistor is connected to the anode of the sixth diode and is connected to the collector of the lower IGBT via the tenth resistor. The second end of the ninth resistor and the first end of the sixth capacitor are connected to the output terminal of the second collector voltage of the second detection module. The cathode of the sixth diode is connected to the positive terminal of the power supply and the first terminal of the fifth capacitor, while the second terminal of the fifth capacitor and the second terminal of the sixth capacitor are grounded.

9. The IGBT protection circuit according to claim 8, characterized in that, The first detection module further includes a first switching transistor, and the second detection module further includes a second switching transistor; The drain of the first switching transistor is connected to the output terminal of the first collector voltage of the first detection module, the source of the first switching transistor is grounded, and the gate of the first switching transistor is used to input a detection control signal to control the conduction state of the first switching transistor. The drain of the second switching transistor is connected to the output terminal of the second collector voltage of the second detection module, the source of the second switching transistor is grounded, and the gate of the second switching transistor is used to input the detection control signal to control the conduction state of the second switching transistor.

10. The IGBT protection circuit according to claim 8, characterized in that, The fault detection unit includes a first comparator, a second comparator, a first filtering module, and a second filtering module; The first input terminal of the first comparator is used to input the reference voltage. The second input terminal of the first comparator is connected to the output terminal of the first collector voltage of the first detection module and is used to input the first collector voltage. The first control signal output by the output terminal of the first comparator is filtered by the first filtering module and then output to the drive protection unit. The first input terminal of the second comparator is used to input the reference voltage. The second input terminal of the second comparator is connected to the output terminal of the second collector voltage of the second detection module and is used to input the second collector voltage. The second control signal output by the output terminal of the second comparator is filtered by the second filtering module and then output to the drive protection unit. Wherein, the first control signal is at a low level when the first collector voltage is greater than the reference voltage, and the second control signal is at a low level when the second collector voltage is greater than the reference voltage.

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