A control circuit and a gated series capacitor

Abstract

The utility model relates to the technical field of gate control series capacitor, especially a control circuit and gate control series capacitor, including main control chip and superposition chip, the input of main control chip is connected with voltage mutual inductor and current transformer respectively, the first output of main control chip is connected with the first input of superposition chip, the second output of main control chip is connected with the second input of superposition chip. The utility model discloses through main control chip handles voltage, current signal simultaneously, and generates fundamental wave compensation instruction and damping compensation instruction respectively, then through superposition chip synthesis total control signal, realized the integration control of power scheduling and subsynchronous oscillation suppression. The system can maintain line power stability, and can also quickly respond and suppress subsynchronous oscillation, effectively promotes system stability.

Description

Technical Field

[0001] This utility model relates to the field of gated series capacitor technology, and in particular to a control circuit and a gated series capacitor. Background Technology

[0002] With the continuous increase in grid-connected wind power capacity, the sub-synchronous oscillation (SSO) problem caused by the interaction between wind farms and series-compensated transmission systems is becoming increasingly prominent.

[0003] Currently, the main methods for suppressing subsynchronous oscillations include installing a supplementary damping controller (SDC) on the wind turbine side or using flexible AC transmission system (FACTS) equipment on the grid side for compensation. However, modifying the wind turbine's own controller often involves coordination among multiple manufacturers, is costly, and difficult to implement. In contrast, using devices such as gate-controlled series capacitors (GCSCs) on the grid side for suppression has the advantages of flexible implementation and does not affect the original control of the wind turbine.

[0004] However, in existing technologies, when using GCSC+Power Scheduler (PSC) compensation, although GCSC provides dynamic compensation capabilities, PSC control using only GCSC cannot suppress SSO phenomena. PSC is mainly used for power dispatch and lacks targeted damping control for SSO modes. Utility Model Content

[0005] In this section, as well as in the abstract and title of this application, some simplifications or omissions may be made to avoid obscuring the purpose of this section, the abstract, and the title of this application. Such simplifications or omissions shall not be used to limit the scope of this utility model.

[0006] To address the shortcomings of existing technologies, one objective of this utility model is to provide a control circuit and a gated series capacitor.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a control circuit, comprising a main control chip and a superimposed chip; The input terminals of the main control chip are respectively connected to a voltage transformer and a current transformer; The first output terminal of the main control chip is connected to the first input terminal of the superimposed chip; The second output terminal of the main control chip is connected to the second input terminal of the superimposed chip.

[0008] In a preferred embodiment of the control circuit described in this utility model, the ADCINA0 pin of the main control chip is connected to the output terminal of the current transformer, the ADCINB0 and ADCINB1 pins of the main control chip are respectively connected to the output terminals of the voltage transformer and the current transformer, the DACOUTA pin of the main control chip is connected to the IN+ pin of the superimposed chip, and the DACOUTB pin of the main control chip is connected to the IN- pin of the superimposed chip.

[0009] In a preferred embodiment of the control circuit described in this utility model, the output terminal of the superimposed chip is connected to a limiting chip.

[0010] In a preferred embodiment of the control circuit described in this utility model, the REF pin of the limiting chip is connected to the OUT1 pin of the superimposed chip, and the CATHODE pin of the limiting chip is connected to the ADCINC0 pin of the main control chip.

[0011] In a preferred embodiment of the control circuit described in this utility model, the main control chip is connected to a lookup table chip via SPL communication.

[0012] In a preferred embodiment of the control circuit described in this utility model, the SPLSTE pin of the main control chip is connected to the CS pin of the lookup table chip, the SPLSIMO pin of the main control chip is connected to the DI pin of the lookup table chip, the SPLSOMI pin of the main control chip is connected to the DO pin of the lookup table chip, and the SPLCLK pin of the main control chip is connected to the CLK pin of the lookup table chip.

[0013] In a preferred embodiment of the control circuit described in this utility model, it further includes a driving unit, the input terminal of which is connected to the output terminal of the main control chip, and the output terminal of the driving unit is connected to a thyristor.

[0014] In a preferred embodiment of the control circuit described in this utility model, the driving unit includes a pulse chip and a driving chip; The TRIG pin of the pulse chip is connected to the GPIO pin of the main control chip, the OUT2 pin of the pulse chip is connected to the Anode pin of the driver chip, and the OUT3 and OUT4 pins of the driver chip are respectively connected to the gates of the two thyristors.

[0015] In a preferred embodiment of the control circuit described in this utility model, the VCC pin of the driver chip is connected to an isolated power supply.

[0016] A gated series capacitor includes a control circuit and a fixed capacitor. Two thyristors are connected in parallel in opposite directions across the two ends of the fixed capacitor. The output terminal of the control circuit is connected to the gate of the thyristors.

[0017] The beneficial effects of this invention are as follows: By simultaneously processing voltage and current signals through the main control chip and generating fundamental compensation and damping compensation commands respectively, and then synthesizing the overall control signal through a superposition chip, integrated control of power scheduling and subsynchronous oscillation suppression is achieved. This system can maintain stable line power while quickly responding to and suppressing subsynchronous oscillations, effectively improving system stability. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the connection of the main control chip of this utility model.

[0020] Figure 2 This is a schematic diagram of the connection of the control circuit of this utility model.

[0021] Figure 3 This is a schematic diagram of the connection of the thyristor of this utility model. Detailed Implementation

[0022] To enable those skilled in the art to better understand this utility model, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0023] The terminology used in this invention refers to those general terms currently widely used in the art in consideration of the functionality of this invention; however, these terms may vary according to the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this invention. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this invention.

[0024] Reference Figure 1 This embodiment provides a control circuit, including a main control chip 100 and a superimposed chip 200.

[0025] The input terminals of the main control chip 100 are connected to voltage transformer 101 and current transformer 102, respectively. The first output terminal of the main control chip 100 is connected to the first input terminal of the superimposed chip 200. The second output terminal of the main control chip 100 is connected to the second input terminal of the superimposed chip 200.

[0026] The main control chip 100 can be a TMS320F28379D.

[0027] The voltage transformer 101 is used to collect voltage signals from the power grid. Its output is connected to a specific analog-to-digital converter (ADC) input pin of the main control chip 100, such as the ADCINB0 pin, to convert the high-voltage signal into a small voltage signal that can be processed by the chip.

[0028] The current transformer 102 is used to collect current signals in the power grid. Its output is connected to another ADC input pin of the main control chip 100, such as the ADCINA0 pin or the ADCINB1 pin, to convert the large current signal into a small current or voltage signal that can be processed by the chip.

[0029] Voltage and current signals serve as a common raw input, simultaneously providing power dispatcher and subsynchronous resonant damping controller functional modules integrated within the main control chip 100.

[0030] The main control chip 100 internally processes and calculates the acquired voltage and current signals. The first output terminal of the main control chip 100, such as the DACOUTA pin, outputs the fundamental frequency compensation command signal. This signal is primarily used for power dispatching to adjust the fundamental impedance of the line. The second output terminal of the main control chip 100, such as the DACOUTB pin, outputs a damping compensation command signal. This signal is used to suppress subsynchronous oscillations and provide positive damping for the system.

[0031] Fundamental compensation command signal The damping compensation command signal is transmitted from the first output terminal of the main control chip 100 to the first input terminal of the superposition chip 200, such as the IN+ pin. The signal is transmitted to the second input terminal, such as the IN- pin, of the superimposed chip 200 via the second output terminal of the main control chip 100.

[0032] The superposition chip 200 is typically an adder or subtractor circuit composed of an operational amplifier that analog superimposes two input signals to generate a single overall control command signal. ,Right now This signal combines the needs of power control and oscillation suppression.

[0033] The ADCINA0 pin of the main control chip 100 is connected to the output terminal of the current transformer 102. The ADCINB0 and ADCINB1 pins of the main control chip 100 are connected to the output terminals of the voltage transformer 101 and the current transformer 102, respectively. The DACOUTA pin of the main control chip 100 is connected to the IN+ pin of the superimposed chip 200. The DACOUTB pin of the main control chip 100 is connected to the IN- pin of the superimposed chip 200.

[0034] Specifically, the first output terminal of the main control chip 100 is its DACOUTA pin. The analog voltage signal output by this pin is the fundamental frequency compensation command signal. This is the result of the calculation by the Power Scheduler (PSC) module. The PSC module calculates the instantaneous active power based on the collected voltage and current signals, and generates a fundamental compensation command to maintain stable line power through its internal proportional-integral (PI) control algorithm.

[0035] The second output terminal of the main control chip 100 is specifically its DACOUTB pin. This pin outputs an analog voltage signal, namely the damping compensation command signal. This is the calculation result of the Subsynchronous Resonant Damping Controller (SSRDC) functional module. The SSRDC module analyzes the subsynchronous frequency component in the current signal and multiplies it by a negative gain to generate a damping compensation command for suppressing subsynchronous oscillations.

[0036] The first input terminal IN+ of the overlay chip 200 receives the fundamental frequency compensation command signal from the PSC. Its second input terminal IN- receives the damping compensation command signal from the SSRDC. .

[0037] The superposition chip 200 combines the two instruction signals and outputs a total control command signal. .

[0038] During normal operation, the system exhibits no oscillation, and the SSRDC output is normal. Approximately equal to 0. The device is entirely controlled by the PSC and performs conventional series compensation.

[0039] When subsynchronous oscillation is detected, the SSRDC module quickly takes action and outputs an output. The signal, superimposed on the PSC command, dynamically modulates the total compensation command, thereby rapidly changing the equivalent capacitive reactance of the gated series capacitor, disrupting the resonance condition of the oscillation, and injecting positive damping into the system. This effectively solves the problem of the lack of damping control capability of the PSC in the original technology, and avoids the high cost and coordination difficulties caused by using multiple independent controllers.

[0040] Reference Figure 2The output terminal of the superimposed chip 200 is connected to the limiting chip 300.

[0041] The REF pin of the limiting chip 300 is connected to the OUT1 pin of the overlay chip 200, and the CATHODE pin of the limiting chip 300 is connected to the ADCINC0 pin of the main control chip 100.

[0042] The limiting chip 300 uses the programmable precision reference source Tl431.

[0043] Among them, the REF pin of the limiting chip 300 is the voltage reference input terminal, and the CATHODE pin of the limiting chip 300 is the cathode output terminal.

[0044] The output terminal OUT1 of the overlay chip 200 is directly connected to the REF pin of the limiting chip 300. This connection transmits the total control command signal output by the overlay chip. The data is sent to the input terminal of the TL431.

[0045] The CATHODE pin of the limiting chip 300 is connected to the ADCINC0 pin of the main control chip 100. This connection outputs the safety command signal after limiting to subsequent circuits, and at the same time feeds the signal back to the main control chip 100 for real-time monitoring and diagnosis.

[0046] When the superimposed chip 200 outputs the total control command signal When the voltage value is within the preset safety range, the voltage at the REF pin of the TL431 is insufficient to turn it on, resulting in a high impedance state between its CATHODE and ANODE pins. At this time, the limiting circuit does not function, and the voltage signal output from the CATHODE pin is incompatible with the overall control command signal. The signal passes through without loss, just like before.

[0047] master control command signal When the voltage value exceeds the preset safety range, the TL431 quickly turns on, thereby ensuring the output of the overall control command signal. They are always confined to a safe zone.

[0048] By setting the limiting chip 300, abnormal commands caused by control algorithm anomalies, signal interference, or system failures can be effectively prevented from being sent to subsequent drive circuits, thereby avoiding the thyristors of the gated series capacitor GCSC from operating in unsafe areas and protecting power equipment from damage.

[0049] The main control chip 100 is connected to the lookup table chip 400 via SPL communication.

[0050] The SPLSTE pin of the main control chip 100 is connected to the CS pin of the lookup table chip 400, the SPLSIMO pin of the main control chip 100 is connected to the DI pin of the lookup table chip 400, the SPLSOMI pin of the main control chip 100 is connected to the DO pin of the lookup table chip 400, and the SPLCLK pin of the main control chip 100 is connected to the CLK pin of the lookup table chip 400.

[0051] The lookup table chip 400 uses a serial flash memory chip, specifically the W25Q128. This chip interacts with the main control chip via the SPI communication protocol and pre-stores reactance command values ​​internally. Table of data relating to the thyristor turn-off angle γ.

[0052] The SPLSTE pin of the main control chip 100 is connected to the CS pin of the lookup table chip 400. This pin is used by the main control chip to initiate a communication session. When SPLSTE is low, the W25Q128 is selected and starts working.

[0053] The SPLCLK pin of the main control chip 100 is connected to the CLK pin of the lookup table chip 400. This pin provides the synchronization clock signal required for communication.

[0054] The SPLSIMO pin of the main control chip 100 is connected to the DI pin of the lookup table chip 400. The main control chip sends read commands and memory addresses to the lookup table chip through this pin.

[0055] The DO pin of the lookup table chip 400 is connected to the SPLSOMI pin of the main control chip 100. The lookup table chip 400 uses this pin to return the shutdown angle γ data stored at a specified address to the main control chip 100, thus achieving data lookup.

[0056] Reference Figure 2 The control circuit also includes a drive unit 500, the input terminal of which is connected to the output terminal of the main control chip 100, and the output terminal of the drive unit 500 is connected to a thyristor 600.

[0057] The drive unit 500 is a power interface circuit that connects the low-voltage control signal and the high-voltage execution component. It is used to convert the logic level signal generated by the main control chip 100 into a high-power pulse signal that can safely and reliably drive the thyristor 600.

[0058] The input terminal of the drive unit 500 is connected to the output terminal of the main control chip 100. This output terminal is used to output a pulse signal representing the turn-off angle γ. The output terminal of the drive unit 500 is connected to the gate G of the thyristor 600 to inject trigger current into the gate G.

[0059] The driving unit 500 includes a pulse chip 501 and a driving chip 502.

[0060] The TRIG pin of the pulse chip 501 is connected to the GPIO pin of the main control chip 100, the OUT2 pin of the pulse chip 501 is connected to the Anode pin of the driver chip 502, and the OUT3 and OUT4 pins of the driver chip 502 are connected to the gates G of the two thyristors 600 respectively.

[0061] The pulse chip 501 uses the NE555 timer circuit. Based on the trigger signal sent by the main control chip 100, the pulse chip 501 generates a logic pulse with a fixed width, high precision and synchronized with the power grid, which is used to determine the conduction angle of the thyristor 600.

[0062] The driver chip 502 uses an integrated optocoupler isolation driver, specifically the TLP250 model. It is used for electrical isolation and power amplification.

[0063] The GPI pin of the main control chip 100, such as the GPI0 pin, is connected to the TRIG pin of the pulse chip 501. The main control chip 100 triggers the operation of the NE555 by sending a low-level pulse to this pin. The timing of this low-level pulse (relative to the zero-crossing point of the power grid) is determined by the turn-off angle γ obtained from a lookup table.

[0064] The OUT2 pin of the pulse chip 501 is connected to the Anode pin of the driver chip 502. When the pulse chip 501 is triggered, the OUT2 pin of the NE555 will output a positive logic level pulse of preset width, which is used to drive the LED inside the TLP250.

[0065] The OUT3 pin of driver chip 502 is connected to the gate G of one thyristor 600. The OUT4 pin of driver chip 502 is connected to the gate G of another thyristor 600.

[0066] The VCC pin of the driver chip 502 is connected to an isolated power supply U.

[0067] The VCC pin of the driver chip 502 is connected to an isolated DC power supply, the ground of which is the same as the cathode of the thyristor 600, thereby ensuring electrical isolation between the drive side and the control side.

[0068] During operation, the main control chip 100 generates a narrow low-level trigger pulse on its GPIO pin based on the calculated turn-off angle γ. This pulse is sent to the TRIG pin of the NE555, triggering the pulse chip 501. The NE555's OUT2 pin then outputs a high-level pulse, the width of which is determined by the values ​​of the externally connected resistors and capacitors, ensuring that the pulse has sufficient width to reliably trigger the thyristor 600. This high-level pulse drives the LED inside the TLP250, causing it to emit a light signal. After the photosensitive element inside the TLP250 receives the light signal, the TLP250's OUT3 and OUT4 pins output drive pulses. These drive pulses are sent through very short leads to the gates G of the two anti-parallel thyristors 600, triggering them to conduct at precise moments.

[0069] A gated series capacitor includes a control circuit and a fixed capacitor 700. Two thyristors 600 are connected in parallel in opposite directions across the fixed capacitor 700. The output of the control circuit is connected to the gate G of the thyristors 600.

[0070] Among them, the capacitance value of the fixed capacitor 700 is fixed and is directly connected in series in the transmission line to provide a fixed capacitive impedance and compensate for the inductive reactance of the line.

[0071] The two thyristors 600 are turn-off thyristors GTO, which are connected in reverse parallel to form an AC switching valve group.

[0072] The final output terminals of the control circuit, namely the OUT3 and OUT4 pins of the driver chip 502, are connected to the gate G of the two thyristors 600, respectively, to provide them with precise trigger pulses.

[0073] When the control circuit does not send a trigger pulse to the thyristor 600, the thyristor valve group is in the off state. At this time, all the line current flows through the fixed capacitor 700. The device exhibits maximum capacitive impedance at this time, and its compensation effect on the line is strongest.

[0074] When the control circuit issues a trigger pulse after the grid current crosses zero, delayed by an angle (the turn-off angle γ), the thyristor 600 corresponding to the current direction is triggered to conduct. Once conducted, the current will flow through the thyristor 600 branch with extremely low impedance. At this time, the device presents minimum impedance, mainly the on-state impedance of the thyristor 600, and its compensation effect on the line is weakest.

[0075] By precisely controlling the triggering time of the thyristor, i.e., the turn-off angle γ, within each cycle, the duration for which the fixed capacitor 700 is connected to the circuit in each AC cycle can be changed. From a macroscopic perspective, the equivalent fundamental capacitive reactance of the entire device is continuously adjustable with the change in the turn-off angle γ. This achieves continuous, rapid, and stepless adjustment of the equivalent impedance. By adjusting the equivalent capacitive reactance in real time, reactive power can be quickly absorbed or generated, dynamically maintaining the stability of the transmission line voltage and improving system stability. The SSRDC function module in the control circuit can output [response information] when oscillation is detected. The command dynamically modulates the capacitive reactance value, injecting positive damping into the system and effectively suppressing subsynchronous oscillations.

[0076] Finally, it should be noted that the methods and devices described in detail above are merely embodiments, and those skilled in the art can modify these embodiments in different ways as long as they do not depart from the scope of this utility model.

Claims

1. A control circuit, characterized in that: It includes a main control chip (100) and a superimposed chip (200); The input terminals of the main control chip (100) are respectively connected to a voltage transformer (101) and a current transformer (102). The first output terminal of the main control chip (100) is connected to the first input terminal of the superimposed chip (200); The second output terminal of the main control chip (100) is connected to the second input terminal of the superimposed chip (200).

2. The control circuit as described in claim 1, characterized in that: The ADCINA0 pin of the main control chip (100) is connected to the output terminal of the current transformer (102). The ADCINB0 and ADCINB1 pins of the main control chip (100) are connected to the output terminals of the voltage transformer (101) and the current transformer (102) respectively. The DACOUTA pin of the main control chip (100) is connected to the IN+ pin of the superimposed chip (200). The DACOUTB pin of the main control chip (100) is connected to the IN- pin of the superimposed chip (200).

3. The control circuit as described in claim 1 or 2, characterized in that: The output terminal of the superimposed chip (200) is connected to the limiting chip (300).

4. The control circuit as described in claim 3, characterized in that: The REF pin of the limiting chip (300) is connected to the OUT1 pin of the superimposed chip (200), and the CATHODE pin of the limiting chip (300) is connected to the ADCINC0 pin of the main control chip (100).

5. The control circuit as described in any one of claims 1, 2, or 4, characterized in that: The main control chip (100) is connected to a lookup table chip (400) via SPL communication.

6. The control circuit as described in claim 5, characterized in that: The SPLSTE pin of the main control chip (100) is connected to the CS pin of the lookup table chip (400), the SPLSIMO pin of the main control chip (100) is connected to the DI pin of the lookup table chip (400), the SPLSOMI pin of the main control chip (100) is connected to the DO pin of the lookup table chip (400), and the SPLCLK pin of the main control chip (100) is connected to the CLK pin of the lookup table chip (400).

7. The control circuit as described in any one of claims 1, 2, 4 or 6, characterized in that: It also includes a drive unit (500), the input end of which is connected to the output end of the main control chip (100), and the output end of the drive unit (500) is connected to a thyristor (600).

8. The control circuit as described in claim 7, characterized in that: The driving unit (500) includes a pulse chip (501) and a driving chip (502). The TRIG pin of the pulse chip (501) is connected to the GPIO pin of the main control chip (100), the OUT2 pin of the pulse chip (501) is connected to the Anode pin of the driver chip (502), and the OUT3 and OUT4 pins of the driver chip (502) are respectively connected to the gates (G) of the two thyristors (600).

9. The control circuit as described in claim 8, characterized in that: The VCC pin of the driver chip (502) is connected to an isolated power supply (U).

10. A gated series capacitor, characterized in that: The system includes a control circuit and a fixed capacitor (700). Two thyristors (600) are connected in parallel in opposite directions across the fixed capacitor (700). The output of the control circuit is connected to the gate (G) of the thyristors (600).

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