A circuit for permanent magnet drive interlock function

Abstract

The utility model discloses a kind of for permanent magnet drive interlock function circuit, mainly solve the technical problem that the control level of existing permanent magnet drive circuit is uncertain in power-on or power-off moment, easy to cause IGBT bridge arm to be turned on simultaneously and cause device damage, the utility model is by being set in control input end by BS250 field effect tube, TLP250H photocoupler driver and the interlock circuit of multistage interlock resistance network composition, realize the hardware exclusion control between FZ,HZ signal, cooperate PESD24VL2BT transient suppression diode and the protection effect of RHRP30120 freewheeling diode, so that IGBT can keep safe cut-off or controlled conduction under any state;The utility model can effectively prevent misoperation, avoid bridge arm breakdown, improve the safety and reliability of permanent magnet circuit breaker drive system.

Description

Technical Field

[0001] This utility model relates to the field of power engineering technology, and more specifically to a circuit for interlocking function of permanent magnet drive. Background Technology

[0002] With the continuous improvement of power distribution automation, permanent magnet circuit breakers are widely used in feeder terminal equipment due to their advantages such as simple structure, low maintenance, and fast operation. Permanent magnet drive mechanisms achieve closing and opening by changing the direction of coil current, and have become the mainstream form of actuators in power distribution terminals.

[0003] Currently, most circuits used for permanent magnet drive control employ an H-bridge structure composed of four IGBTs. The controller outputs a signal to drive corresponding optocouplers, switching the current in both directions to complete the opening and closing operations of the permanent magnet mechanism. To prevent malfunctions during power-on, some devices set a default off state during software initialization or incorporate simple power-on reset protection in hardware. However, during the brief moment when the control signal level is not fully determined, there is still a risk that both upper and lower bridge arms may conduct simultaneously. If diagonal IGBTs conduct simultaneously, it will cause a shoot-through short circuit, damaging the devices and potentially causing power supply fluctuations, affecting the reliability of the entire feeder terminal system.

[0004] In existing technologies, logic interlocking or time-delayed driving methods are typically used to avoid this situation. However, these methods rely on software timing or signal synchronization, have high requirements for level stability, and poor anti-interference capabilities. Especially during power-on, power-off, or system reset processes, control signals are susceptible to interference. If the delay control is inaccurate or the level drifts, it will cause interlock failure, resulting in a short-term shoot-through of the H-bridge. In addition, some solutions have complex interlocking logic settings and slow response speeds, which are not conducive to achieving high-reliability field applications in power terminal equipment. Utility Model Content

[0005] The purpose of this invention is to design a circuit for interlocking function of permanent magnet drive, which improves the safety and reliability of system operation through multi-loop control with independent partitions, the addition of electrical isolation components and dual protection units.

[0006] To achieve the above-mentioned technical effects, the present invention adopts the following technical solution: A permanent magnet drive interlocking circuit includes first to fourth IGBT devices I1, I2, I3, and I4 constituting an H-bridge, wherein the two midpoints of the H-bridge are respectively used as the LQ+ and LQ− terminals of the permanent magnet coil LQ. It also includes first to fourth opto-isolators UG1, UG2, UG3, and UG4. The light-emitting side of the first to fourth opto-isolators is electrically connected to the output of the host drive controller, and the output of the receiving side is directly electrically connected to the gate of the corresponding IGBT. The system further includes third to sixth field-effect transistors Q3, Q4, Q5, and Q6. The drain of each field-effect transistor is electrically connected to an auxiliary DC +24V power supply, and the source is electrically connected to the third pin of the first to fourth opto-isolators UG1, UG2, UG3, and UG4, respectively. The gate of each field-effect transistor is electrically connected to two interlock control signals FZ and HZ, respectively. By turning the field-effect transistors on or off, the on / off control of the +24V power supply to the third pin of the opto-isolator is achieved.

[0007] As a further description of the above technical solution: the third to sixth field-effect transistors Q3, Q4, Q5, and Q6 are enhancement-mode N-channel field-effect transistors, and the drain of each field-effect transistor is connected to a protection element in parallel with the +24V power supply through a Schottky or fast recovery diode. The source of each field-effect transistor is connected to the third pin of the corresponding optocoupler, and a gate current limiting resistor and an RC hysteresis network are connected in parallel between the gate and source of each field-effect transistor.

[0008] As a further description of the above technical solution: the receiving side output terminals of the first to fourth opto-isolators UG1, UG2, UG3, and UG4 are provided with gate damping resistors and gate pull-down resistors connected in parallel with the corresponding IGBT gates. One end of the gate pull-down resistor is grounded and is used to pull the IGBT gate to the cutoff potential when there is no drive.

[0009] As a further description of the above technical solution: The H-bridge has a structure of two upper bridge arms and two lower bridge arms. The collectors / drains of the upper bridge arms I1 and I3 are connected to two DC positive terminals TC+ and HC+, respectively. The emitters / sources of the lower bridge arms I2 and I4 are connected to the negative terminal of the power supply or ground, respectively. The midpoints of the upper and lower bridge arms form the LQ+ and LQ- terminals of the permanent magnet coil LQ, respectively. A current sensing resistor and an overvoltage absorption element are connected in parallel between the main terminals of the IGBT as a matching protection unit.

[0010] As a further description of the above technical solution: an absorption circuit is connected in parallel across the two ends of the permanent magnet coil LQ. The absorption circuit consists of an RC absorption network and a reverse parallel diode. The absorption circuit is connected between LQ+, LQ− and the output node of the H bridge to suppress transient overvoltage during coil commutation and protect the IGBT device.

[0011] As a further description of the above technical solution: the interlock control signals FZ and HZ are electrically connected to the upper controller via an electrostatic suppression circuit, and the gates of the field-effect transistors Q3, Q4, Q5, and Q6 are connected to the power supply or ground via pull-up or pull-down resistors, and the values ​​of the pull-up / pull-down resistors are matched with the gate capacitance of the optocoupler and the field-effect transistor.

[0012] As a further description of the above technical solution: the light-emitting side and the receiving side of the opto-isolators UG1, UG2, UG3 and UG4 are respectively reserved with test points and connected in parallel with detection resistors. This detection circuit is electrically connected to the external fault indication unit.

[0013] In summary, due to the adoption of the above technical solution, the beneficial effects of this utility model are as follows: By adding an interlock circuit to the H-bridge drive end, this utility model forms a hardware interlock relationship between the optocoupler drive end and the field-effect transistor. Through the logical combination of control signals FZ and HZ, the optocoupler's conduction or cutoff selection is automatically realized, allowing only one set of diagonal IGBTs to conduct at any given time, and causing all optocouplers to enter the cutoff state when both signals are at a high level, fundamentally eliminating the shoot-through risk caused by level uncertainty. This solution does not rely on software timing control and can maintain the IGBT in a safe state at any stage of power-on, power-off, and system reset, avoiding circuit short circuits and device damage. Since the interlock relationship is established at the hardware level, the response speed is fast, the anti-interference ability is strong, ensuring the stable operation of the permanent magnet drive circuit, improving the reliability of the circuit breaker operating mechanism control and the overall safety of the equipment. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a circuit principle framework diagram of this utility model. Detailed Implementation

[0015] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] First, a detailed explanation of the circuit's principle will be provided; please refer to [link / reference needed]. Figure 1The circuit schematic is shown below. This circuit is centered around a driver module with hardware interlocking and power-on protection features. Structurally, the entire module consists of four main power switches, four optocoupler drive units, several MOSFETs, and peripheral current-limiting, protection, absorption, and testing components. The target of the drive is the coil of a permanent magnet actuator, requiring the provision of high-current pulses in both forward and reverse directions within an extremely short time to achieve closing and opening actions, while ensuring that no bridge arm shoot-through or false triggering occurs under any conditions. Because the characteristics of the permanent magnet actuator dictate that the coil retains its state after power-off, the drive circuit is only energized for a brief moment during operation, with the entire process measured in milliseconds. This places extremely high demands on the reliability and response speed of the switching devices.

[0017] The main circuit uses four G160N60 IGBTs, forming a typical full-bridge topology. Two upper bridge arms and two lower bridge arms have positive and negative buses from the +220V and -220V terminals of the control power supply, respectively. The midpoint of each bridge arm is connected to both ends of the permanent magnet coil. By controlling the switching combinations of the four IGBTs, a positive or reverse voltage can be generated on the LQ coil, achieving closing or opening of the circuit. This part of the H-bridge is almost devoid of any fancy features; the focus is entirely on control and protection. Because even a momentary erroneous conduction of the upper or lower bridge arms can lead to a momentary short circuit in the power supply, such a fault in a permanent magnet system often means the failure of the entire power board. Therefore, the design philosophy is "prevent it from failing first, then consider how to make it move quickly."

[0018] Each IGBT's gate is isolated by a TLP250H optocoupler driver. The four optocouplers are labeled UG1 to UG4, corresponding to I1 to I4 IGBTs. The light-emitting terminals of the optocouplers are directly driven by the logic signal output from the host control board. A current-limiting resistor is connected in series on the input side, and an anti-reverse parallel diode is also connected to prevent backflow of the control signal. The optocoupler output side drives the IGBT gate, with a small-value damping resistor connected in series on the gate and a pull-down resistor in parallel. This is to ensure that the gate voltage is quickly pulled to the emitter potential when the optocoupler is turned off, preventing it from floating. The reason for choosing the TLP250H is simple: it has a certain drive current capability and a short power-on recovery time, making it suitable for applications requiring instantaneous action and isolation.

[0019] The interlocking is implemented using a set of P-channel MOSFETs, specifically the BS250. A total of six BS250s are used, four of which are the main components directly involved in the interlocking, and the other two are auxiliary components for signal toggling or state holding. The source of each BS250 is connected to a +24V auxiliary power supply, and its drain is connected to the power supply pin (pin 3) of its respective optocoupler. When a BS250 is turned on, its corresponding optocoupler receives power and can respond to signals from the host controller; conversely, when a BS250 is turned off, regardless of the host controller's output, the corresponding IGBT will not activate. This method allows for hardware-level determination of which optocouplers are allowed to operate.

[0020] The two interlock signals, FZ and HZ, are connected to the gates of these BS250s through a network of resistors. Through logical combinations, when FZ is high, only UG1 and UG4 are energized; when HZ is high, only UG2 and UG3 are energized; and when both are high or both are low, all BS250s remain off. No matter how chaotic the control logic becomes, the upper and lower bridge arms cannot conduct simultaneously. The entire interlock logic is not determined by software; it is handled entirely at the analog circuit level, and all are in a completely off state at the moment of power-on. In power grid equipment, the power-on sequence of the control board and power board is sometimes unstable, and the software initialization delay is sometimes slower than the power-on delay. If the interlock is determined by program logic, even a momentary spike could trigger a catastrophic short circuit.

[0021] Furthermore, to ensure signal integrity in harsh electromagnetic environments, small transient suppression diodes (PSDs) such as the PESD24VL2BT are connected in parallel at the FZ and HZ input terminals. These diodes have a fast response time and can limit sudden high-voltage pulses to below 24V, protecting the MOSFET gate from breakdown. This protection is essential considering that interlock signals are sometimes drawn from a distant control board. Additionally, an RC snubber network is added between each optocoupler output and the IGBT gate to suppress self-oscillation and false turn-on at high dv / dt. This portion of the resistors is substantial, constituting a significant portion of the 27 resistors.

[0022] In the main power circuit, in addition to the IGBT itself, RHRP30120 fast recovery diodes are connected in parallel. These diodes are connected across the upper and lower nodes of the bridge arm, forming an anti-parallel circuit. This is mainly used to provide a return current path during commutation or turn-off, preventing the inductance of the coil from damaging the IGBT. Because the permanent magnet coil stores a significant amount of energy, the current does not immediately disappear upon disconnection. Without a sufficiently fast freewheeling path, the voltage will surge. The RHRP30120 has excellent reverse recovery characteristics, allowing it to take over the current within tens of nanoseconds, and then release the energy in conjunction with the main capacitor or snubber resistor. An RC snubber network is also connected in parallel across the coil terminals to suppress voltage spikes and reduce electromagnetic interference to the system during sudden changes in coil current.

[0023] When the system is powered on, +24V is established first. The gate of the BS250 naturally enters a safe state through pull-up and voltage divider resistors, cutting off all MOSFETs and thus disabling all optocouplers. Even if the host control board is not yet ready or the signal ports are in an uncertain state, no IGBTs will receive power at this time. Only when the control logic confirms the system state and issues a clear FZ or HZ enable signal will the BS250 be biased into the conducting state, and the corresponding optocouplers will receive power. This action is controlled in hardware by an RC delay formed by the gate resistor and capacitor, with a delay of only a few milliseconds, sufficient to avoid power-on glitches. During this process, the IGBT gate remains close to the emitter potential due to the pull-down resistor, eliminating the possibility of floating conduction. A natural protective gap is formed between the system's power-on state and its operational state, a practice highly practical in power electronic devices.

[0024] To facilitate maintenance and debugging, test points are reserved on the input and output sides of the optocoupler, as well as around the gate of the MOSFET. For example, a small resistor of about 100Ω is connected in series in the LED circuit of UG1, and TP1 is led out from both ends. By measuring the voltage at this point when the circuit is powered on, it can be determined whether the LED is working properly. A similar TP is also provided on the MOSFET side to confirm whether the interlock signal is transmitted in place and whether the BS250 is conducting properly. All test points are isolated by high-value resistors to ensure that the testing will not interfere with the circuit operation. These details are very useful in the actual debugging stage, especially when the circuit cannot be closed but no problem can be found in the field. It can quickly locate whether the interlock is not released or the optocoupler is damaged.

[0025] In addition to TVS diodes and snubber diodes, the protection system also includes current sampling resistors for the main power supply circuit. These resistors are connected in series at the power input to monitor instantaneous current or trigger external overcurrent protection units. Generally, high-power metal film resistors or manganese-copper shunts are selected, with resistance values ​​in the milliohm range. The external monitoring module detects this voltage drop to determine if a bridge arm short circuit or coil fault has occurred. During normal operation, the current waveform is very sharp but short-lasting, while during a short circuit, the current duration is long and the amplitude is extremely high, making it easy to distinguish.

[0026] The entire module is structurally designed as a single, independent power board, with power and control signals connected via foolproof sockets. The H-bridge and control sections are arranged in layers, separated by a grounded shielding layer. IGBTs are mounted on heatsinks, while optocouplers and MOSFETs are concentrated in the control area on one side. This layout separates high-voltage and low-voltage circuits, reducing interference and facilitating replacement. The four IGBTs are positioned as close as possible to the coil output terminals to minimize the current loop area. RHRP30120 fast recovery diodes are mounted near the IGBTs, connected using short copper foil to reduce parasitic inductance. The PESD24VL2BT, due to its small size and low heat generation, can be directly mounted near the signal interface. All grounding wires use a single-point bus to the power ground, avoiding interference loops between the control ground and power ground.

[0027] The driver module designed in this way can reliably enter a safe state during power-on testing. Even if the control board is completely powered off or the signal cable is disconnected, the H-bridge will not conduct. The corresponding optocoupler driver will only be unlocked when the interlock signal explicitly specifies the "allow opening" or "allow closing" state. This hardware-based interlock is much safer than the traditional method that relies on a microcontroller. An engineering experiment was conducted: the control signal terminals were simultaneously pulled high and then suddenly powered off and back on; the module remained in the off state throughout, without a single instance of false turn-on. For equipment like power distribution terminals that are unattended for extended periods, this design effectively eliminates the risk of short circuits at its source.

[0028] like Figure 1In the circuit, the FZ and HZ signal inputs are each divided into several branches after passing through current-limiting resistors, and each branch is connected to the gate control terminal of a different BS250. Taking the FZ path as an example, when FZ is pulled high, the gate potential of the corresponding MOSFET decreases, and the source and drain are connected. The 24V voltage is transmitted through the drain to the third pin of UG1 and UG4 to power their drive. At the same time, the gate potential of the MOSFET connected to the HZ channel is pulled up to close to 24V by the resistor network, keeping it off, thus disconnecting the power path of UG2 and UG3. In this way, through the complementary control of the two sets of signals, a hardware-level electrical interlock relationship is formed. Conversely, when HZ is high and FZ is low, the circuit logic automatically reverses, allowing only UG2 and UG3 to be powered. If both are high or low at the same time, all MOSFETs are off, and the optocoupler drive power supply is completely cut off. In the diagram, the four field-effect transistors Q3, Q4, Q5, and Q6 together form a cross-interlock unit. Their sources are connected to +24V, their drains are connected to the power supply terminals of each optocoupler, and their gates are connected by voltage divider resistors to ensure a stable interlock state during signal transitions.

[0029] During implementation, the system control logic first outputs an FZ or HZ signal based on the external command status. When the FZ terminal is pulled high, the signal connected to this terminal is sent to the level distribution network of the preceding stage through a current-limiting resistor, biasing the corresponding BS250 gate, so that the channels containing UG1 and UG4 receive a 24V power supply. At this time, UG2 and UG3 are in a de-energized state because their corresponding field-effect transistors are cut off. As UG1 and UG4 are turned on, the gates of I1 and I4 are driven, and the current flows from DC+ through I1 to the LQ+ terminal of the permanent magnet coil, and then from the LQ− terminal back to the power supply ground through I4, forming a positive voltage across the permanent magnet coil. The magnetic field inside the coil is directed from left to right, forming an attractive and repulsive force with the magnetization direction of the permanent magnet core, causing the armature to move to the left to complete the opening action. The entire process is extremely short, and the drive current is cut off after milliseconds.

[0030] When closing is required, the control terminal pulls the HZ signal high and simultaneously pulls the FZ signal low. At this time, UG2 and UG3 receive drive power, while UG1 and UG4 are de-energized. The gates of I2 and I3 are triggered sequentially, and the current flows through the coil in the opposite direction, from LQ− to LQ+, reversing the magnetic field direction. The armature is then forced to the right to complete the closing action. Throughout the process, because the two sets of optocoupler drive power supplies are completely interlocked, there is no path for simultaneous conduction. Even if the control signals overlap briefly, the series connection between the BS250 MOSFETs still ensures that only one set receives operating voltage at any given time.

[0031] To prevent excessive reverse voltage caused by current pulses during turn-off, RHRP30120 fast recovery diodes are connected in parallel across the permanent magnet coil. These diodes are paired with the current flow path in both directions, allowing the back electromotive force generated during current cut-off to be released through the diode circuit, preventing breakdown of the IGBT's collector-emitter junction. Each diode has a 1200V reverse voltage capability, effectively covering the coil's induced voltage. The circuit also includes a suitable damping network, typically composed of a series resistor and capacitor, to absorb any remaining spike energy. To suppress high-frequency oscillations, a small capacitor is connected between the IGBT's gate and emitter to filter out dv / dt interference. These designs result in a smoother transient response during switching and reduce electromagnetic interference to other electronic modules.

[0032] In the optocoupler driving section, each TLP250H output is equipped with an independent power supply decoupling capacitor, typically ranging from 0.1μF to 1μF, to maintain the stability of the gate drive current. Because the TLP250H has an internal push-pull output structure, insufficient power supply stability can easily lead to a brief undervoltage state during turn-off. Connecting a capacitor in parallel at its power supply effectively prevents this voltage sag from causing false triggering. In addition to a series current-limiting resistor, each optocoupler input also has a reverse-parallel diode connected in parallel to absorb the inductive flyback voltage at the input, protecting the LED from impact. Along the entire path of the drive signal from the host computer output to the optocoupler input, several voltage divider resistors are also present. These resistors primarily serve a level matching function, ensuring that the logic voltage remains within the optocoupler's allowable range.

[0033] In the interlock control circuit, the source of each BS250 is connected to a +24V power supply, and the drain is connected to the corresponding optocoupler driver power supply, with a current-limiting resistor of several tens of ohms in series in between. The gate receives the FZ and HZ signals through a network of voltage divider resistors. Some gates are also cross-connected with other BS250 gates to form an interlock relationship. For example, when FZ is high, the control network pulls the gate potential of the MOSFET connected to the HZ channel high to near the source, keeping it off; while the gate potential of the MOSFET connected to the FZ channel is pulled down, making it conduct, thus forming a complementary relationship of one group locked and one group conducting. When FZ and HZ are both high, all BS250 gates are close to the source potential and are all off. At this time, all four optocoupler drivers lose power, and the entire H-bridge is in a fully locked state. If an external signal line fails or the control power supply fails at this time, the circuit can still maintain this state and will not short-circuit.

[0034] To ensure the reliability of the BS250's switching between on and off states, its gate is also equipped with pull-up and pull-down resistors, forming a fixed static bias point. Under long-line interference or lightning strikes, the bias network prevents the MOSFET from malfunctioning. Simultaneously, the PESD24VL2BT transient voltage suppressor diodes added at the FZ and HZ input terminals provide additional protection. When the input voltage exceeds 24V, they quickly turn on, dissipating excessive energy to ground, thus preventing the BS250 gate from breaking down.

[0035] An absorption capacitor and a small-value resistor are arranged between the center node of the H-bridge and the permanent magnet coil, forming an RC snubber network to reduce voltage spikes during switching. A small capacitor is also connected in parallel to each IGBT, limiting the voltage rise rate during high-speed turn-off, thereby reducing electromagnetic radiation and stress. Because the G160N60 IGBT itself has strong voltage and current withstand capabilities, some energy remains during the reverse recovery phase. The external absorption network allows this energy to be recovered smoothly. This significantly reduces device temperature rise during repeated operation and extends device lifespan.

[0036] It should be noted that the twenty-seven resistors distributed throughout the circuit not only serve a current-limiting function but also undertake multiple tasks such as level isolation, biasing, and discharging. For example, the pull-down resistor at the optocoupler output allows the IGBT to quickly release its gate charge when the optocoupler is turned off; the voltage divider resistors in the interlock network are used to stabilize the gate potential of the MOSFET; and the resistors at the input signal terminals, together with the TVS diode, form a protection network. The entire circuit was designed with full consideration of the interactions between these resistors, ensuring that the signal speed is not affected while maintaining a reasonable time constant.

[0037] In actual operation, when the control system issues a closing command, the HZ terminal signal is first set high, turning on the UG2 and UG3 drive power supplies via the MOSFET network. After approximately 1-2 ms, the optocoupler output begins charging the IGBT gate, turning it on. Simultaneously, the FZ channel remains completely de-energized due to hardware interlocking. Current flows in the H-bridge, forming a positive voltage across the coil. After the closing action is completed, the control signal is removed, the optocoupler turns off, and the IGBT is cut off. Because the optocoupler turns off extremely quickly, the gate voltage is rapidly discharged by the pull-down resistor, preventing residual charge from causing a slow turn-off. Residual current energy is released through the anti-parallel diode and RC snubber circuit, ensuring a smooth circuit. The opening process is completely symmetrical, except that the signal and current directions are reversed.

[0038] During power-on and power-off, when an external 24V power supply is connected, all MOSFETs are cut off because the BS250 gate potential is in a pull-up state by default, so there is no output from the optocoupler drive power supply. Even if glitches occur at the control board signal terminals, they will not affect the IGBT gate. The MOSFETs in the corresponding channels only begin to conduct after the control system is fully initialized and sends a valid signal. Conversely, when the system is powered off, the auxiliary power supply voltage drop first turns off the BS250, thus cutting off the optocoupler drive power supply in advance and causing the IGBT to turn off early, avoiding a semi-conducting state during the power decay phase. This logic of cutting off the drive first and then the main power is inherently determined by the circuit and does not require software intervention.

[0039] In implementation, the circuit module was designed with heat dissipation and electromagnetic compatibility in mind. The G160N60 IGBT and RHRP30120 diodes are mounted on the same heatsink, connected via thermal grease to form a compact thermal path. Optocouplers, MOSFETs, and signal circuits are concentrated on the control side, using a multi-layer PCB with a grounded copper shield between the signal and power layers. This prevents electromagnetic interference generated during IGBT high-frequency switching from coupling to the control coil. All ground lines are star-connected to ensure that signal ground and power ground have only one point of convergence, avoiding interference caused by ground loop current.

[0040] After assembly, the entire circuit can be directly installed in the feeder terminal module of power distribution automation equipment and connected to the main control unit via a multi-core connector. The interface includes two interlock signal input terminals (FZ and HZ), a +24V auxiliary power input, a ±220V main power input, and a coil output terminal. The module casing is metal-shielded and properly grounded to resist external electromagnetic interference. During operation, the module can perform the corresponding actions according to the interlock logic as long as a command is issued by the host computer.

[0041] While specific embodiments of this utility model have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of this utility model. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of this utility model. Therefore, the scope of this utility model is defined only by the appended claims.

Claims

1. A circuit for interlocking function in permanent magnet drive, characterized in that, The first to fourth IGBT devices I1, I2, I3, and I4 that constitute the H-bridge are included, and the two midpoints of the H-bridge are respectively used as the LQ+ and LQ− terminals of the permanent magnet coil LQ for output. It also includes first to fourth opto-isolators UG1, UG2, UG3, and UG4. The light-emitting side of the first to fourth opto-isolators is electrically connected to the output of the host drive controller, and the output of the receiving side is directly electrically connected to the gate of the corresponding IGBT. The system further includes third to sixth field-effect transistors Q3, Q4, Q5, and Q6. The drain of each field-effect transistor is electrically connected to an auxiliary DC +24V power supply, and the source is electrically connected to the third pin of the first to fourth opto-isolators UG1, UG2, UG3, and UG4, respectively. The gate of each field-effect transistor is electrically connected to two interlock control signals FZ and HZ, respectively. By turning the field-effect transistors on or off, the on / off control of the +24V power supply to the third pin of the opto-isolator is achieved.

2. The circuit for permanent magnet drive interlock function according to claim 1, characterized in that: The third to sixth field-effect transistors Q3, Q4, Q5, and Q6 are enhancement-mode N-channel field-effect transistors. The drain of each field-effect transistor is connected to a protection element in parallel with the +24V power supply through a Schottky or fast recovery diode. The source of each field-effect transistor is connected to the third pin of the corresponding optocoupler. A gate current limiting resistor and an RC hysteresis network are connected in parallel between the gate and source of each field-effect transistor.

3. The circuit for permanent magnet drive interlock function according to claim 1, characterized in that: The first to fourth opto-isolators UG1, UG2, UG3, and UG4 are provided with gate damping resistors and gate pull-down resistors connected in parallel between the receiving side output terminals and the corresponding IGBT gates. One end of the gate pull-down resistor is grounded and is used to pull the IGBT gate to the cutoff potential when there is no drive.

4. A circuit for interlocking function of permanent magnet drive according to claim 1, characterized in that: The H-bridge has a structure of two upper bridge arms and two lower bridge arms. The collectors / drains of the upper bridge arms I1 and I3 are connected to two DC positive terminals TC+ and HC+, respectively. The emitters / sources of the lower bridge arms I2 and I4 are connected to the negative terminal of the power supply or ground, respectively. The midpoints of the upper and lower bridge arms form the LQ+ and LQ- terminals of the permanent magnet coil LQ, respectively. A current sensing resistor and an overvoltage absorption element are connected in parallel between the main terminals of the IGBT as a matching protection unit.

5. A permanent magnet drive interlock circuit according to claim 1, characterized in that: An absorption circuit is connected in parallel across the two ends of the permanent magnet coil LQ. The absorption circuit consists of an RC absorption network and a reverse parallel diode. The absorption circuit is connected between LQ+, LQ− and the output node of the H bridge to suppress transient overvoltage during coil commutation and protect the IGBT device.

6. A permanent magnet drive interlock circuit according to claim 1, characterized in that: The interlock control signals FZ and HZ are electrically connected to the host controller via an electrostatic suppression circuit, and the gates of the field-effect transistors Q3, Q4, Q5, and Q6 are connected to the power supply or ground via pull-up or pull-down resistors, with the pull-up / pull-down resistor values ​​matched to the gate capacitance of the optocoupler and the field-effect transistors.

7. A circuit for interlocking function of permanent magnet drive according to claim 1, characterized in that: The opto-isolators UG1, UG2, UG3, and UG4 have reserved test points on their light-emitting and receiving sides, and a detection resistor is connected in parallel. The detection circuit formed by the test points and the detection resistor is electrically connected to the external fault indication unit.

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