High voltage power supply circuit for a phased array ultrasound instrument and phased array ultrasound instrument

Abstract

The utility model provides a kind of high voltage power supply circuit and phased array ultrasonic instrument for phased array ultrasonic instrument, it is related to integrated circuit field.The input end of positive polarity main power circuit is connected with the output end of digital regulation feedback circuit;The input end of digital regulation feedback circuit is connected with host computer;Part structure in positive polarity main power circuit is multiplexed as its input end by negative polarity mirror circuit;The output end of positive polarity main power circuit, negative polarity mirror circuit is connected with load all.The high voltage power supply circuit of the utility model can output +23V to +100V and-23V to-100V positive and negative high voltage to load, with low ripple, high conversion efficiency and compact PCB layout, low EMI and other characteristics, meet phased array ultrasonic 64 channel probe drive demand.Through hybrid topology innovation and digital regulation technology, break through traditional high voltage power supply efficiency, volume, noise bottleneck, as new power module, can be widely used in industrial phased array high voltage power supply or medical phased array high voltage power supply field.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuits, and in particular to a high-voltage power supply circuit for a phased array ultrasonic instrument and a phased array ultrasonic instrument. Background Technology

[0002] Current phased array ultrasonic instruments use controllers with low efficiency (typically <85%) and poor cross-regulation (voltage deviation >5% under ±5% load fluctuation); moreover, most adopt Buck+Boost schemes, while in traditional Buck+Boost schemes, bipolar power supplies require independent positive and negative power supply modules, resulting in an increase of more than 40% in core cost; and the conventional LC filter used in them has residual ripple >50mVpp at a 100kHz switching frequency, which will interfere with the sampling of ultrasonic echo signals.

[0003] In addition, a few use mechanical potentiometers to adjust the voltage, which has low voltage adjustment accuracy (1% step) and cannot be remotely programmed via SPI to achieve precise control of multiple levels. Summary of the Invention

[0004] In view of the above problems, the present invention aims to provide a high-voltage power supply circuit for a phased array ultrasonic instrument and a phased array ultrasonic instrument that overcomes or at least partially solves the above problems.

[0005] In a first aspect, embodiments of the present invention provide a power-off circuit for a phased array ultrasonic instrument, comprising: Positive polarity main power circuit, negative polarity mirror circuit, digital adjustment feedback circuit; The input terminal of the positive polarity main power circuit is connected to the output terminal of the digital adjustment feedback circuit; the input terminal of the digital adjustment feedback circuit is connected to the host computer; the negative polarity mirror circuit reuses part of the structure in the positive polarity main power circuit as its input terminal; the output terminals of the positive polarity main power circuit and the negative polarity mirror circuit are both connected to the digital adjustment feedback circuit and the load respectively. The digital adjustment feedback circuit is configured to acquire the output voltage of the positive polarity main power circuit or the negative polarity mirror circuit and feed it back to the control chip in the positive polarity main power circuit, and set the target value of the output terminal resistance based on the instruction sent by the host computer. The range of the settable target value is 2.15K~10K. The positive polarity main power circuit is configured to positively boost the 12V input voltage in combination with the target value of the output terminal resistor and the voltage fed back by the digital adjustment feedback circuit, and output a target positive voltage to the load. The target positive voltage range of the output is +23V to +100V. The negative polarity mirror circuit is configured to perform a negative boost on the 12V input voltage, combined with the target value of the output terminal resistor and the voltage fed back by the digital adjustment feedback circuit, and output a target negative voltage to the load. The target negative voltage range of the output is -23V to -100V.

[0006] Optionally, the positive polarity main power circuit includes: The control chip has a VIN pin that receives a 12V input voltage through an input resistor, a SENSE pin that is connected to the source of the control MOS transistor, the first end of the first grounding resistor, and the first end of the frequency suppression resistor, and a GATE pin that is connected to the gate of the control MOS transistor. The second end of the first grounding resistor is connected to the first end of the second grounding resistor, and the second end of the second grounding resistor is grounded. The second end of the frequency suppression resistor is connected to the first end of the frequency suppression capacitor, and the second end of the frequency suppression capacitor is connected to the drain of the control MOS transistor, the primary winding of the coupling inductor, and the first end of the first transmission capacitor, respectively. The second terminal of the first transmission capacitor is connected to the secondary side coil of the coupling inductor and the anode of the first diode, respectively. The cathode of the first diode is connected in parallel with a filter capacitor bank and then connected to the digital adjustment feedback circuit. The cathode of the first diode is also connected to the first terminal of the first output inductor through a resistor and is connected in parallel with another filter capacitor bank. The second terminal of the first output inductor outputs the target positive voltage. All parallel filter capacitor banks must be grounded.

[0007] Optionally, the negative polarity mirror circuit shares the control chip, the control MOSFET, and the coupling inductor in the positive polarity main power circuit, and the connection relationships between the control chip and the control MOSFET, and between the control MOSFET and the coupling inductor are also the same; The negative polarity mirror circuit also includes: The first end of the second transmission capacitor is connected to the drain of the control MOS transistor, the second end of the frequency suppression capacitor, and the primary winding of the coupling inductor, respectively. The second terminal of the second transmission capacitor is connected to the secondary side coil of the coupled inductor and the anode of the second diode, respectively. The cathode of the second diode is grounded; The secondary coil of the coupled inductor is connected in parallel with a filter capacitor bank and then connected to the digital adjustment feedback circuit. The secondary coil of the coupled inductor is also connected to the first end of the second output inductor through a resistor and in parallel with another filter capacitor bank. The second end of the second output inductor outputs the target negative voltage. All parallel filter capacitor banks must be grounded.

[0008] Optionally, the digital adjustment feedback circuit includes: A dual-channel digital potentiometer that receives SPI commands from a host computer via the CS#, SCK, SI, and SO pins. These SPI commands are used to set the resistance value of the output terminal, which ranges from 2.15KΩ to 10KΩ. The PW0 pin of the dual-channel digital potentiometer is connected to the positive polarity main power circuit and the negative polarity mirror circuit respectively through a voltage divider structure.

[0009] Optionally, the digital adjustment feedback circuit further includes an enable control circuit; The enable control circuit includes: a switching MOSFET; The source of the MOSFET receives a 12V input voltage and is connected to its gate through a resistor. The gate of the MOSFET is connected to the collector of the transistor, and the base of the transistor is connected to the external FPGA through a voltage divider resistor to receive control signals sent by the FPGA. The emitter of the transistor is grounded. A voltage-regulating capacitor is connected in parallel to the drain of the MOSFET and is connected to the positive main power circuit and the negative mirror circuit respectively, outputting a 12V input voltage to both.

[0010] Optionally, the MODE pin of the control chip is connected to the INTVCC pin; The control chip is configured in synchronous SEPIC mode, i.e., synchronous pulse skipping mode.

[0011] Optionally, the coupling inductor is a six-winding coupling inductor, using a transformer winding configuration.

[0012] Optionally, the voltage divider structure includes: a first voltage divider resistor, a second voltage divider resistor, and a third voltage divider resistor; The first end of the first voltage divider resistor is connected to the PWO pin, and the second end is connected to the FB pin of the control chip, the first end of the second voltage divider resistor, and the first end of the grounding capacitor. The second end of the grounding capacitor is grounded. The first terminal of the second voltage divider resistor also receives an external direct voltage, which is 1.23V. The second end of the second voltage divider resistor is connected to the first end of the third voltage divider resistor, and the second end of the third voltage divider resistor is connected to the positive polarity main power circuit and the negative polarity mirror circuit, respectively.

[0013] Optionally, the control chip is model LTC1871; The control MOSFET is an N-MOSFET, model APM4953, with parameters of 80V / 20A and Rds=0.1Ω. The duty cycle of the GATE pin is set to a range of 50%~80%. The coupling inductor is model VPH4-0860-R with an inductance of 159μH; The parallel filter capacitor bank includes: a multilayer ceramic capacitor, model 250V X7R, with a capacitance of 2.2μF; and a high-voltage aluminum electrolytic capacitor, model UUJ2C330MNQ1MS, with parameters of 33μF / 160V, 12.5*13.5, and 95mA@120Hz. Both the first output inductor and the second output inductor are integrally molded alloy power inductors, which, together with their respective connected filter capacitor banks, form a second-order filter network with parameters of 30 ohm @ 100 MHz / 3A. The frequency suppression resistor and the frequency suppression capacitor form an RC snubber circuit with parameters of 10Ω / 1W+1nF / 1kV. The first grounding resistor and the second grounding resistor are both model WSL2512R0220FEA, and their resistance values ​​are both 0.44Ω.

[0014] Secondly, embodiments of the present invention provide a phased array ultrasonic instrument, the phased array ultrasonic instrument including a high-voltage power supply circuit for a phased array ultrasonic instrument as described in any of the first aspects.

[0015] The high-voltage power supply circuit for a phased-array ultrasonic instrument of this invention includes: a positive polarity main power circuit, a negative polarity mirror circuit, and a digital adjustment feedback circuit. The input terminal of the positive polarity main power circuit is connected to the output terminal of the digital adjustment feedback circuit; the input terminal of the digital adjustment feedback circuit is connected to a host computer; the negative polarity mirror circuit reuses part of the structure of the positive polarity main power circuit as its input terminal; the output terminals of both the positive polarity main power circuit and the negative polarity mirror circuit are connected to the digital adjustment feedback circuit and the load, respectively.

[0016] The digital adjustment feedback circuit is configured to acquire the output voltage of either the positive polarity main power circuit or the negative polarity mirror circuit and feed it back to the control chip in the positive polarity main power circuit. It also sets the target value of the output terminal resistance based on instructions sent from the host computer; the target value can be set within a range of 2.15K to 10K. The positive polarity main power circuit is configured to positively boost the 12V input voltage, combined with the target value of the output terminal resistance and the voltage fed back from the digital adjustment feedback circuit, to output a target positive voltage to the load; the target positive voltage range is +23V to +100V. The negative polarity mirror circuit is configured to negatively boost the 12V input voltage, combined with the target value of the output terminal resistance and the voltage fed back from the digital adjustment feedback circuit, to output a target negative voltage to the load; the target negative voltage range is -23V to -100V.

[0017] This invention presents a novel hardware-based high-voltage power supply circuit, specifically designed for traditional phased-array ultrasonic instruments. Based on the LTC1871 chip and its peripheral circuitry, a positive-polarity main power circuit and a negative-polarity mirror circuit that reuses a portion of the positive-polarity main power circuit structure are designed. Utilizing the composite topology of these two circuits, combined with SPI voltage regulation via a digital feedback circuit, adjustable positive and negative DC high voltages (+23V to +100V and -23V to -100V) are output to the load. It features low ripple (<10mVpp), high conversion efficiency (>93%), a compact PCB layout, and low EMI, meeting the driving requirements of a 64-channel phased-array ultrasonic probe. Through hybrid topology innovation and digital adjustment technology, it overcomes the bottlenecks of efficiency, size, and noise in traditional high-voltage power supplies. As a novel power module, it can be widely used in industrial or medical phased-array high-voltage power supplies, demonstrating excellent practicality. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a modular schematic diagram of a high-voltage power supply circuit for a phased array ultrasonic instrument according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the positive polarity main power circuit illustrated in the embodiments of this utility model; Figure 3 This is a schematic diagram of the negative polarity mirror circuit exemplified in the embodiments of this utility model; Figure 4 This is a schematic diagram of the digital adjustment feedback circuit exemplified in an embodiment of this utility model. Detailed Implementation

[0019] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] The high-voltage power supply circuit for a phased array ultrasonic instrument of this invention includes: a positive polarity main power circuit, a negative polarity mirror circuit, and a digital adjustment feedback circuit; (Refer to...) Figure 1 The modular schematic diagram shows that the input terminal of the positive polarity main power circuit is connected to the output terminal of the digital adjustment feedback circuit; the input terminal of the digital adjustment feedback circuit is connected to the host computer. Figure 1 (Not shown in the diagram) Connection; The negative polarity mirror circuit reuses part of the structure in the positive polarity main power circuit as its input terminal; The output terminals of both the positive polarity main power circuit and the negative polarity mirror circuit are connected to the digital adjustment feedback circuit and the load respectively.

[0021] In the above structure, the digital adjustment feedback circuit is configured to acquire the output voltage of either the positive polarity main power circuit or the negative polarity mirror circuit, i.e., acquire the target positive voltage or the target negative voltage, generate a feedback voltage and feed it back to the control chip in the positive polarity main power circuit, and set the target value of the output terminal resistance based on the instructions sent by the host computer. The settable target value range is 2.15K~10K. The positive polarity main power circuit is configured to positively boost the 12V input voltage combined with the target value of the output terminal resistance and the voltage fed back by the digital adjustment feedback circuit, and output the target positive voltage to the load. The target positive voltage range of the output is +23V to +100V. The negative polarity mirror circuit is configured to negatively boost the 12V input voltage combined with the target value of the output terminal resistance and the voltage fed back by the digital adjustment feedback circuit, and output the target negative voltage to the load. The target negative voltage range of the output is -23V to -100V.

[0022] To better understand the circuit structure of the high-voltage power supply circuit described above, refer to... Figure 2 The diagram shown is a schematic of the positive polarity main power circuit. Figure 2 The control chip U43 is illustrated using the LTC1871 chip as an example.

[0023] The control chip U43 receives a 12V input voltage through its VIN pin via input resistor R779. Figure 2(VCC_12V_PA indicates this). The SENSE pin is connected to the source of the control MOSFET Q6, the first terminal of the first grounding resistor R789, and the first terminal of the frequency suppression resistor R813, respectively. The GATE pin is connected to the gate of the control MOSFET Q6. The second end of the first grounding resistor R789 is connected to the first end of the second grounding resistor R790, and the second end of the second grounding resistor R790 is grounded; the second end of the frequency suppression resistor R813 is connected to the first end of the frequency suppression capacitor C880, and the second end of the frequency suppression capacitor C880 is connected to the drain of the control MOS transistor Q6, the primary winding of the coupling inductor L8, and the first end of the first transmission capacitor C823, respectively.

[0024] The second terminal of the first transmission capacitor C823 is connected to the secondary winding of the coupling inductor L8 and the anode of the first diode D58, respectively; a filter capacitor bank is connected in parallel to the cathode of the first diode D58. Figure 2 After resistor R791 and capacitors C825, C827, and C829, it is connected to the digital adjustment feedback circuit. Figure 1 Resistors R780, R785, and R788 are part of the digital adjustment feedback circuit structure. HV_ADJ_PA_FB is the signal sent by the digital adjustment feedback circuit. Refer to [reference needed] for the specific structure. Figure 4 (As shown) connection.

[0025] The cathode of the first diode D58 is also connected to the first terminal of the first output inductor L10 through a resistor R794, and to another filter capacitor group ( Figure 2 The capacitors C832, C834, and C836 are connected in parallel, and the second terminal of the first output inductor L10 outputs the target positive voltage HV_PA_P. Figure 2 The example shown is PA+23V~+100V); all parallel filter capacitor banks must be grounded.

[0026] Combination Figure 2 The working principle of the positive polarity main power circuit is as follows: The switching on and off of MOSFET Q6 is controlled by the GATE pin of the control chip U43. This control is based on a pulse signal generated by the GATE pin, which is derived from the target value of the output resistor and the voltage feedback from the digital adjustment feedback circuit. When MOSFET Q6 is on, there are two loops: Loop 1 is the input DC 12V, which flows through resistor R779 and the two series-connected coils on the primary side of coupling inductor L8, then back to power ground via MOSFET Q6, grounding resistors R789 and R790; Loop 2 is the two series-connected coils on the secondary side of coupling inductor L8, which transmit power through transfer capacitor C823, then back to power ground via MOSFET Q6, grounding resistors R789 and R790.

[0027] When the MOSFET Q6 is turned off, there are two circuits: Circuit 1 is the two series coils on the secondary side of the coupling inductor L8, which are then boosted to high voltage output by the first diode D58 and resistor R794; Circuit 2 is the input DC 12V, which is then boosted to high voltage output by the first diode D58 and resistor R794 after passing through resistor R779 and the two series coils on the primary side of the coupling inductor L8.

[0028] Furthermore, to suppress ripple in the high-voltage output, the output stage employs a second-order filter network consisting of multi-stage, multi-layer ceramic capacitors C832 and C834, a chip-type high-voltage aluminum electrolytic capacitor C836, and an integrated alloy inductor L10. An RC snubber circuit, also known as an RC buffer circuit, is added to the switching node controlling the MOSFET Q6. This circuit, composed of a frequency suppression resistor R813 and a frequency suppression capacitor C880, effectively suppresses high-frequency ringing. This method effectively suppresses ripple in the positive high-voltage output, ensuring its accuracy and stability. Simulation results show that the peak-to-peak ripple of the positive polarity main power circuit is 7.12mV, significantly lower than that of the traditional structure.

[0029] The remaining pins of the control chip U43 and its peripheral circuits can be derived by those skilled in the art through simple reasoning based on the pin functions of the LTC1871 chip, and will not be described in detail here.

[0030] In the embodiments of this application, the negative polarity mirror circuit shares the control chip U43, control MOSFET Q6, and coupling inductor L8 in the positive polarity main power circuit. For a better understanding of the structure of the negative polarity mirror circuit, refer to... Figure 3 The schematic diagram of the negative polarity mirror circuit shown shows that the connection relationship between the control chip U43 and the control MOSFET Q6, and between the control MOSFET Q6 and the coupling inductor L8, is the same as that in the positive polarity main power circuit.

[0031] Figure 3 Zhongyu Figure 2 The same structure will not be described again. The difference between the negative polarity mirror circuit and the positive polarity main power circuit is that the negative polarity mirror circuit includes: a second transmission capacitor C824. The first end of the second transmission capacitor C824 is connected to the drain of the control MOS transistor Q6, the second end of the frequency suppression capacitor C880, and the primary side coil of the coupling inductor L8, respectively.

[0032] The second terminal of the second transmission capacitor C824 is connected to the secondary winding of the coupling inductor L8 and the anode of the second diode D59, respectively; the cathode of the second diode D59 is grounded; a filter capacitor bank is connected in parallel to the secondary winding of the coupling inductor L8. Figure 3 The resistor R792, capacitors C826, C828, and C830 are connected to the digital adjustment feedback circuit. The secondary winding of the coupling inductor L8 is also connected to the first terminal of the second output inductor L9 via a resistor R793, and to another filter capacitor bank ( Figure 3 The capacitors C831, C833, and C835 are connected in parallel, and the second output inductor L9 outputs the target negative voltage HV_PA_M at its second terminal. Figure 3 Examples are shown in the diagram (PA-23V~-100V); all parallel filter capacitor banks must be grounded.

[0033] Combination Figure 3 The working principle of the negative polarity mirror circuit is as follows: Similarly, the MOSFET Q6 is controlled to turn on and off via the GATE pin of the control chip U43. The control of the MOSFET Q6 via the GATE pin of the control chip U43 is based on the pulse signal it generates. This pulse signal is also generated based on the target value of the output resistor and the voltage fed back by the digital adjustment feedback circuit. The difference is that when the control chip Q6 is turned on, there are two loops: Loop 1 is the input DC 12V, which flows through the resistor R779 and the two series coils on the primary side of the coupling inductor L8, and then flows back to power ground through the control chip Q6, grounding resistors R789 and R790; Loop 2 is the two series coils on the secondary side of the coupling inductor L8, which transmit power through the transmission capacitor C824, and then flow back to power ground through the control chip Q6, grounding resistors R789 and R790.

[0034] When the control chip Q6 is off, there are two circuits: Circuit 1 is the two series coils on the secondary side of the coupled inductor L8, which then pass through the second diode D59 and the load, and are boosted to a negative high voltage output; Circuit 2 is the input DC 12V, which passes through the resistor R779 and the two series coils on the primary side of the coupled inductor L8, and then the power is transferred through the transmission capacitor C824, flows back to power ground through the second diode D59, and then passes through the load, and is boosted to a negative high voltage output.

[0035] Similarly, to suppress the ripple of the high-voltage output, the output stage of the negative polarity mirror circuit also uses a second-order filter network composed of multi-level, multi-layer ceramic capacitors C831 and C833, a chip-type high-voltage aluminum electrolytic capacitor C835, and an alloy integrated inductor L9; the RC buffer circuit consists of a frequency suppression resistor R813 and a frequency suppression capacitor C880, which can suppress high-frequency ringing. This method effectively suppresses the ripple of the negative high-voltage output, ensuring its accuracy and stability. Simulation results show that the peak-to-peak ripple of the negative polarity mirror circuit is 4.96mV, which is significantly lower than that of the traditional structure.

[0036] The MODE pin of the aforementioned control chip U43 is connected to the INTVCC pin (the classic value of this pin is 5.2V); this connection method enables the control chip U43 to be configured in synchronous SEPIC mode, that is, synchronous pulse skipping mode.

[0037] The coupling inductor L8 is preferably a six-winding coupling inductor, employing a transformer winding configuration. On the main coil output path of the coupling inductor L8 (i.e., the output path of the primary winding), resistors R789 and R790 are connected in parallel to ground as current-sensing resistors, and also serve as conventional shunt resistors controlling the source of the MOSFET Q6. These resistors are connected to the SENSE pin of the control chip U43 to form a current sampling circuit. Simultaneously, when the load current changes, the output current remains adjustable through the amplifier comparator circuit associated with the SENSE pin within the control chip U43.

[0038] The two transfer capacitors, C824 and C823, serve as power transfer capacitors and additionally provide DC blocking from the VIN pin to VOUT. This DC blocking characteristic can provide protection when there is a risk of output short circuit. Furthermore, since the coupling inductor L8 is a transformer winding, this isolated output topology protects front-end chips and other devices from damage in the event of a short circuit at the output.

[0039] In embodiments of this application, the digital adjustment feedback circuit includes a dual-channel digital potentiometer. For a better understanding of the structure of the digital adjustment feedback circuit, refer to... Figure 4 The schematic diagram of the digital adjustment feedback circuit shown indicates that the dual-channel digital potentiometer U40 receives data from the host computer via the CS#, SCK, SI, and SO pins. Figure 4 The SPI command (not shown) is sent to set the resistance value of the output terminal resistor, which varies from 2.15KΩ to 10KΩ. The PW0 pin of the dual-channel digital potentiometer U40 is connected to the positive polarity main power circuit and the negative polarity mirror circuit respectively through a voltage divider structure.

[0040] The above pressure-dividing structure refers to Figure 1 As shown, it includes: a first voltage divider resistor R780, a second voltage divider resistor R785, and a third voltage divider resistor R788. The first terminal of the first voltage divider resistor R780 is connected to the PW0 pin and receives the HV_ADJ_PA_FB signal sent by the PW0 pin of the dual-channel digital potentiometer U40. The second terminal of the first voltage divider resistor R780 is connected to the FB pin of the control chip U43, the first terminal of the second voltage divider resistor R785, and the first terminal of the grounding capacitor C821, the second terminal of which is grounded.

[0041] The first terminal of the second voltage divider resistor R785 also receives external direct voltage. Figure 1 TP45 represents the input of the external direct voltage, and the voltage value of this voltage Vfb is 1.23V; the second terminal of the second voltage divider resistor R785 is connected to the first terminal of the third voltage divider resistor R788, and the second terminal of the third voltage divider resistor R788 is connected to the positive polarity main power circuit and the negative polarity mirror circuit respectively.

[0042] The dual-channel digital potentiometer U40 (10kΩ / 256 levels, 0.4% accuracy) allows the output resistor Radj to be set within the range of 2.15K-10K via SPI commands (CLK=10MHz). Through a 374K resistor divider at the back end (the sum of the resistances of the first divider resistor R780, the second divider resistor 785, and the third divider resistor 788), the high-voltage power supply output voltage can be calculated to be adjustable from ±23V to ±100V using the formula VO = 1.230V * (1 + 374 / Radj).

[0043] In the embodiments of this application, to prevent uncontrolled high-voltage power supply output after the phased array ultrasonic instrument is powered on, a 12V input enable control circuit is added. (See also...) Figure 4 The digital adjustment feedback circuit also includes an enable control circuit; the enable control circuit includes a switching MOSFET Q7.

[0044] Switching the source of MOSFET Q7 to receive a 12V input voltage ( Figure 4 The MOSFET Q7 is represented by VCC_12V and connected to its gate via a resistor R826. The gate of MOSFET Q7 is connected to the collector of transistor Q8, and the base of transistor Q8 is connected to the external FPGA via a voltage divider resistor R827. Figure 4 (Not shown in the image) is connected to receive control signals sent by the FPGA. Figure 4 (represented by F_PA_PWREN in Chinese), transistor Q8's emitter is grounded.

[0045] A voltage regulator capacitor C865 is connected in parallel to the drain of MOSFET Q7, and is also connected to the positive main power circuit and the negative mirror circuit respectively, outputting a 12V input voltage to both. Figure 4 (Represented as VCC_12V_PA in Chinese). The on / off MOSFET Q7 acts as an ideal diode circuit to implement input reverse connection protection. Its gate pin is controlled by the FPGA to enable or disable the output of the high-voltage power supply.

[0046] In one embodiment of this application, the preferred selection of the above-mentioned devices is as follows: The control chip U43 is model LTC1871; the control MOSFET Q6 is an N-MOSFET, model APM4953, with parameters of 80V / 20A and Rds=0.1Ω. The duty cycle of the control chip U43's GATE pin is set to a range of 50%~80%; the switching MOSFET Q7 is a P-MOSFET, model FDS6679, with parameters of 30V and Rds=0.013Ω.

[0047] The coupling inductor L8 is model VPH4-0860-R with an inductance of 159μH; the parallel filter capacitor bank includes: a multilayer ceramic capacitor, model 250V X7R with a capacitance of 2.2μF; and a high-voltage aluminum electrolytic capacitor, model UUJ2C330MNQ1MS with parameters of 33μF / 160V, 12.5*13.5, and 95mA@120Hz.

[0048] The first output inductor L10 and the second output inductor L9 are both integrally molded alloy power inductors, which, together with their respective connected filter capacitor groups, form a second-order filter network with parameters of 30 ohms @ 100 MHz / 3 A. The frequency suppression resistor R813 and the frequency suppression capacitor C880 form an RC buffer circuit with parameters of 10Ω / 1W + 1nF / 1kV. The first grounding resistor R789 and the second grounding resistor R790 are both WSL2512R0220FEA with a resistance of 0.44Ω.

[0049] To verify the effectiveness of the high-voltage power supply circuit described in this application, the high-voltage power supply circuit for the phased array ultrasonic instrument was fabricated and tested. The results were compared with those of a traditional phased array ultrasonic instrument using a Flyback circuit architecture, and are shown in the table below.

[0050] It is evident that the high-voltage power supply circuit proposed in this application, compared to the traditional structure, not only has a smaller PCB area but also superior performance in various aspects.

[0051] Based on the above-mentioned high-voltage power supply circuit, this utility model embodiment also proposes a phased array ultrasonic instrument, which includes the above-mentioned high-voltage power supply circuit for the phased array ultrasonic instrument.

[0052] In summary, the high-voltage power supply circuit for a phased array ultrasonic instrument of this invention includes: a positive polarity main power circuit, a negative polarity mirror circuit, and a digital adjustment feedback circuit. The input terminal of the positive polarity main power circuit is connected to the output terminal of the digital adjustment feedback circuit; the input terminal of the digital adjustment feedback circuit is connected to a host computer; the negative polarity mirror circuit reuses part of the structure in the positive polarity main power circuit (reusing the control chip, control MOSFET, and coupling inductor) as its input terminal; the output terminals of both the positive polarity main power circuit and the negative polarity mirror circuit are connected to the digital adjustment feedback circuit and the load, respectively.

[0053] The digital adjustment feedback circuit is configured to acquire the output voltage of either the positive polarity main power circuit or the negative polarity mirror circuit and feed it back to the control chip in the positive polarity main power circuit. It also sets the target value of the output terminal resistance based on instructions sent from the host computer; the target value can be set within a range of 2.15K to 10K. The positive polarity main power circuit is configured to positively boost the 12V input voltage, combined with the target value of the output terminal resistance and the voltage fed back from the digital adjustment feedback circuit, to output a target positive voltage to the load; the target positive voltage range is +23V to +100V. The negative polarity mirror circuit is configured to negatively boost the 12V input voltage, combined with the target value of the output terminal resistance and the voltage fed back from the digital adjustment feedback circuit, to output a target negative voltage to the load; the target negative voltage range is -23V to -100V.

[0054] This invention presents a novel hardware-based high-voltage power supply circuit, specifically designed for traditional phased-array ultrasonic instruments. Based on the LTC1871 chip and its peripheral circuitry, a positive-polarity main power circuit and a negative-polarity mirror circuit that reuses a portion of the positive-polarity main power circuit structure are designed. Utilizing the composite topology of these two circuits, combined with SPI voltage regulation via a digital adjustment feedback circuit, adjustable positive and negative DC high voltages (+23V to +100V and -23V to -100V) are output to the load.

[0055] It also features excellent high-voltage output ripple suppression, ensuring accurate and stable positive and negative high-voltage outputs. When the load current changes, the amplifier comparator circuit related to the SENSE pin inside the control chip maintains the adjustability of the output current. It provides DC blocking, which protects against output short-circuit risks. In the event of a short circuit at the output, the coupling inductor isolates the output topology, protecting front-end chips and other components from damage. Furthermore, it prevents uncontrolled high-voltage power supply output after the phased array ultrasonic instrument is powered on.

[0056] The entire high-voltage power supply circuit features low ripple (<10mVpp), high conversion efficiency (>93%), compact PCB layout, and low EMI, meeting the driving requirements of a 64-channel phased array ultrasound probe. Through hybrid topology innovation and digital adjustment technology, it overcomes the bottlenecks of traditional high-voltage power supply efficiency, size, and noise. As a novel power module, it can be widely used in industrial or medical phased array high-voltage power supplies, demonstrating excellent practicality.

[0057] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0058] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0059] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A high-voltage power supply circuit for a phased array ultrasonic instrument, characterized in that, include: Positive polarity main power circuit, negative polarity mirror circuit, digital adjustment feedback circuit; The input terminal of the positive polarity main power circuit is connected to the output terminal of the digital adjustment feedback circuit; The input terminal of the digital adjustment feedback circuit is connected to the host computer; the negative polarity mirror circuit reuses part of the structure in the positive polarity main power circuit as its input terminal; the output terminals of the positive polarity main power circuit and the negative polarity mirror circuit are respectively connected to the digital adjustment feedback circuit and the load. The digital adjustment feedback circuit is configured to acquire the output voltage of the positive polarity main power circuit or the negative polarity mirror circuit and feed it back to the control chip in the positive polarity main power circuit, and set the target value of the output terminal resistance based on the instruction sent by the host computer. The range of the settable target value is 2.15K~10K. The positive polarity main power circuit is configured to positively boost the 12V input voltage in combination with the target value of the output terminal resistor and the voltage fed back by the digital adjustment feedback circuit, and output a target positive voltage to the load. The target positive voltage range of the output is +23V to +100V. The negative polarity mirror circuit is configured to perform a negative boost on the 12V input voltage, combined with the target value of the output terminal resistor and the voltage fed back by the digital adjustment feedback circuit, and output a target negative voltage to the load. The target negative voltage range of the output is -23V to -100V.

2. The high-voltage power supply circuit according to claim 1, characterized in that, The positive polarity main power circuit includes: The control chip has a VIN pin that receives a 12V input voltage through an input resistor, a SENSE pin that is connected to the source of the control MOS transistor, the first end of the first grounding resistor, and the first end of the frequency suppression resistor, and a GATE pin that is connected to the gate of the control MOS transistor. The second end of the first grounding resistor is connected to the first end of the second grounding resistor, and the second end of the second grounding resistor is grounded. The second end of the frequency suppression resistor is connected to the first end of the frequency suppression capacitor, and the second end of the frequency suppression capacitor is connected to the drain of the control MOS transistor, the primary winding of the coupling inductor, and the first end of the first transmission capacitor, respectively. The second terminal of the first transmission capacitor is connected to the secondary side coil of the coupling inductor and the anode of the first diode, respectively. The cathode of the first diode is connected in parallel with a filter capacitor bank and then connected to the digital adjustment feedback circuit. The cathode of the first diode is also connected to the first terminal of the first output inductor through a resistor and is connected in parallel with another filter capacitor bank. The second terminal of the first output inductor outputs the target positive voltage. All parallel filter capacitor banks must be grounded.

3. The high-voltage power supply circuit according to claim 2, characterized in that, The negative polarity mirror circuit shares the control chip, the control MOSFET, and the coupling inductor in the positive polarity main power circuit, and the connection relationships between the control chip and the control MOSFET, and between the control MOSFET and the coupling inductor are also the same; The negative polarity mirror circuit also includes: The first end of the second transmission capacitor is connected to the drain of the control MOS transistor, the second end of the frequency suppression capacitor, and the primary winding of the coupling inductor, respectively. The second terminal of the second transmission capacitor is connected to the secondary side coil of the coupled inductor and the anode of the second diode, respectively. The cathode of the second diode is grounded; The secondary coil of the coupled inductor is connected in parallel with a filter capacitor bank and then connected to the digital adjustment feedback circuit. The secondary coil of the coupled inductor is also connected to the first end of the second output inductor through a resistor and in parallel with another filter capacitor bank. The second end of the second output inductor outputs the target negative voltage. All parallel filter capacitor banks must be grounded.

4. The high-voltage power supply circuit according to claim 2, characterized in that, The digital adjustment feedback circuit includes: A dual-channel digital potentiometer that receives SPI commands from a host computer via the CS#, SCK, SI, and SO pins. These SPI commands are used to set the resistance value of the output terminal, which ranges from 2.15KΩ to 10KΩ. The PW0 pin of the dual-channel digital potentiometer is connected to the positive polarity main power circuit and the negative polarity mirror circuit respectively through a voltage divider structure.

5. The high-voltage power supply circuit according to claim 1, characterized in that, The digital adjustment feedback circuit also includes: an enable control circuit; The enable control circuit includes: a switching MOSFET; The source of the MOSFET receives a 12V input voltage and is connected to its gate through a resistor. The gate of the MOSFET is connected to the collector of the transistor, and the base of the transistor is connected to the external FPGA through a voltage divider resistor to receive control signals sent by the FPGA. The emitter of the transistor is grounded. A voltage-regulating capacitor is connected in parallel to the drain of the MOSFET and is connected to the positive main power circuit and the negative mirror circuit respectively, outputting a 12V input voltage to both.

6. The high-voltage power supply circuit according to claim 2, characterized in that, The MODE pin of the control chip is connected to the INTVCC pin; The control chip is configured in synchronous SEPIC mode, i.e., synchronous pulse skipping mode.

7. The high-voltage power supply circuit according to claim 2, characterized in that, The coupling inductor is a six-winding coupling inductor, using a transformer winding configuration.

8. The high-voltage power supply circuit according to claim 4, characterized in that, The voltage divider structure includes: a first voltage divider resistor, a second voltage divider resistor, and a third voltage divider resistor; The first end of the first voltage divider resistor is connected to the PWO pin, and the second end is connected to the FB pin of the control chip, the first end of the second voltage divider resistor, and the first end of the grounding capacitor. The second end of the grounding capacitor is grounded. The first terminal of the second voltage divider resistor also receives an external direct voltage, which is 1.23V. The second end of the second voltage divider resistor is connected to the first end of the third voltage divider resistor, and the second end of the third voltage divider resistor is connected to the positive polarity main power circuit and the negative polarity mirror circuit, respectively.

9. The high-voltage power supply circuit according to claim 3, characterized in that, include: The control chip is model LTC1871; The control MOSFET is an N-MOSFET, model APM4953, with parameters of 80V / 20A and Rds=0.1Ω. The duty cycle of the GATE pin is set to a range of 50%~80%. The coupling inductor is model VPH4-0860-R with an inductance of 159μH; The parallel filter capacitor bank includes: a multilayer ceramic capacitor, model 250V X7R, with a capacitance of 2.2μF; and a high-voltage aluminum electrolytic capacitor, model UUJ2C330MNQ1MS, with parameters of 33μF / 160V, 12.5*13.5, and 95mA@120Hz. Both the first output inductor and the second output inductor are integrally molded alloy power inductors, which, together with their respective connected filter capacitor banks, form a second-order filter network with parameters of 30 ohm @ 100 MHz / 3 A. The frequency suppression resistor and the frequency suppression capacitor form an RC snubber circuit with parameters of 10Ω / 1W+1nF / 1kV. Both the first and second grounding resistors are model WSL2512R0220FEA, and their resistance values ​​are both 0.44Ω.

10. A phased array ultrasonic instrument, characterized in that, The phased array ultrasonic instrument includes a high-voltage power supply circuit for a phased array ultrasonic instrument as described in any one of claims 1-9.

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