Input stage circuit and chip testing apparatus

Abstract

An input stage circuit and a chip testing device are disclosed. The input stage circuit is configured to drive a fully differential amplifier having an input terminal. The input stage circuit includes a signal input terminal, a first path configured to directly connect the signal input terminal to the input terminal of the fully differential amplifier, a second path including at least a series connection of an attenuation network and an operational amplifier, the attenuation network being connected to the signal input terminal, and an output terminal of the operational amplifier being connected to the input terminal of the fully differential amplifier, and a switch assembly coupled between the signal input terminal and the fully differential amplifier and configured to selectively enable the first path or the second path to connect the signal input terminal to the input terminal of the fully differential amplifier through the selected path. The circuit reduces the large signal bandwidth requirement of the input operational amplifier under high frequency conditions.

Description

Technical Field

[0001] This application relates to the field of signal conditioning technology, and in particular to an input stage circuit and chip testing device. Background Technology

[0002] In the field of semiconductor chip testing, small-signal measurement systems (often called digitizer systems) are widely used to evaluate the DC and AC performance metrics of digital-to-analog converter (DAC) chips, such as integral nonlinearity, signal-to-noise ratio, and total harmonic distortion (THD). A typical architecture of such systems includes an input buffer, a fully differential amplifier driver stage, and an analog-to-digital converter. It must also support flexible switching of input impedance between low-impedance states (e.g., 50 ohms) and high-impedance states (e.g., 1 megaohm) to adapt to different testing scenarios.

[0003] Currently, a common approach to input impedance switching is to connect resistors of different values ​​in parallel at the preamplifier stage and combine this with switch control. Figures 1 to 3 As shown. Although this scheme is relatively simple in structure and suitable for measuring low-frequency signals below tens of megahertz, its performance is significantly limited in high-frequency applications. When the signal frequency increases to the range of hundreds of megahertz, since analog-to-digital converters generally use differential input and are driven by high-speed fully differential amplifiers, if a single-ended operational amplifier is used as the input buffer and impedance switching unit in the front stage, the harmonic distortion introduced will be superimposed on the entire signal chain, severely degrading the system's key performance indicators such as total harmonic distortion and signal-to-noise ratio in the high-frequency band, thus making it difficult to meet the requirements of high-speed and high-precision testing. Summary of the Invention

[0004] One of the objectives of this application is to provide an input stage circuit to solve the technical problem in the prior art where the use of single-ended operational amplifiers for input impedance switching in signal measurement systems easily introduces harmonic distortion, leading to a severe performance degradation of the system under high-frequency signals.

[0005] One objective of this application is to provide an input stage circuit for driving a fully differential amplifier having an input terminal. The input stage circuit includes: a signal input terminal; a first path configured to directly connect the signal input terminal to the input terminal of the fully differential amplifier; a second path including at least a series-connected attenuation network and an operational amplifier, the attenuation network being connected to the signal input terminal and the output terminal of the operational amplifier being connected to the input terminal of the fully differential amplifier; and a switching component coupled between the signal input terminal and the fully differential amplifier, configured to selectively conduct either the first path or the second path to connect the signal input terminal to the input terminal of the fully differential amplifier via the selected path.

[0006] As a further improvement of one embodiment of this application, the fully differential amplifier is configured to provide a preset low impedance value at its input.

[0007] As a further improvement of one embodiment of this application, the attenuation network includes a first part and a second part connected in series. The first part is connected to the signal input terminal, one end of the second part is connected to the input terminal of the operational amplifier, and the other end is connected to a reference potential. The first part is used to establish high impedance and achieve voltage attenuation, and the second part is used to filter out high-frequency noise.

[0008] As a further improvement of one embodiment of this application, the first part includes a first resistor and a first capacitor connected in parallel, and the second part includes a second resistor and a second capacitor connected in parallel, wherein the first resistor and the second resistor are configured such that the sum of their corresponding first resistance values ​​and second resistance values ​​is equal to a preset high impedance value, and the ratio of the first resistance value to the second resistance value is equal to the ratio of the second capacitance value of the second capacitor to the first capacitance value of the first capacitor.

[0009] As a further improvement of one embodiment of this application, the attenuation value of the attenuation network is set as the ratio of the first resistance value to the sum of the first resistance value and the second resistance.

[0010] As a further improvement of one embodiment of this application, the operational amplifier is configured as a voltage follower.

[0011] As a further improvement of one embodiment of this application, the preset high impedance value is 1 Mohm, and the preset low impedance value is 50 ohm.

[0012] As a further improvement of one embodiment of this application, the switching assembly includes a first switch and a second switch, the first switch being connected to the signal input terminal and the second switch being connected to the input terminal of the fully differential amplifier; the first path and the second path are connected in parallel between the first switch and the second switch.

[0013] As a further improvement of one embodiment of this application, the first switch and / or the second switch is a single-pole double-throw switch or a relay.

[0014] To achieve one of the above-mentioned objectives, one embodiment of this application provides a chip testing device, which includes the input stage circuit described in any one of the claims.

[0015] Compared with the prior art, the embodiments of this application have at least one of the following beneficial effects: This application employs an input stage circuit. On one hand, in low-impedance operating mode, the signal is directly connected to the fully differential amplifier via a through-path, completely avoiding the harmonic distortion introduced by the buffer stage of the traditional single-ended operational amplifier. This allows the system's harmonic distortion performance and signal-to-noise ratio in the high-frequency band to be directly determined by the high-performance fully differential amplifier, thereby significantly improving test accuracy. On the other hand, in high-impedance operating mode, a cascaded design between the pre-attenuation network and the operational amplifier ensures high input impedance characteristics while effectively reducing the dynamic range requirements of the subsequent operational amplifier by utilizing the attenuation network. This solves the stringent requirements of traditional solutions for operational amplifier slew rate and large signal bandwidth. This dual-path parallel and functionally specialized design reduces the large signal bandwidth requirement of the input operational amplifier under high-frequency conditions. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a high-speed small signal measurement system in one embodiment of this application.

[0017] Figure 2 This is a schematic diagram of a conventional input impedance switching structure in one embodiment of this application.

[0018] Figure 3 This is a schematic diagram of a conventional input impedance switching structure in another embodiment of this application.

[0019] Figure 4 This is a schematic diagram of the input stage circuit in one embodiment of this application. Detailed Implementation

[0020] The present application will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of this application.

[0021] The terms used in this document, such as “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” indicating spatial relative positions, are used for illustrative purposes to describe the relationship of one unit or feature relative to another unit or feature as shown in the accompanying drawings. The terms “spatial relative positions” may be intended to include different orientations of the equipment in use or operation other than those shown in the figures.

[0022] For example, if the device in the figure is flipped, a unit described as being "below" or "under" other units or features will be "above" other units or features. Therefore, the exemplary term "below" can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially related descriptive terms used herein will be interpreted accordingly.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] It should be noted that the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] like Figure 4 As shown, one embodiment of this application provides an input stage circuit 100.

[0026] The input stage circuit 100 refers to the circuit module located at the very front end of the signal processing system. It is responsible for receiving the raw electrical signals from the signal source and performing primary operations such as impedance transformation, signal conditioning, or mode switching. Its performance (e.g., input impedance, noise, and bandwidth) directly determines the fidelity and adaptability of the entire system to external signals.

[0027] In this application, the input stage circuit 100 is a configurable impedance interface designed specifically for driving the subsequent fully differential amplifier 13.

[0028] The fully differential amplifier 13 is a high-performance amplifier integrated circuit with differential input and differential output structures. It has one input terminal and internally includes a high-gain error amplifier and a matched built-in resistor network to realize single-ended signal to differential signal conversion, common-mode noise suppression, and provide the low-distortion, large-swing differential signal required to drive high sampling rate mode converters.

[0029] The input stage circuit 100 includes a signal input terminal 11. The signal input terminal 11 is the electrical interface port of the circuit or system, and is the physical node through which the input stage circuit 100 receives external signals. The characteristics of this port (e.g., connector type, wiring, etc.) must be matched with the output characteristics of the signal source and the transmission line impedance to ensure complete signal transmission.

[0030] The input stage circuit 100 includes a first path 12, which is configured to directly connect the signal input terminal 11 to the input terminal of the fully differential amplifier 13.

[0031] It should be noted that the first path 12 is a direct signal path, configured to physically bypass any active gain or buffer stage, routing the input signal directly to the subsequent circuitry with minimal insertion loss and phase distortion. This path is used to achieve a low-impedance, high-performance input mode.

[0032] For example, the 50-ohm signal received at the signal input terminal 11 can be directly input to the fully differential amplifier 13 via the first path 12, and impedance matching can be achieved directly using the subsequent fully differential amplifier 13. By configuring the values ​​of the input series resistor and the feedback resistor around the fully differential amplifier 13, the equivalent input impedance from the input terminal is made to be exactly 50Ω (ohms). Figure 4 The equivalent impedance is represented by R3 = 50Ω. In actual calculations, this is the impedance represented by the feedback network of the fully differential amplifier 13.

[0033] In the first path 12, since the operational amplifier 16 is completely bypassed, there is one less active device in the signal chain, that is, one less source of harmonic distortion and noise. The total harmonic distortion and noise performance is mainly determined by the better-performing fully differential amplifier and digital-to-analog converter (ADC).

[0034] The input stage circuit 100 includes a second path 14, which includes at least a series-connected attenuation network 15 and an operational amplifier 16. The attenuation network 15 is connected to the signal input terminal 11, and the output terminal of the operational amplifier 16 is connected to the input terminal of the fully differential amplifier 13.

[0035] The attenuation network 15 is a two-port network composed of passive components such as resistors and capacitors in a specific topology (such as an L-type or compensated voltage divider). It is used to provide a stable voltage attenuation coefficient that is independent of the signal frequency over a wide bandwidth, and works with the operational amplifier 16 to set the input impedance of the system in high-impedance mode.

[0036] In one embodiment, the attenuation network 15 includes a first part 15-1 and a second part 15-2 connected in series. The first part 15-1 is connected to the signal input terminal 11, and one end of the second part 15-2 is connected to the input terminal of the operational amplifier 16, while the other end is connected to a reference point. The first part 15-1 is used to establish high impedance and achieve voltage attenuation, while the second part 15-2 is used to filter out high-frequency noise.

[0037] In one specific embodiment, the first part 15-1 includes a first resistor R1 and a first capacitor C1 connected in parallel, and the second part 15-2 includes a second resistor R2 and a second capacitor C2 connected in parallel.

[0038] Specifically, continue to refer to Figure 4 As shown, the first end of the first resistor R1 and the first end of the first capacitor C1 are connected to the first node and serve as the input of the attenuation network 15; the first end of the second resistor R2 and the first end of the second capacitor C2 are both connected to the first node, which serves as the output of the attenuation network 15 and is connected to the input of the operational amplifier 16; the second end of the second resistor R2 and the second end of the second capacitor C2 are connected to a reference potential (e.g., ground).

[0039] In one specific embodiment, the reference potential refers to the common reference ground of the circuit.

[0040] It should be noted that the first part 15-1 (the first resistor R1 and the first capacitor C1 in parallel) is connected in series in the signal path after being connected in parallel, and its corresponding first composite impedance changes with frequency. At low frequencies, the capacitive reactance of the first capacitor C1 increases, and this first composite impedance is mainly determined by the first resistor R1, which is used for signal attenuation and setting the direct input impedance; at high frequencies, the capacitive reactance of the first capacitor C1 decreases, and the first composite capacitive reactance decreases accordingly, which weakens the attenuation effect of the first part 15-1 on high-frequency signals.

[0041] Therefore, Part 15-1 is used to provide a dynamic impedance that varies with frequency, together with Part 14 to form a frequency-dependent voltage division ratio, and to perform preliminary phase lead compensation for high-frequency signals.

[0042] Part 2, section 15-2 (the second resistor R2 and the second capacitor C2 in parallel), is directly connected between the input of operational amplifier 16 and the reference ground. Its corresponding second composite impedance also varies with frequency. At low frequencies, the difference between the second composite impedance and the second resistor R2 is small, and together with part 15-1, it determines the low-frequency attenuation ratio. At high frequencies, the capacitive reactance of the second capacitor C2 decreases, causing the second composite capacitive reactance to approach zero. Connected in parallel with the second resistor R2, it provides a frequency-dependent load to ground for the circuit.

[0043] Specifically, on the one hand, it participates in setting low-frequency attenuation; on the other hand, it provides a low-impedance ground discharge path for high-frequency noise and interference signals through the second capacitor C2, thereby suppressing high-frequency noise, limiting system bandwidth, and improving the operating stability of operational amplifier 16.

[0044] The entire attenuation network 15 is a composite impedance voltage divider consisting of the first part 15-1 and the second part 15-2 connected in series. By selecting appropriate R1, C1, R2 and C2, the voltage divider can provide high input impedance and basic attenuation, while utilizing the synergistic effect of the two parallel networks to achieve bandwidth control, high-frequency noise suppression and phase characteristic shaping, ensuring that the subsequent operational amplifier 16 operates stably in its linear region.

[0045] In one embodiment, the first resistor R1 and the second resistor R2 are configured such that the sum of their corresponding first resistance values ​​and second resistance values ​​is equal to a preset high impedance value.

[0046] In one specific embodiment, the preset high impedance value is 1 Mohm (or, 1 M ohm, 1 MΩ).

[0047] In this way, high input impedance can be provided to meet the requirements of high-impedance input.

[0048] Among them, the first resistor R1 and the second resistor R2 are voltage divider resistors, and the first capacitor C1 and the second capacitor C2 are compensation capacitors.

[0049] In one embodiment, the ratio of the first resistance value to the second resistance value is equal to the ratio of the second capacitance value of the second capacitor C2 to the first capacitance value of the first capacitor C1. That is, R1 / R2 = C2 / C1.

[0050] In this way, by configuring the resistor ratio to be the reciprocal of the capacitor ratio, the voltage division ratios of the resistor and capacitor are ensured to be the same, so that the voltage division ratio (i.e., the attenuation coefficient α) of the entire attenuation network remains consistent at different frequencies. Otherwise, the attenuation would vary with frequency, resulting in an uneven amplitude-frequency response.

[0051] In one specific embodiment, the attenuation value of the attenuation network 15 is set as the ratio of the first resistance value to the sum of the first resistance value and the second resistance value. That is, the attenuation coefficient is equal to α = R1 / (R1 + R2).

[0052] Operational amplifier 16 is a voltage-controlled voltage source with high open-loop gain, high input impedance, and low output impedance.

[0053] It should be noted that the second path 14 is a conditioned signal path used to achieve a high input impedance input mode, while reducing the dynamic range requirements of subsequent active devices (such as operational amplifiers) through the pre-attenuation network 15.

[0054] In one embodiment, the fully differential amplifier 13 is configured to provide a preset low impedance value at its input.

[0055] In this way, this configuration ensures that when the signal passes through the first path 12 (i.e., the through path), the entire input stage circuit 100 presents a precise, stable, and frequency-independent low input impedance.

[0056] In one specific embodiment, the preset low impedance value is 50 ohms (or, 50 ohms, 50Ω).

[0057] In one specific embodiment, operational amplifier 16 is configured as a voltage follower.

[0058] This enables buffer isolation with high input impedance and low output impedance, ensuring that the performance of the attenuation network is not affected by the subsequent circuitry and can effectively drive the subsequent load.

[0059] A voltage follower is a circuit configuration in which the output is directly fed back to the inverting input, while the non-inverting input receives the signal input. This feedback structure allows it to achieve high input impedance and low output impedance while maintaining a constant signal voltage amplitude. For example, the input impedance can reach the megaohm level, effectively avoiding a load effect on the preceding circuitry; the output impedance can be reduced to the ohm level, giving it strong load driving capability.

[0060] In the second path 14, the signal amplitude is reduced as it is first attenuated by the attenuation network 15, resulting in a smaller signal amplitude reaching the input of the operational amplifier 16. For a signal requiring an output of 1Vpp (Voltage Peak-to-Peak), if the attenuation coefficient α of the attenuation network 15 is 0.1, the actual input signal amplitude that the operational amplifier 16 needs to process is only 0.1Vpp. This reduces the required slew rate and large-signal bandwidth of the operational amplifier 16 by a factor of 10. This allows for the selection of a lower-cost, lower-power, and more common operational amplifier 16, significantly reducing the performance requirements for the operational amplifier 16 while retaining its high-impedance characteristics. This is because, although the signal is attenuated, the system's input impedance remains unchanged, determined by R1+R2=1MΩ.

[0061] The input stage circuit 100 also includes a switching component coupled between the signal input terminal 11 and the fully differential amplifier 13, which is configured to selectively conduct either the first path 12 or the second path 14 to connect the signal input terminal 11 to the input terminal of the fully differential amplifier 16 via the selected path.

[0062] "Coupling" refers to the establishment of a signal path between two circuit modules or components through a direct electrical connection or passive / active network, enabling information transmission. It can encompass various forms, from simple wire connections (direct coupling) to connections through components such as capacitors and transformers (AC coupling), without specific limitations.

[0063] In one embodiment, the switching assembly includes a first switch 17 and a second switch 18. The first switch 17 is connected to the signal input terminal 11, and the second switch 18 is connected to the input terminal of the fully differential amplifier 13. A first path 12 and a second path 14 are connected in parallel between the first switch 17 and the second switch 18.

[0064] In this way, by using two independent switches, complete isolation and no crosstalk between the two signal paths are ensured, and the switching action is synchronized.

[0065] Specifically, the first switch 17 selects the signal input and the second switch 18 selects the signal output. This architecture physically ensures that only the selected path is connected, while the other path is completely disconnected from the circuit, achieving true path isolation.

[0066] In one specific embodiment, the first switch 17 is a single-pole double-throw switch or a relay; the second switch 18 is a single-pole double-throw switch or a relay.

[0067] The various implementation methods, embodiments, or specific examples provided in this application can be combined with each other to ultimately form multiple better implementation methods.

[0068] The following is combined Figure 4 Describe the specific processing procedure of the input stage circuit 100 described in this application.

[0069] When the device under test is a current output type or requires low input impedance (e.g., 50Ω) load matching, the first switch 17 and the second switch 18 operate synchronously, and the switching components conduct the first path 12, so that the input signal completely bypasses the attenuation network 15 and the operational amplifier 16 and is directly connected to the fully differential amplifier 13, thereby constructing a passive and shortest direct communication channel. This direct connection method is simple and direct, with less interference to the signal, and fundamentally eliminates the harmonic distortion and noise that may be introduced by the active devices in the front stage.

[0070] That is, the first path 12 is: signal input terminal -> first switch S1 -> [Bypass path] -> second switch S2 -> equivalent input impedance R3 -> fully differential amplifier (FDA) -> digital-to-analog converter (ADC).

[0071] When the device under test is a voltage output type and requires high impedance measurement, the first switch 17 and the second switch 18 operate synchronously. The switching components cause the second path 14. The input signal is first scaled by a fixed ratio through the attenuation network 15 to reduce the dynamic range required by the subsequent operational amplifier 16. The signal attenuated by the attenuation network 15 is then impedance transformed by the operational amplifier 16 configured as a voltage follower. Its high input impedance ensures the accuracy of the attenuation ratio, and its low output impedance drives the subsequent fully differential amplifier 13.

[0072] This process effectively reduces the slew rate and dynamic range of the signal to be processed by the operational amplifier 16 through pre-attenuation, thereby suppressing the nonlinear distortion that may occur when it operates at high slew rate, and ensuring the measurement accuracy and stability of the system under high frequency conditions.

[0073] That is, the second path 14 is: signal input terminal -> attenuation network -> operational amplifier (A1) -> first switch S1 -> second switch S2 -> equivalent input impedance R3 -> fully differential amplifier (FDA) -> digital-to-analog converter (ADC).

[0074] The two paths described above physically separate the 50Ω low-impedance input path and the 1MΩ high-impedance input path, customizing two distinct signal paths for two different needs (high impedance vs. high performance). By using a switch to switch between the two independent paths, a balance between high linearity and high input impedance is achieved in the high-frequency range.

[0075] The input stage circuit 100 described in this application is compared to Figures 1 to 3 The existing technical solution described above has the following advantages: Figure 1 A schematic diagram of a high-speed small-signal measurement system is shown, including an input buffer, a fully differential amplifier, and an analog-to-digital converter. It highlights the need for compatibility with both low-impedance inputs (e.g., 50Ω) and high-impedance inputs (e.g., 1MΩ). However, it only states the objective without providing specific high-frequency solutions, thus failing to address the contradictions inherent in high-speed applications.

[0076] Figure 2 The diagram illustrates a traditional input impedance switching scheme. Its core principle is to use a switch at the input of the operational amplifier to switch between parallel low-impedance inputs (e.g., 50Ω) and high-impedance inputs (e.g., 1MΩ), thereby changing the input impedance. While this scheme is simple in structure, at frequencies above 100MHz, the signal must pass through a pre-amplified single-ended op-amp, which introduces its own harmonic distortion into the entire system, severely degrading high-frequency performance (such as total harmonic distortion and signal-to-noise ratio).

[0077] Figure 3This diagram illustrates another conventional input impedance switching architecture. Its core principle is to use a single-ended operational amplifier as an input buffer before the high-speed fully differential amplifier to perform impedance switching. This scheme attempts to... Figure 2 The simple structure is applied to higher-speed differential systems, but this introduces additional active components, and distortion introduced by the preceding single-ended op-amp is still unavoidable. At the same time, in order to process high-frequency large signals, the slew rate and large-signal bandwidth of this single-ended op-amp are required to be extremely high, resulting in difficult selection and high cost.

[0078] Figure 4 The input stage circuit 100 described in this application is shown, compared to Figures 1 to 3 The proposed solution, firstly, creates an independent "through path" in 50Ω input mode, where the signal directly enters the subsequent fully differential amplifier 13 via a switch, completely bypassing the preceding single-ended operational amplifier 16. This eliminates the harmonic distortion and noise introduced by the preceding operational amplifier in traditional solutions, allowing the system's total harmonic distortion and signal-to-noise ratio performance in 50Ω mode to approach the theoretical limits of the subsequent fully differential amplifier (FDA) and digital-to-analog converter (ADC).

[0079] Secondly, in high-impedance (e.g., 1MΩ) operating mode, a compensated passive attenuation network 15 composed of R1 / C1 / R2 / C2 is introduced before the operational amplifier (A1). This attenuation network 15 provides both a 1MΩ input impedance and attenuates the signal by a fixed proportion. Through the coordinated design of the pre-attenuation network 15 and the buffer stage of the operational amplifier 16, while ensuring megaohm-level input impedance, the requirements for the dynamic range of the operational amplifier 16 are significantly reduced, resolving the technical contradiction of balancing high speed and high impedance in traditional solutions.

[0080] Finally, by adopting a physically separated dual-path architecture and an impedance matching / signal conditioning function decoupled architecture, an adaptive front-end with both high-frequency, low-distortion and high-precision DC measurement capabilities is provided for the test device, effectively improving the overall performance and applicability of the test system.

[0081] One embodiment of this application provides a chip testing device, which is a relatively independent and specific physical entity or device, and has an input stage circuit encapsulated inside.

[0082] In one embodiment, the packaged input stage circuit can refer to the input stage circuit described above in this application, and the corresponding embodiments and effects will not be repeated here.

[0083] Specifically, the chip testing device can be exemplified as a tester, whose housing integrates the input stage circuit described above as the core motherboard, and is equipped with necessary power modules, heat dissipation units, and human-machine interfaces (such as touch screens, buttons, and status indicator lights). The front panel of the testing device is equipped with standardized test interfaces (such as flexible printed circuit board connectors or probe arrays) for direct connection to the object under test (such as the ribbon cable of an automotive screen). After the user starts the test process through the operating interface, the core motherboard automatically applies and measures signals to multiple test points on the object under test according to the working process of the test circuit described above, and presents the results on the interactive interface, thus forming a fully functional and easy-to-use independent device.

[0084] In summary, the input stage circuit and chip testing device provided in this application employ a physically separated dual-path architecture and an impedance matching / signal conditioning function decoupled architecture. On the one hand, in low-impedance operating mode, the signal is directly connected to the fully differential amplifier through a through-path, completely avoiding the harmonic distortion introduced by the buffer stage of the traditional single-ended op-amp. This allows the harmonic distortion performance and signal-to-noise ratio of the system in the high-frequency band to be directly determined by the high-performance fully differential amplifier, thereby significantly improving the testing accuracy. On the other hand, in high-impedance operating mode, by using a cascaded design between the pre-attenuation network and the operational amplifier, both high input impedance characteristics are ensured, and the dynamic range requirements of the subsequent operational amplifier signal processing are effectively reduced by the attenuation network, solving the strict requirements of traditional solutions for operational amplifier slew rate and large signal bandwidth. This dual-path parallel and functionally specialized design reduces the large signal bandwidth requirement of the input operational amplifier under high-frequency conditions.

[0085] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0086] The detailed descriptions listed above are merely specific descriptions of feasible implementation methods of this application and are not intended to limit the scope of protection of this application. All equivalent implementation methods or modifications made without departing from the spirit of the art of this application should be included within the scope of protection of this application.

Claims

1. An input stage circuit for driving a fully differential amplifier, the fully differential amplifier having an input terminal, characterized in that, The input stage circuit includes: Signal input terminal; The first path is configured to connect the signal input terminal directly to the input terminal of the fully differential amplifier; The second path includes at least a series attenuation network and an operational amplifier, wherein the attenuation network is connected to the signal input terminal and the output terminal of the operational amplifier is connected to the input terminal of the fully differential amplifier. A switching assembly, coupled between the signal input terminal and the fully differential amplifier, is configured to selectively conduct either the first path or the second path to connect the signal input terminal to the input terminal of the fully differential amplifier via the selected path.

2. The input stage circuit according to claim 1, characterized in that, The fully differential amplifier is configured to provide a preset low impedance value at its input.

3. The input stage circuit according to claim 1, characterized in that, The attenuation network includes a first part and a second part connected in series. The first part is connected to the signal input terminal, and one end of the second part is connected to the input terminal of the operational amplifier, while the other end is connected to a reference potential. The first part is used to establish high impedance and achieve voltage attenuation, while the second part is used to filter out high-frequency noise.

4. The input stage circuit according to claim 3, characterized in that, The first part includes a first resistor and a first capacitor connected in parallel, and the second part includes a second resistor and a second capacitor connected in parallel. The first resistor and the second resistor are configured such that the sum of their corresponding first resistance values ​​and second resistance values ​​is equal to a preset high impedance value, and the ratio of the first resistance value to the second resistance value is equal to the ratio of the second capacitance value of the second capacitor to the first capacitance value of the first capacitor.

5. The input stage circuit according to claim 4, characterized in that, The attenuation value of the attenuation network is set as the ratio of the first resistance value to the sum of the first resistance value and the second resistance value.

6. The input stage circuit according to claim 1, characterized in that, The operational amplifier is configured as a voltage follower.

7. The input stage circuit according to any one of claims 2 and 4, characterized in that, The preset high impedance value is 1 Mohm, and the preset low impedance value is 50 ohm.

8. The input stage circuit according to claim 1, characterized in that, The switching assembly includes a first switch and a second switch. The first switch is connected to the signal input terminal, and the second switch is connected to the input terminal of the fully differential amplifier. The first path and the second path are connected in parallel between the first switch and the second switch.

9. The input stage circuit according to claim 1, characterized in that, The first switch and / or the second switch are single-pole double-throw switches or relays.

10. A chip testing device, characterized in that, Includes the input stage circuit as described in any one of claims 1-9.

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