A zero adjustable programmable gain amplifier circuit

Abstract

The utility model discloses a programmable gain amplifier circuit of zero point adjustable relates to programmable gain amplifier field, including operational amplifier circuit and at least one sample and hold circuit, the input of operational amplifier in sample and hold circuit and operational amplifier circuit is connected, the sample and hold circuit is used for sampling reset signal VRST and exposure signal VEXP, and will generate the sample signal output to the input of operational amplifier after sampling, when the sample and hold circuit samples, the upper plate voltage of sampling capacitor in sample and hold circuit is configured to be in the input voltage range of operational amplifier, the operational amplifier circuit is used for generating amplification signal according to sample signal. The circuit can reduce output error, improve output precision.

Description

Technical Field

[0001] This utility model relates to the field of programmable gain amplifiers, and in particular to a zero-point adjustable programmable gain amplifier circuit. Background Technology

[0002] Figure 1 Figure -2 shows a prior art zero-point adjustable programmable gain amplifier and its timing diagram. Those skilled in the art will understand that during the sampling phase, when the S5 control signal is high, the S5 switch is closed, and the voltage at the VPIXEL terminal is sampled onto the positive capacitor array. At this time, the VPIXEL terminal voltage is the pixel's reset signal, commonly referred to as VRST. When the S1 control signal is high, the S1 switch is closed, and the VPIXEL terminal voltage is sampled onto the negative capacitor array. At this time, the VPIXEL voltage is the pixel's exposure signal, commonly referred to as VEXP. When the SAMPLE signal is high and the PGA_RST signal is low, the programmable gain amplifier is in the closed-loop amplification phase.

[0003] When the S5 control signal is high, the upper plates of the capacitors in the positive capacitor array are connected to the VPIXEL terminal (connected to VRST), and the lower plates of some capacitors CY are connected to VREF+. When the S5 signal transitions from high to low, all the lower plates of the positive capacitor array are grounded. Considering charge conservation, the voltage across the upper plates of the capacitors in the positive capacitor array becomes VRST﹣VREF+CY / (C1+C2+C3+C4). This voltage is generally high, much higher than the common-mode voltage VCM, and can easily exceed the op-amp's input voltage range. When the SAMPLE signal is high, the upper plates of the capacitors in the positive capacitor array are connected to the op-amp's input, and all the lower plates are grounded. When the S1 control signal is high, the upper plates of the capacitors in the negative capacitor array are connected to the VPIXEL terminal (connected to VEXP), and the lower plates of some capacitors CY are connected to VREF−. When the S1 control signal transitions from high to low, all the lower plates of the capacitors in the negative capacitor array are grounded. Considering charge conservation, the voltage across the upper plate of the capacitors in the negative capacitor array becomes VEXP﹣VREF﹣CY / (C1+C2+C3+C4). When the SAMPLE signal is high, the upper plates of the capacitors in the negative capacitor array are connected to the input of the op-amp, and the lower plates are all grounded. The voltage VEXP varies greatly, and when combined with the negative reference voltage VREF−, the common-mode voltage at the op-amp input varies significantly. CY specifically refers to the capacitor whose lower plate is connected to the reference voltage (VREF+ and VREF﹣). If both RANGE0 and RANGE1 switches are open, then CY=0; if RANGE0 switch is closed and RANGE1 switch is open, then CY=C2; if RANGE0 switch is open and RANGE1 switch is closed, then CY=C3; if both RANGE0 and RANGE1 switches are closed, then CY=C2+C3. Figure 1 The switching states of Range0B and Range1B are opposite to those of RANGE0 and RANGE1.

[0004] As explained above, the problem with existing programmable gain amplifiers is that the common-mode voltage at the op-amp input varies significantly during amplification, potentially exceeding the op-amp's usable common-mode input range. Even if the op-amp has a high common-mode rejection ratio (CMRR), its CMRR is always finite, and large variations in the common-mode input can cause non-negligible errors in the differential output. Utility Model Content

[0005] In response to the aforementioned problems and technical requirements, the applicant has proposed a zero-point adjustable programmable gain amplifier circuit.

[0006] The technical solution of this utility model is as follows: A zero-point adjustable programmable gain amplifier circuit includes an operational amplifier circuit and at least one sample-and-hold circuit, wherein the sample-and-hold circuit is connected to the input terminal of the operational amplifier in the operational amplifier circuit. The sample-and-hold circuit is used to sample the reset signal VRST and the exposure signal VEXP, and outputs the sampled signal generated after sampling to the input terminal of the operational amplifier. When the sample-and-hold circuit performs sampling, the voltage of the upper plate of the sampling capacitor in the sample-and-hold circuit is configured to be within the input voltage range of the operational amplifier. The operational amplifier circuit is used to generate an amplified signal based on the sampled signal.

[0007] A further technical solution is that the sample-and-hold circuit includes capacitors C1, C2, C3, C4, C1', C2', C3', C4', switch S5, switch S1, switch SAMPLE01, switch SAMPLE02, switch SAMPLE03, and switch SAMPLE04, wherein... The upper plate of capacitor C1 is connected to one end of switch S5, the upper plate of capacitor C1' is connected to one end of switch S1, the other ends of switch S1 and switch S5 are both connected to the common-mode voltage VCM of operational amplifier, the upper plate of capacitor C1 is connected to the upper plates of capacitors C2, C3 and C4, and the upper plate of capacitor C1' is connected to the upper plates of capacitors C2', C3' and C4'. The lower plate of capacitor C1 is connected to the lower plate of capacitor C1' via switch SAMPLE01; the lower plate of capacitor C2 is connected to the lower plate of capacitor C2' via switch SAMPLE02; the lower plate of capacitor C3 is connected to the lower plate of capacitor C3' via switch SAMPLE03; and the lower plate of capacitor C4 is connected to the lower plate of capacitor C4' via switch SAMPLE04.

[0008] A further technical solution is that the sample-and-hold circuit further includes switches RANGE01, RANGE02, RANGE11, RANGE12, S5D1, S5D2, S1D, and S1B, wherein... One end of switch S5D2 is connected to the lower plate of capacitor C1, and one end of switch S1D is connected to the lower plate of capacitor C1'; one end of switch RANGE01 is connected to the lower plate of capacitor C2, and one end of switch RANGE11 is connected to the lower plate of capacitor C3; the lower plate of capacitor C4, the other end of switch RANGE01 and switch RANGE11 are connected to one end of switch S5D1, and the other end of switch S5D1 is connected to the VREF+ terminal; One end of switch RANGE02 is connected to the lower plate of capacitor C2', one end of switch RANGE12 is connected to the lower plate of capacitor C3', the lower plate of capacitor C4', switch RANGE02, and the other end of switch RANGE12 are connected to one end of switch S1B, and the other end of switch S1B is connected to the VREF- terminal; the VREF+ terminal is connected to a positive reference voltage V. REF+ The VREF- terminal is connected to a negative reference voltage V. REF -.

[0009] A further technical solution is that the other end of the switch S5D2 and the other end of the switch S1D are both connected to the VPIXEL terminal; Alternatively, the other end of switch S5D2 may be connected to the VRST terminal, and the other end of switch S1D may be connected to the VEXP terminal.

[0010] A further technical solution is that, when the zero-point adjustable programmable gain amplifier circuit includes multiple sample-and-hold circuits, the sample-and-hold circuit further includes switches SAMPLE1 and SAMPLE2, wherein... One end of switch SAMPLE1 is connected to the upper plate of capacitor C1, and the other end of switch SAMPLE1 is connected to the non-inverting input of the operational amplifier in the operational amplifier circuit. One end of switch SAMPLE2 is connected to the upper plate of capacitor C1', and the other end of switch SAMPLE2 is connected to the inverting input of the operational amplifier in the operational amplifier circuit.

[0011] A further technical solution is that switch S1B is controlled by control signal S1B, and switches S5D1 and S5D2 are controlled by control signal S5D; switch S1 is controlled by control signal S1, and switch S5 is controlled by control signal S5; switches SAMPLE01, SAMPLE02, SAMPLE03, SAMPLE04, SAMPLE1, and SAMPLE2 are controlled by control signal SAMPLE.

[0012] A further technical solution is that the operational amplifier circuit includes an operational amplifier, capacitors C5, C6, C7, C5', C6', C7', switches RANGE03, RANGE04, RANGE13, RANGE14, PGA_RST1, and PGA_RST2, wherein... The inverting output terminal of the operational amplifier is connected to one end of capacitors C5, C6, and C7 and switch PGA_RST1. The other end of capacitor C7 is connected to one end of switch RANGE13. The other end of capacitor C6 is connected to one end of switch RANGE03. The other ends of switches PGA_RST1, RANGE13, RANGE03, and capacitor C5 are connected to the non-inverting input terminal of the operational amplifier. The non-inverting output terminal of the operational amplifier is connected to one end of capacitors C5', C6', C7', and switch PGA_RST2. The other end of capacitor C7' is connected to one end of switch RANGE14, and the other end of capacitor C6' is connected to one end of switch RANGE04. The other ends of switches PGA_RST2, RANGE14, RANGE04, and capacitor C5' are connected to the inverting input terminal of the operational amplifier.

[0013] A further technical solution is that switches RANGE01, RANGE02, RANGE03, and RANGE04 are controlled by control signal RANGE0; switches RANGE11, RANGE12, RANGE13, and RANGE14 are controlled by control signal RANGE1; and switches PGA_RST1 and PGA_RST2 are controlled by control signal PGA_RST. The control signal S1B is the inverted signal of the control signal S1; the zero-point adjustable programmable gain amplifier circuit includes a sampling phase and an amplification phase when it is working. During the sampling phase, when the control signal SAMPLE remains low and the control signal PGA_RST remains high, and the control signals S5 and S5D are high while the control signals S1 and S1D are low, the sample-and-hold circuit samples the reset signal VRST. When the control signals S5 and S5D are low while the control signals S1 and S1D are high, the sample-and-hold circuit samples the exposure signal VEXP. In the amplified phase, the control signal SAMPLE is high, the control signal PGA_RST is low, and the control signals S5, S5D, S1, and S1D are low. The operational amplifier circuit generates the amplified signal based on the sampled signal.

[0014] A further technical solution is that the capacitance values ​​of capacitors C1 and C1' are both... C1 The capacitance values ​​of capacitors C2 and C2' are both... C2 The capacitance values ​​of capacitors C3 and C3' are both C3 The capacitance values ​​of capacitors C4 and C4' are bothC4 The capacitance values ​​of capacitors C5 and C5' are both C5 The capacitance values ​​of capacitors C6 and C6' are both C6 The capacitance values ​​of capacitors C7 and C7' are both... C7 .

[0015] A further technical solution is that the amplified signal V OUT It can be represented as:

[0016] Among them, V OP The voltage at the non-inverting output terminal of the operational amplifier, V ON This is the voltage at the inverting output terminal of the operational amplifier. CX It is a negative feedback capacitor. CY Reference capacitor; When both control signal RANGE0 and control signal RANGE1 are low level CX = CY =0; When the control signal RANGE0 is high and the control signal RANGE1 is low... CX = C6 , CY=C2 When the control signal RANGE0 is low and the control signal RANGE1 is high, CX = C7 , CY=C3 ; When both control signal RANGE0 and control signal RANGE1 are high level CX = C6 + C7 , CY = C2 + C3 .

[0017] The beneficial technical effects of this utility model are: The zero-point adjustable programmable gain amplifier circuit provided by this utility model eliminates the common-mode voltage variation at the input terminal of the operational amplifier in the operational amplifier circuit by optimizing the circuit structure of the sample-and-hold circuit. This eliminates the error caused by drastic changes in the common-mode voltage. Under the sampling phase, the voltage at the input terminal of the operational amplifier is maintained at the common-mode voltage VCM, ensuring that it will not exceed the input voltage range of the operational amplifier. Attached Figure Description

[0018] Figure 1 This is a circuit schematic of a programmable gain amplifier circuit with adjustable zero point in the prior art.

[0019] Figure 2This is the timing diagram of a programmable gain amplifier circuit with adjustable zero point in the prior art.

[0020] Figure 3 This is a circuit schematic diagram of Embodiment 1 of the zero-point adjustable programmable gain amplifier circuit provided by this utility model.

[0021] Figure 4 This is a signal timing diagram of Embodiment 1 of the zero-point adjustable programmable gain amplifier circuit provided by this utility model.

[0022] Figure 5 This is a circuit schematic diagram of Embodiment 2 of the zero-point adjustable programmable gain amplifier circuit provided by this utility model.

[0023] Figure 6 This is a circuit schematic diagram of Embodiment 3 of the zero-point adjustable programmable gain amplifier circuit provided by this utility model.

[0024] Figure 7 This is a circuit schematic diagram of Embodiment 4 of the programmable gain amplifier circuit with zero-point adjustable provided by this utility model.

[0025] Figure 8 This is a circuit schematic diagram of Embodiment 5 of the zero-point adjustable programmable gain amplifier circuit provided by this utility model. Detailed Implementation

[0026] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0027] This invention provides a zero-point adjustable programmable gain amplifier circuit, including an operational amplifier circuit and at least one sample-and-hold circuit. The sample-and-hold circuit is connected to the input terminal of the operational amplifier in the operational amplifier circuit. The sample-and-hold circuit is used to sample the reset signal VRST and the exposure signal VEXP, and outputs the sampled signal generated after sampling to the input terminal of the operational amplifier. When the sample-and-hold circuit performs sampling, the voltage of the upper plate of the sampling capacitor in the sample-and-hold circuit is configured to be within the input voltage range of the operational amplifier. The operational amplifier circuit is used to generate an amplified signal based on the sampled signal.

[0028] Example 1 For details, please refer to Figure 3In Embodiment 1, a sample-and-hold circuit is provided. The sample-and-hold circuit includes capacitors C1, C2, C3, C4, C1', C2', C3', and C4', as well as switches S5, S1, SAMPLE01, SAMPLE02, SAMPLE03, and SAMPLE04. The upper plate of capacitor C1 is connected to one end of switch S5, the upper plate of capacitor C1' is connected to one end of switch S1, the other ends of switch S1 and switch S5 are both connected to the common-mode voltage VCM of operational amplifier, the upper plate of capacitor C1 is connected to the upper plates of capacitors C2, C3 and C4, and the upper plate of capacitor C1' is connected to the upper plates of capacitors C2', C3' and C4'. The lower plate of capacitor C1 is connected to the lower plate of capacitor C1' via switch SAMPLE01; the lower plate of capacitor C2 is connected to the lower plate of capacitor C2' via switch SAMPLE02; the lower plate of capacitor C3 is connected to the lower plate of capacitor C3' via switch SAMPLE03; and the lower plate of capacitor C4 is connected to the lower plate of capacitor C4' via switch SAMPLE04.

[0029] The sample-and-hold circuit further includes switches RANGE01, RANGE02, RANGE11, RANGE12, S5D1, S5D2, S1D, and S1B, wherein... One end of switch S5D2 is connected to the other end of capacitor C1, and one end of switch S1D is connected to the lower plate of capacitor C1'. One end of switch RANGE01 is connected to the other end of capacitor C2, and one end of switch RANGE11 is connected to the lower plate of capacitor C3. The other ends of capacitor C4, switch RANGE01, and switch RANGE11 are connected to one end of switch S5D1, and the other end of switch S5D1 is connected to the VREF+ terminal. One end of switch RANGE02 is connected to the other end of capacitor C2', and one end of switch RANGE12 is connected to the other end of capacitor C3'. The other ends of capacitor C4', switch RANGE02, and switch RANGE12 are connected to one end of switch S1B, and the other end of switch S1B is connected to the VREF- terminal. The VREF+ terminal is connected to the positive reference voltage VREF+, and the VREF- terminal is connected to the negative reference voltage VREF-.

[0030] The sampling capacitors in the sample-and-hold circuit refer to capacitors C1-C4 and C1'-C4'. In Embodiment 1, the other end of switch S5D2 and the other end of switch S1D are both connected to the VPIXEL terminal. Specifically, switch S1B is controlled by control signal S1B, and switches S5D1 and S5D2 are controlled by control signal S5D; switch S1 is controlled by control signal S1, and switch S5 is controlled by control signal S5; switches SAMPLE01, SAMPLE02, SAMPLE03, and SAMPLE04 are controlled by control signal SAMPLE.

[0031] The control signal S1B is the inverted signal of the control signal S1; the zero-point adjustable programmable gain amplifier circuit includes a sampling phase and an amplification phase when it is working. Please refer to Figure 4 In the sampling phase, the control signal SAMPLE remains low and the control signal PGA_RST remains high. First, in the first sampling phase, control signals S5 and S5D are high, and control signals S1 and S1D are low. At this time, the VPIXEL terminal is connected to the reset signal VRST, and the sample-and-hold circuit samples the reset signal VRST. The sampled reset signal VRST is sampled to the lower plate of capacitor C1, and the voltage of the upper plate of capacitor C1 is the common-mode voltage VCM. Subsequently, in the second sampling phase, when control signals S5 and S5D are low and control signals S1 and S1D are high, the VPIXEL terminal is connected to the exposure signal VEXP, and the sample-and-hold circuit samples the exposure signal VEXP. The sampled exposure signal VEXP is sampled to the lower plate of capacitor C1', and the voltage of the upper plate of capacitor C1' is the common-mode voltage VCM. Therefore, in the sampling phase, the voltage at the input terminal of the operational amplifier circuit will remain at VCM, ensuring that it will not exceed the input voltage range of the operational amplifier. Specifically, in the first sampling phase, control signal S5 changes before control signal S5D. After control signal S5 becomes high / low, control signal S5D becomes high / low after a preset delay. In the second sampling phase, control signal S1 changes before control signal S1D. After control signal S1 becomes high / low, control signal S1D becomes high / low after a preset delay.

[0032] Furthermore, the operational amplifier circuit includes an operational amplifier, capacitors C5, C6, C7, C5', C6', C7', switches RANGE03, RANGE04, RANGE13, RANGE14, PGA_RST1, and PGA_RST2, wherein... The inverting output terminal of the operational amplifier is connected to one end of capacitors C5, C6, and C7 and switch PGA_RST1. The other end of capacitor C7 is connected to one end of switch RANGE13. The other end of capacitor C6 is connected to one end of switch RANGE03. The other ends of switches PGA_RST1, RANGE13, RANGE03, and capacitor C5 are connected to the non-inverting input terminal of the operational amplifier. The non-inverting output terminal of the operational amplifier is connected to one end of capacitors C5', C6', C7', and switch PGA_RST2. The other end of capacitor C7' is connected to one end of switch RANGE14, and the other end of capacitor C6' is connected to one end of switch RANGE04. The other ends of switches PGA_RST2, RANGE14, RANGE04, and capacitor C5' are connected to the inverting input terminal of the operational amplifier.

[0033] The switches RANGE01, RANGE02, RANGE03 and RANGE04 are controlled by the control signal RANGE0; the switches RANGE11, RANGE12, RANGE13 and RANGE14 are controlled by the control signal RANGE1; and the switches PGA_RST1 and PGA_RST2 are controlled by the control signal PGA_RST. In the amplified phase, the control signal SAMPLE is high, the control signal PGA_RST is low, and the control signals S5, S5D, S1, and S1D are low. The operational amplifier circuit generates the amplified signal based on the sampled signal.

[0034] Specifically, the capacitance values ​​of capacitor C1 and capacitor C1' are both C1 The capacitance values ​​of capacitors C2 and C2' are both... C2 The capacitance values ​​of capacitors C3 and C3' are both C3 The capacitance values ​​of capacitors C4 and C4' are both C4 The capacitance values ​​of capacitors C5 and C5' are both C5 The capacitance values ​​of capacitors C6 and C6' are both C6 The capacitance values ​​of capacitors C7 and C7' are both... C7 .

[0035] The amplified signal V OUT It can be represented as:

[0036] Among them, V OP The voltage at the non-inverting output terminal of the operational amplifier, V ONThis is the voltage at the inverting output terminal of the operational amplifier. CX It is a negative feedback capacitor. CY This is the reference capacitor. When VEXP = VRST, V OUT The zero point can be adjusted by the second term in the above formula.

[0037] CX , CY Control can be achieved through control signals RANGE0 and RANGE1. Specifically, when both control signals RANGE0 and RANGE1 are low, CX = CY =0; when the control signal RANGE0 is high and the control signal RANGE1 is low. CX = C6 , CY=C2 When the control signal RANGE0 is low and the control signal RANGE1 is high, CX = C7 , CY=C3 When both control signal RANGE0 and control signal RANGE1 are high, CX = C6 + C7 , CY = C2 + C3 .

[0038] Example 2 The difference between Example 2 and Example 1 is as follows, please refer to... Figure 5 The sample-and-hold circuit further includes switches SAMPLE1 and SAMPLE2. One end of switch SAMPLE1 is connected to the upper plate of capacitor C1, and the other end of switch SAMPLE1 is connected to the non-inverting input of the operational amplifier in the operational amplifier circuit. One end of switch SAMPLE2 is connected to the upper plate of capacitor C1', and the other end of switch SAMPLE2 is connected to the inverting input of the operational amplifier in the operational amplifier circuit. Both switches SAMPLE1 and SAMPLE2 are controlled by the control signal SAMPLE. With switches SAMPLE1-2, the sample-and-hold circuit isolates the sampling phase from the operational amplifier input through switches SAMPLE1-2 controlled by the SAMPLE signal. Therefore, when the sample-and-hold circuit has switches SAMPLE1-2, the zero-point adjustable programmable gain amplifier circuit can include multiple sample-and-hold circuits, with multiple channel sample-and-hold circuits sharing a single operational amplifier circuit.

[0039] Example 3 like Figure 6As shown, the difference between Embodiment 3 and Embodiment 2 is that the zero-point adjustable programmable gain amplifier circuit includes three sample-and-hold circuits, which share a single operational amplifier circuit. The operating principles of the sample-and-hold circuit and the operational amplifier circuit are consistent with those described above. It should be noted that when the zero-point adjustable programmable gain amplifier circuit includes multiple sample-and-hold circuits, the control signals SAMPLE used by these circuits are differentiated. Taking Embodiment 3 as an example, control signals SAMPLE1, SAMPLE2, and SAMPLE3 are set for the three sample-and-hold circuits. When the amplified signal is generated using the sampled signal output by one of the sample-and-hold circuits during the amplification phase, the control signal SAMPLE corresponding to that sample-and-hold circuit is pulled high, while the control signals SAMPLE corresponding to the other two sample-and-hold circuits remain low. Simultaneously, the control signal PGA_RST is set low to achieve selection of the three sample-and-hold circuits.

[0040] Example 4 Furthermore, in practical applications, the VPIXEL terminal of the sample-and-hold circuit described in Embodiment 2 can be divided into a VRST terminal and a VEXP terminal, as follows: Figure 7 As shown, when the VPIXEL terminal is divided into the VRST terminal and the VEXP terminal, the other end of the switch S5D2 is connected to the VRST terminal, and the other end of the switch S1D is connected to the VEXP terminal. The VRST terminal is connected to the reset signal VRST in the first sampling phase, and the VEXP terminal is connected to the exposure signal VEXP in the second sampling phase.

[0041] Example 5 Furthermore, such as Figure 8 As shown, the zero-point adjustable programmable gain amplifier circuit can also be configured with multiple sample-and-hold circuits as described in Embodiment 4, so that multiple sample-and-hold circuits can share a single operational amplifier circuit. The operating principle of the programmable gain amplifier circuit with multiple sample-and-hold circuits is consistent with the above, and will not be repeated here.

[0042] In the description of this specification, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0043] The use of terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0044] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A zero-point adjustable programmable gain amplifier circuit, characterized in that, It includes an operational amplifier circuit and at least one sample-and-hold circuit, wherein the sample-and-hold circuit is connected to the input terminal of the operational amplifier in the operational amplifier circuit; The sample-and-hold circuit is used to sample the reset signal VRST and the exposure signal VEXP, and outputs the sampled signal generated after sampling to the input terminal of the operational amplifier. When the sample-and-hold circuit performs sampling, the voltage of the upper plate of the sampling capacitor in the sample-and-hold circuit is configured to be within the input voltage range of the operational amplifier. The operational amplifier circuit is used to generate an amplified signal based on the sampled signal.

2. The zero-point adjustable programmable gain amplifier circuit according to claim 1, characterized in that, The sample-and-hold circuit includes capacitors C1, C2, C3, C4, C1', C2', C3', C4', switch S5, switch S1, switch SAMPLE01, switch SAMPLE02, switch SAMPLE03, and switch SAMPLE04, wherein... The upper plate of capacitor C1 is connected to one end of switch S5, the upper plate of capacitor C1' is connected to one end of switch S1, the other ends of switch S1 and switch S5 are both connected to the common-mode voltage VCM of operational amplifier, the upper plate of capacitor C1 is connected to the upper plates of capacitors C2, C3 and C4, and the upper plate of capacitor C1' is connected to the upper plates of capacitors C2', C3' and C4'. The lower plate of capacitor C1 is connected to the lower plate of capacitor C1' via switch SAMPLE01; the lower plate of capacitor C2 is connected to the lower plate of capacitor C2' via switch SAMPLE02; the lower plate of capacitor C3 is connected to the lower plate of capacitor C3' via switch SAMPLE03; and the lower plate of capacitor C4 is connected to the lower plate of capacitor C4' via switch SAMPLE04.

3. The zero-point adjustable programmable gain amplifier circuit according to claim 2, characterized in that, The sample-and-hold circuit further includes switches RANGE01, RANGE02, RANGE11, RANGE12, S5D1, S5D2, S1D, and S1B, wherein... One end of switch S5D2 is connected to the lower plate of capacitor C1, and one end of switch S1D is connected to the lower plate of capacitor C1'; one end of switch RANGE01 is connected to the lower plate of capacitor C2, and one end of switch RANGE11 is connected to the lower plate of capacitor C3; the lower plate of capacitor C4, the other end of switch RANGE01 and switch RANGE11 are connected to one end of switch S5D1, and the other end of switch S5D1 is connected to the VREF+ terminal; One end of switch RANGE02 is connected to the lower plate of capacitor C2', one end of switch RANGE12 is connected to the lower plate of capacitor C3', the lower plate of capacitor C4', switch RANGE02, and the other end of switch RANGE12 are connected to one end of switch S1B, and the other end of switch S1B is connected to the VREF- terminal; the VREF+ terminal is connected to a positive reference voltage V. REF+ The VREF- terminal is connected to a negative reference voltage V. REF -.

4. The zero-point adjustable programmable gain amplifier circuit according to claim 3, characterized in that, The other end of switch S5D2 and the other end of switch S1D are both connected to the VPIXEL terminal; Alternatively, the other end of switch S5D2 may be connected to the VRST terminal, and the other end of switch S1D may be connected to the VEXP terminal.

5. The zero-point adjustable programmable gain amplifier circuit according to claim 4, characterized in that, When the zero-point adjustable programmable gain amplifier circuit includes multiple sample-and-hold circuits, the sample-and-hold circuit further includes switches SAMPLE1 and SAMPLE2, wherein... One end of switch SAMPLE1 is connected to the upper plate of capacitor C1, and the other end of switch SAMPLE1 is connected to the non-inverting input of the operational amplifier in the operational amplifier circuit. One end of switch SAMPLE2 is connected to the upper plate of capacitor C1', and the other end of switch SAMPLE2 is connected to the inverting input of the operational amplifier in the operational amplifier circuit.

6. The zero-point adjustable programmable gain amplifier circuit according to claim 5, characterized in that, The switch S1B is controlled by the control signal S1B, and the switches S5D1 and S5D2 are controlled by the control signal S5D; the switch S1 is controlled by the control signal S1, and the switch S5 is controlled by the control signal S5; the switches SAMPLE01, SAMPLE02, SAMPLE03, SAMPLE04, SAMPLE1, and SAMPLE2 are controlled by the control signal SAMPLE.

7. The zero-point adjustable programmable gain amplifier circuit according to claim 6, characterized in that, The operational amplifier circuit includes an operational amplifier, capacitors C5, C6, C7, C5', C6', C7', RANGE03, RANGE04, RANGE13, RANGE14, PGA_RST1, and PGA_RST2, wherein... The inverting output terminal of the operational amplifier is connected to one end of capacitors C5, C6, and C7 and switch PGA_RST1. The other end of capacitor C7 is connected to one end of switch RANGE13. The other end of capacitor C6 is connected to one end of switch RANGE03. The other ends of switches PGA_RST1, RANGE13, RANGE03, and capacitor C5 are connected to the non-inverting input terminal of the operational amplifier. The non-inverting output terminal of the operational amplifier is connected to one end of capacitors C5', C6', C7', and switch PGA_RST2. The other end of capacitor C7' is connected to one end of switch RANGE14, and the other end of capacitor C6' is connected to one end of switch RANGE04. The other ends of switches PGA_RST2, RANGE14, RANGE04, and capacitor C5' are connected to the inverting input terminal of the operational amplifier.

8. The zero-point adjustable programmable gain amplifier circuit according to claim 7, characterized in that, The switches RANGE01, RANGE02, RANGE03 and RANGE04 are controlled by the control signal RANGE0; the switches RANGE11, RANGE12, RANGE13 and RANGE14 are controlled by the control signal RANGE1; and the switches PGA_RST1 and PGA_RST2 are controlled by the control signal PGA_RST. The control signal S1B is the inverted signal of the control signal S1; the zero-point adjustable programmable gain amplifier circuit includes a sampling phase and an amplification phase when it is working. During the sampling phase, when the control signal SAMPLE remains low and the control signal PGA_RST remains high, and the control signals S5 and S5D are high while the control signals S1 and S1D are low, the sample-and-hold circuit samples the reset signal VRST. When the control signals S5 and S5D are low while the control signals S1 and S1D are high, the sample-and-hold circuit samples the exposure signal VEXP. In the amplified phase, the control signal SAMPLE is high, the control signal PGA_RST is low, and the control signals S5, S5D, S1, and S1D are low. The operational amplifier circuit generates the amplified signal based on the sampled signal.

9. The zero-point adjustable programmable gain amplifier circuit according to claim 8, characterized in that, The capacitance values ​​of capacitors C1 and C1' are both C1 The capacitance values ​​of capacitors C2 and C2' are both... C2 The capacitance values ​​of capacitors C3 and C3' are both C3 The capacitance values ​​of capacitors C4 and C4' are both C4 The capacitance values ​​of capacitors C5 and C5' are both C5 The capacitance values ​​of capacitors C6 and C6' are both C6 The capacitance values ​​of capacitors C7 and C7' are both C7 .

10. The zero-point adjustable programmable gain amplifier circuit according to claim 8, characterized in that, The amplified signal V OUT It can be represented as: Among them, V OP The voltage at the non-inverting output terminal of the operational amplifier, V ON This is the voltage at the inverting output terminal of the operational amplifier. CX It is a negative feedback capacitor. CY Reference capacitor; When both control signal RANGE0 and control signal RANGE1 are low level CX = CY =0; When the control signal RANGE0 is high and the control signal RANGE1 is low... CX = C6 , CY=C2 When the control signal RANGE0 is low and the control signal RANGE1 is high, CX = C7 , CY=C3 ; When both control signal RANGE0 and control signal RANGE1 are high level CX = C6 + C7 , CY = C2 + C3 .

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