A buffer circuit

Abstract

The utility model discloses an embodiment of buffer circuit. The buffer circuit includes: capacitor module and follower module, wherein, one end of capacitor module inputs first voltage, the other end of capacitor module and the first input end of follower module are electrically connected, the second input end of follower module inputs target signal, the power end of follower module inputs second voltage, and the first output end and the second output end of follower module output two signals respectively, capacitor module includes capacitor and switch unit, and the capacitance of capacitor module is adjustable. The buffer circuit provided by the utility model embodiment can improve the power supply rejection ratio and the common mode rejection ratio of input of buffer circuit.

Description

Technical Field

[0001] This utility model relates to buffer technology, and more particularly to a buffer circuit. Background Technology

[0002] Buffers, such as those in differential amplifier circuits, isolate the input signal source from the internal bias resistor network, preventing the signal source impedance from affecting the accuracy of common-mode rejection ratio (CMRR) and differential-mode gain calculations. Currently, existing buffer circuits suffer from low power supply rejection ratio (PSRR) and input PSRR. Utility Model Content

[0003] This utility model provides a buffer circuit to improve the power supply rejection ratio and the input common-mode rejection ratio of the buffer circuit.

[0004] This utility model embodiment provides a buffer circuit, including: a capacitor module and a follower module;

[0005] The capacitor module has a first voltage input at one end, and the other end of the capacitor module is electrically connected to the first input terminal of the follower module. The second input terminal of the follower module receives the target signal, and the power supply terminal of the follower module receives the second voltage. The first and second output terminals of the follower module output two signals respectively. The capacitor module includes a capacitor and a switching unit, and the capacitance value of the capacitor module is adjustable.

[0006] Optionally, the follower module includes a first follower and a second follower. The first follower includes a first current source and a first MOSFET, and the second follower includes a second current source and a second MOSFET. The second voltage is input to the input terminals of the first and second current sources. The output terminal of the first current source is electrically connected to the first terminal of the first MOSFET, and the output terminal of the second current source is electrically connected to the first terminal of the second MOSFET. The second terminals of both the first and second MOSFETs are grounded. The gates of the first and second MOSFETs serve as the first and second input terminals of the follower module, respectively. The first terminals of the first and second MOSFETs serve as the first and second output terminals of the follower module, respectively.

[0007] Optionally, both the first MOSFET and the second MOSFET are PMOS transistors.

[0008] Optionally, the first terminal of the first MOSFET and the first terminal of the second MOSFET are both sources, and the first follower and the second follower are both source followers.

[0009] Optionally, the capacitor module includes multiple parallel branches, each branch including a capacitor, and the multiple branches including an electrically connected capacitor and a switching unit.

[0010] Optionally, the switching unit includes an inverter, a first switching transistor, and a second switching transistor; the control terminal of the first switching transistor is electrically connected to the output terminal of the inverter, the input terminal of the inverter receives a control signal, the power supply terminal of the inverter receives the second voltage, the control terminal of the second switching transistor receives the control signal, the first terminals of the first and second switching transistors are both electrically connected to the capacitor, the second terminal of the first switching transistor is electrically connected to the first input terminal of the follower module, and the second terminal of the second switching transistor is grounded.

[0011] Optionally, the inverter includes a third current source, a third switch, and a fourth switch. The input terminal of the third current source receives the second voltage, the output terminal of the third current source is electrically connected to the first terminal of the fourth switch, the second terminal of the fourth switch is electrically connected to the first terminal of the third switch, the second terminal of the third switch is grounded, the control terminal of the third switch and the control terminal of the fourth switch receive the control signal, the first terminal of the third switch is electrically connected to the control terminal of the first switch, and the second terminal of the third switch is electrically connected to the control terminal of the first switch through a capacitor.

[0012] Optionally, the first switch, the second switch, and the third switch are all NMOS, and the fourth switch is a PMOS.

[0013] Optionally, the capacitance value of each of the branches is different.

[0014] Optionally, the target signal is a sound pressure signal generated by a microphone.

[0015] The buffer circuit provided in this embodiment includes a capacitor module and a follower module. One end of the capacitor module receives a first voltage, and the other end is electrically connected to the first input terminal of the follower module. The second input terminal of the follower module receives a target signal, and the power supply terminal of the follower module receives a second voltage. The first and second output terminals of the follower module output two signals respectively. The capacitor module includes a capacitor and a switching unit, and the capacitance value of the capacitor module is adjustable. The buffer circuit provided in this embodiment forms a pseudo-differential input by inputting signals through the first and second input terminals of the follower module. This solves the problem of low power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) in existing buffer circuits that use single-ended input and single-ended output, effectively improving the PSRR and CMRR of the buffer circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a buffer circuit provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the structure of a switching unit provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, not the entire structure.

[0019] Current condenser silicon microphone technology utilizes the collaborative operation of MEMS (Micro Electro Mechanical System) devices and ASICs (Application Specific Integrated Circuits) to convert the capacitance changes of MEMS devices caused by sound pressure into electrical signals, which are then converted into high-quality digital or analog signals by the ASIC. Since the output from the MEMS is a high-impedance signal without driving capability, a buffer circuit is needed between the MEMS device and the readout circuit of the ASIC. Traditional buffer circuits used for MEMS and ASIC readout circuits typically employ a single-ended input, single-ended output source follower structure. Their power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) are low. Power supply noise and ripple from the charge pump providing high voltage between the two MEMS plates are effectively transferred to the signal chain of the ASIC readout circuit, ultimately becoming output noise and affecting the overall signal-to-noise ratio of the system.

[0020] Based on this, the present invention provides a buffer circuit, which can be a pseudo-differential input buffer circuit applied to a silicon microphone ASIC, in order to reduce the impact of noise on the buffer power supply and charge pump output ripple on the system output signal-to-noise ratio. Figure 1 This is a schematic diagram of a buffer circuit provided in an embodiment of this utility model. (Reference) Figure 1 The buffer circuit includes a capacitor module 10 and a follower module 20. One end of the capacitor module 10 is input with a first voltage VBIAS, and the other end of the capacitor module 10 is electrically connected to the first input terminal of the follower module 20. The second input terminal of the follower module 20 is input with a target signal, the power supply terminal of the follower module 20 is input with a second voltage VDD, and the first and second output terminals of the follower module 20 output two signals VON and VOP, respectively. The capacitor module 10 includes a capacitor 11 and a switching unit 12, and the capacitance value of the capacitor module 10 is adjustable.

[0021] Specifically, when the buffer circuit is working, a first voltage VBIAS is input to one end of the capacitor module 10. The first voltage VBIAS is transmitted to the first input terminal of the follower module 20 through the capacitor module 10, and also to the microelectromechanical system (MEMS), thus forming a pseudo-differential signal. The capacitance value of the capacitor module 10 can be adjusted according to the capacitance of the MEMS. The MEMS outputs the target signal to the second input terminal of the follower module 20, the first output terminal of the follower module 20 outputs the signal VON, and the second output terminal of the follower module 20 outputs the signal VOP.

[0022] The buffer circuit provided in this embodiment includes a capacitor module and a follower module. One end of the capacitor module receives a first voltage, and the other end is electrically connected to the first input terminal of the follower module. The second input terminal of the follower module receives a target signal, and the power supply terminal of the follower module receives a second voltage. The first and second output terminals of the follower module output two signals respectively. The capacitor module includes a capacitor and a switching unit, and the capacitance value of the capacitor module is adjustable. The buffer circuit provided in this embodiment forms a pseudo-differential input by inputting signals through the first and second input terminals of the follower module. This solves the problem of low power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) in existing buffer circuits that use single-ended input and single-ended output, effectively improving the PSRR and CMRR of the buffer circuit.

[0023] Optionally, the follower module 20 includes a first follower 21 and a second follower 22. The first follower 21 includes a first current source IB1 and a first MOSFET M1, and the second follower 22 includes a second current source IB2 and a second MOSFET M2. A second voltage VDD is input to the input terminal of the first current source IB1 and the input terminal of the second current source IB2. The output terminal of the first current source IB1 is electrically connected to the first terminal of the first MOSFET M1, and the output terminal of the second current source IB2 is electrically connected to the first terminal of the second MOSFET M2. The second terminals of the first MOSFET M1 and the second MOSFET M2 are both grounded. The gate of the first MOSFET M1 and the gate of the second MOSFET M2 serve as the first input terminal and the second input terminal of the follower module, respectively. The first terminal of the first MOSFET M1 and the first terminal of the second MOSFET M2 serve as the first output terminal and the second output terminal of the follower module, respectively.

[0024] The first current source IB1 outputs a signal VON, which is the first gate transmission signal VON of the first MOSFET M1, and also the output signal VON of the first follower 21. Furthermore, the first gate transmission signal VON of the first MOSFET M1 is the signal input to the gate of the first MOSFET M1, i.e., the voltage signal transmitted from the capacitor module 10 to the gate of the first MOSFET M1, and also the signal input to the first follower 21, thus enabling the signal output by the first follower 21 to follow its own input signal. The second current source IB2 outputs a signal VOP, which is the first gate transmission signal VOP of the second MOSFET M2, and also the output signal VOP of the second follower 22. Furthermore, the first gate transmission signal VOP of the second MOSFET M2 is the target signal input to the gate of the second MOSFET M2, and also the signal input to the second follower 22, thus enabling the signal output by the second follower 22 to follow its own input signal.

[0025] Furthermore, taking the target signal transmitted by the aforementioned microelectromechanical system (MEMS) as an example, when the MEMS detects a change in external sound pressure, it converts the sound pressure into a change in the MEMS capacitance, ΔC, and inputs it to the gate of the second MOSFET M2. The input signal, i.e., the voltage of the target signal, is proportional to ΔC × VBIAS. The signal VON output by the first follower 21 and the signal VOP output by the second follower 22 can be transmitted to a pseudo-differential programmable gain amplifier for amplification, then quantized by an analog-to-digital converter, and finally output in the form of PDM (Pulse Density Modulation) code. The first voltage VBIAS can be generated by a charge pump circuit. This voltage provides an electrostatic field between the diaphragm and the backplate of the MEMS and is also input to the capacitor module, thereby forming a pseudo-differential signal.

[0026] Optionally, both the first MOSFET M1 and the second MOSFET M2 are PMOS transistors.

[0027] Specifically, when a high-level signal (or low-level signal) is input to the gate of the first MOSFET, the first MOSFET is turned on (off); when a high-level signal (or low-level signal) is input to the gate of the second MOSFET, the second MOSFET is turned on (off). When the buffer circuit is working, when a high-level signal is input to the gate of the first MOSFET, the first MOSFET is turned on; when a high-level signal is input to the gate of the second MOSFET, the second MOSFET is turned on, so that the first follower 21 outputs signal VON and the second follower 22 outputs signal VOP.

[0028] Optionally, the first terminal of the first MOSFET M1 and the first terminal of the second MOSFET M2 are both sources, and the first follower 21 and the second follower 22 are both source followers.

[0029] Specifically, in the first follower 21, the source-transmitted signal VON of the first MOSFET M1 follows the signal input to the gate of the first MOSFET M1; similarly, in the second follower 22, the source-transmitted signal VOP of the second MOSFET M2 follows the signal input to the gate of the second MOSFET M2. Furthermore, the source follower has high input impedance and low output impedance. By using a fixed current source to bias the source follower, complete tracking of the gate and source inputs and outputs of the MOSFETs can be achieved.

[0030] refer to Figure 1 Optionally, the capacitor module 10 includes multiple parallel branches, each branch including a capacitor, and the multiple branches including electrically connected capacitors and switching units.

[0031] For example, the capacitor module 10 includes five parallel branches, one of which has a capacitor, and each of the other four parallel branches has a capacitor and a switching unit. The capacitors C0, C1, C2, C3, and C4 are located in the five branches respectively, and the branches where the capacitors C1, C2, C3, and C4 are located have switching units SW1, SW2, SW3, and SW4 respectively. Specifically, when the buffer circuit is working, all of the switching units SW1, SW2, SW3, and SW4 are open or at least one is on. When all of the switching units SW1, SW2, SW3, and SW4 are open, the capacitance value of the capacitor module 10 is the capacitance value of capacitor C0. When at least one of the switching units SW1, SW2, SW3, and SW4 is on, the capacitance value of the capacitor module 10 is the capacitance value of capacitor C0 in parallel with the capacitance of the branch where the on-circuit switching unit is located. That is, the capacitance value of the capacitor module 10 is the capacitance value in parallel with the branch with a capacitor but no switching unit and the branch with a switching unit and on. The on and off of the branch is achieved by switching the units on and off, thereby making the capacitance value of the capacitor module 10 adjustable.

[0032] Figure 2 This is a schematic diagram of the structure of a switching unit provided in an embodiment of this utility model. (Reference) Figure 2 Optionally, the switching unit includes an inverter 11, a first switching transistor Q1, and a second switching transistor Q2. The control terminal of the first switching transistor Q1 is electrically connected to the output terminal of the inverter 11, the input terminal of the inverter 11 receives a control signal VC, the power supply terminal of the inverter 11 receives a second voltage VDD, the control terminal of the second switching transistor Q2 receives a control signal VC, the first terminal of the first switching transistor Q1 and the first terminal of the second switching transistor Q2 are both electrically connected to a capacitor, the second terminal of the first switching transistor Q1 is electrically connected to the first input terminal of the follower module, and the second terminal of the second switching transistor Q2 is grounded.

[0033] The control signal VC is a level signal, such as a high-level signal or a low-level signal. For example, when the control signal VC is high, the gate of the second switch Q2 is high, and the second switch Q2 is turned on. The control signal VC is converted to a low-level signal by an inverter, and the gate of the first switch Q1 is low, so the first switch Q1 is turned off. At this time, the branch containing the capacitor connected to the first switch Q1 is open. Taking the first switch Q1 connected to capacitor C1 as an example, when the first switch Q1 is turned off, the branch containing capacitor C1 connected to the first switch Q1 is open. For example, when the control signal VC is low, the first switch Q1 is turned on, and the second switch Q2 is turned off. At this time, the branch containing the capacitor connected to the first switch Q1 is turned on. Taking the first switch Q1 connected to capacitor C1 as an example, when the first switch Q1 is turned on, the branch containing capacitor C1 connected to the first switch Q1 is turned on. The capacitance value of the capacitor module is related to the capacitor C1 connected to the first switch Q1. The control signal VC of different switching units can be the same or different, so as to adjust the capacitance value of the capacitor module through the control signal VC.

[0034] Furthermore, combined Figure 1 and Figure 2 The second terminal of the first switching transistor Q1 is electrically connected to the gate of the first MOSFET M1 through port B. All switching units have the same structure. Taking switching unit SW1 as an example, the first terminal of both the first switching transistor Q1 and the first terminal of the second switching transistor Q2 are electrically connected to capacitor C1 through port A. An inverter makes the gate voltage level of the first switching transistor Q1 opposite to the gate voltage level of the second switching transistor Q2. The function of the second switching transistor Q2 is to provide a ground potential to port A when the first switching transistor Q1 is off. Since port A is in a high-impedance state when the first switching transistor Q1 is off, and a voltage VBIAS is applied through the capacitor, port A is at an unknown potential. Excessive voltage at port A could potentially damage the first switching transistor Q1. Therefore, by providing a ground potential to port A when the first switching transistor Q1 is off, the second switching transistor Q2 prevents excessive voltage at port A from damaging the first switching transistor Q1.

[0035] refer to Figure 2 Optionally, the inverter 11 includes a third current source IB3, a third switch Q3, and a fourth switch Q4. The input terminal of the third current source IB3 is input with a second voltage. The output terminal of the third current source IB3 is electrically connected to the first terminal of the fourth switch Q4. The second terminal of the fourth switch Q4 is electrically connected to the first terminal of the third switch Q3. The second terminal of the third switch Q3 is grounded. The control terminals of the third switch Q3 and the fourth switch Q4 are input with a control signal VC. The first terminal of the third switch Q3 is electrically connected to the control terminal of the first switch Q1. The second terminal of the third switch Q3 is electrically connected to the control terminal of the first switch Q1 through a capacitor CL.

[0036] Specifically, the third switch Q3 and the fourth switch Q4 are different types of switches. When the control terminal of the third switch Q3 and the control terminal of the fourth switch Q4 are input with the control signal VC, one of them is turned on and the other is turned off. For example, the third switch Q3 is an NMOS and the fourth switch Q4 is a PMOS. When the control signal VC is high, the third switch Q3 is turned on and the fourth switch Q4 is turned off. The output of the inverter, i.e., the first terminal of the third switch Q3, is a low-level signal, which is also the signal at the control terminal of the first switch Q1. Thus, the inverter's inversion function is achieved through the third switch Q3 and the fourth switch Q4, so that when the input of the inverter is high, the output is low. When the control signal VC is low, the third switch Q3 is off and the fourth switch Q4 is on. The output of the inverter, i.e., the first terminal of the third switch Q3, is a high-level signal, which is also the signal at the control terminal of the first switch Q1. Thus, the inverter's inversion function is achieved through the third switch Q3 and the fourth switch Q4, so that when the input of the inverter is low, the output is high.

[0037] For example, the inverter is a current-biased inverter. The current-biased inverter can precisely control the drive current of the inverter. The capacitor CL connected after it can control the charging time of the capacitor CL on the one hand, and reduce the charge injection effect at port A when the first switch Q1 is turned on, thereby reducing noise.

[0038] Optionally, the first switch Q1, the second switch Q2, and the third switch Q3 are all NMOS, and the fourth switch Q4 is a PMOS.

[0039] Specifically, when the control signal VC is high, since the gates of the second switch Q2, the third switch Q3, and the fourth switch Q4 all receive the control signal VC, the second switch Q2 is turned on, the third switch Q3 is turned on, and the fourth switch Q4 is turned off. Since the gate of the first switch Q1 is electrically connected to the first terminal of the third switch Q3, and the first terminal of the third switch Q3 is electrically connected to the second terminal of the fourth switch Q4, and the second terminal of the third switch Q3 is grounded, the gate of the first switch Q1 is low, and the first switch Q1 is turned off. This causes the high-level control signal input to the inverter to be output as a low-level signal through the inverter. When the control signal VC is low, since the gates of the second switch Q2, the third switch Q3, and the fourth switch Q4 all receive the control signal VC, the second switch Q2 is off, the third switch Q3 is off, and the fourth switch Q4 is on. Since the gate of the first switch Q1 is electrically connected to the first terminal of the third switch Q3, the first terminal of the third switch Q3 is electrically connected to the second terminal of the fourth switch Q4, and the first terminal of the fourth switch Q4 is electrically connected to the third current source, the gate of the first switch Q1 is high, and the first switch Q1 is on. This causes the low-level control signal input to the inverter to be output as a high-level signal through the inverter.

[0040] Furthermore, all switching transistors are MOSFETs. MOSFETs have extremely high input impedance and very low drive requirements. The gate and channel of a MOSFET are isolated by an insulating layer, theoretically consuming almost no gate current; only a voltage signal is needed to control the on / off state. MOSFETs have a simple structure and high integration. MOSFETs do not require PN junction isolation, simplifying the manufacturing process and allowing for extremely small unit sizes, reducing the footprint. MOSFETs exhibit outstanding low-power characteristics. Enhancement-mode MOSFETs have almost zero drain current in the off state, resulting in extremely low static power consumption. The CMOS structure (NMOS + PMOS complementarity) only has instantaneous on-current during switching, and dynamic power consumption can be further reduced through voltage and frequency optimization. MOSFETs have fast switching speeds and excellent high-frequency performance. MOSFETs are unipolar devices (conducting only by majority carriers), with no minority carrier storage effect, and switching speeds can reach nanosecond levels (some high-frequency models can reach picosecond levels). MOSFETs come in a wide variety of types, offering broad adaptability. Different types can be selected based on requirements, such as NMOS (electron-conducting) and PMOS (hole-conducting); enhancement-mode (default cutoff) and depletion-mode (default on); covering the entire spectrum from low-voltage small-signal applications to high-voltage high-power applications. MOSFETs exhibit good thermal stability. Their on-resistance increases with temperature, possessing a negative temperature coefficient (as current increases, heat generates resistance, inhibiting further current increase), making them less prone to thermal runaway damage and more reliable in high-power circuits. Therefore, MOSFETs possess characteristics such as high input impedance, ultra-high integration, low power consumption, high-speed switching, flexible types, and good thermal stability, making them suitable for use as switching units in capacitor modules of buffer circuits. Additionally, the first switching transistor Q1 has a gate-drain capacitance Cgd between its gate and drain.

[0041] Optionally, the capacitance value of each branch can be different.

[0042] For details, please refer to Figure 2 The capacitor module 10 includes five parallel branches. In one embodiment, the capacitance range of the capacitor module 10 is 0.5pF-2.75pF. For example, capacitor C0 is 0.5pF, capacitor C1 is 0.15pF, capacitor C2 is 0.3pF, capacitor C3 is 0.6pF, and capacitor C4 is 1.2pF. Then, the capacitance values ​​of each branch of the capacitor module 10 are 0.5pF, 0.15pF, 0.3pF, 0.6pF, and 1.2pF, respectively. When the switching units of the branches containing capacitors C1-C4 are all open, the capacitance value of the capacitor module 10 is the capacitance value of capacitor C0, which is 0.5pF. When the switching units of the branches containing capacitors C1-C4 are all closed, the capacitance value of the capacitor module 10 is the capacitance value of capacitors C0-C4 connected in parallel, which is 2.75pF. Thus, the various capacitance values ​​of the capacitor module 10 can be adjusted by using different capacitance values ​​for each branch.

[0043] Optionally, the target signal is the sound pressure level signal generated by the microphone.

[0044] Specifically, the buffer circuit is applied to a condenser silicon microphone within a microelectromechanical system (MEMS). The sound pressure level signal generated by the silicon microphone is transmitted from the MEMS to one input of a follower in the buffer circuit, and the output signal of the buffer circuit is transmitted to the silicon microphone readout circuit. The buffer circuit achieves a power supply rejection ratio (PSRR) of approximately 70-80 dB, and the ripple of the charge pump output of the silicon microphone, i.e., the voltage VBIAS, can suppress noise in the buffer circuit by approximately 30-40 dB. This significantly reduces noise in the signal chain of the silicon microphone system and improves the overall signal-to-noise ratio (SNR) of the system output.

[0045] It should be noted that the values ​​of each parameter in this embodiment can be determined according to the actual circuit requirements, and are not limited here.

[0046] The buffer circuit provided in this embodiment includes a capacitor module and a follower module. One end of the capacitor module receives a first voltage, and the other end is electrically connected to the first input terminal of the follower module. The second input terminal of the follower module receives a target signal, and the power supply terminal receives a second voltage. The first and second output terminals of the follower module output two signals respectively. The capacitor module includes a capacitor and a switching unit, and the capacitance value of the capacitor module is adjustable. The follower module includes a first follower and a second follower. The first follower includes a first current source and a first MOSFET, and the second follower includes a second current source and a second MOSFET. The capacitor module includes multiple parallel branches, each including a capacitor, and the multiple branches include electrically connected capacitors and switching units. The switching unit includes an inverter, a first switching transistor, and a second switching transistor. The inverter includes a third current source, a third switching transistor, and a fourth switching transistor. The buffer circuit provided in this embodiment forms a pseudo-differential input through the first and second input terminals of the follower module, i.e., the source of the first MOSFET and the source of the second MOSFET. This effectively improves the power supply rejection ratio and the common-mode rejection ratio of the buffer circuit, and reduces noise. Furthermore, the capacitor module can achieve adjustable capacitance value through the switching unit to meet actual needs. The switching unit provides a control signal to the first switching transistor in the switching unit through an inverter to achieve signal inversion. On the one hand, this reduces the noise caused by charge injection when the switching transistor is turned on. On the other hand, when the first switching transistor is turned off, the second switching transistor provides a potential to the capacitor in the capacitor module connected to the first switching transistor through the conduction of the second switching transistor, thereby improving the reliability of the circuit.

[0047] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, rearrangements, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A buffer circuit, characterized in that, include: Capacitor modules and follower modules; The capacitor module has a first voltage input at one end, and the other end of the capacitor module is electrically connected to the first input terminal of the follower module. The second input terminal of the follower module receives the target signal, and the power supply terminal of the follower module receives the second voltage. The first and second output terminals of the follower module output two signals respectively. The capacitor module includes a capacitor and a switching unit, and the capacitance value of the capacitor module is adjustable.

2. The buffer circuit according to claim 1, characterized in that, The follower module includes a first follower and a second follower. The first follower includes a first current source and a first MOSFET, and the second follower includes a second current source and a second MOSFET. The second voltage is input to the input terminals of the first and second current sources. The output terminal of the first current source is electrically connected to the first terminal of the first MOSFET, and the output terminal of the second current source is electrically connected to the first terminal of the second MOSFET. The second terminals of both the first and second MOSFETs are grounded. The gates of the first and second MOSFETs serve as the first and second input terminals of the follower module, respectively. The first terminals of the first and second MOSFETs serve as the first and second output terminals of the follower module, respectively.

3. The buffer circuit according to claim 2, characterized in that, Both the first MOSFET and the second MOSFET are PMOS transistors.

4. The buffer circuit according to claim 2, characterized in that, The first terminal of the first MOSFET and the first terminal of the second MOSFET are both sources, and the first follower and the second follower are both source followers.

5. The buffer circuit according to claim 1, characterized in that, The capacitor module includes multiple parallel branches, each branch including a capacitor, and the multiple branches including an electrically connected capacitor and a switching unit.

6. The buffer circuit according to claim 5, characterized in that, The switching unit includes an inverter, a first switching transistor, and a second switching transistor. The control terminal of the first switching transistor is electrically connected to the output terminal of the inverter. The input terminal of the inverter receives a control signal, the power supply terminal of the inverter receives the second voltage, and the control terminal of the second switching transistor receives the control signal. The first terminals of both the first and second switching transistors are electrically connected to the capacitor. The second terminal of the first switching transistor is electrically connected to the first input terminal of the follower module, and the second terminal of the second switching transistor is grounded.

7. The buffer circuit according to claim 6, characterized in that, The inverter includes a third current source, a third switch, and a fourth switch. The input terminal of the third current source receives the second voltage, and the output terminal of the third current source is electrically connected to the first terminal of the fourth switch. The second terminal of the fourth switch is electrically connected to the first terminal of the third switch, and the second terminal of the third switch is grounded. The control terminal of the third switch and the control terminal of the fourth switch receive the control signal. The first terminal of the third switch is electrically connected to the control terminal of the first switch, and the second terminal of the third switch is electrically connected to the control terminal of the first switch through a capacitor.

8. The buffer circuit according to claim 7, characterized in that, The first switch, the second switch, and the third switch are all NMOS, and the fourth switch is a PMOS.

9. The buffer circuit according to claim 5, characterized in that, The capacitance value is different for each of the branches.

10. The buffer circuit according to claim 1, characterized in that, The target signal is the sound pressure signal generated by the microphone.

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