A small digital train number antenna

Abstract

The utility model discloses a small -size digitization car number antenna belongs to railway car number identification technical field, including radio frequency module, decoding module, magnetic steel signal processing module, processor module and network interface module, radio frequency module is connected with processor module and decoding module respectively, decoding module is connected with processor module, magnetic steel signal processing module is connected with processor module, processor module is connected with network interface module, the utility model solves the problem that the existing railway car number automatic identification system maintains frequently and digitization deficiency.

Description

Technical Field

[0001] This utility model belongs to the field of railway vehicle number recognition technology, and in particular relates to a small digital vehicle number antenna. Background Technology

[0002] Traditional railway automatic vehicle number identification systems employ a distributed structure. The vehicle number antenna is installed inside the track using a clip-on method, while the main unit is located in a machine room. The antenna and main unit are connected via a coaxial cable. This installation method requires on-site personnel assistance during track maintenance machinery operations, as the antenna needs to be disassembled and reinstalled after the machinery work is completed.

[0003] With the development of railways, the number of automatic train number identification systems is increasing, and the operation of these systems in conjunction with track maintenance machinery is becoming more frequent. This results in maintenance personnel needing to spend a significant amount of time coordinating these operations, increasing their workload and creating potential safety hazards for road traffic. As technology advances and user needs evolve, existing automatic train number identification systems are struggling to meet the demands for digitalization, networking, miniaturization, and disassembly-free operation. Utility Model Content

[0004] In view of the above-mentioned shortcomings in the existing technology, the present invention provides a small digital vehicle number antenna, which solves the problems of frequent maintenance and insufficient digitalization in the existing railway vehicle number automatic identification system.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this utility model is as follows: RF module, decoding module, magnet signal processing module, processor module, and network interface module; The radio frequency module is connected to both the processor module and the decoding module; the decoding module is connected to the processor module; the magnet signal processing module is connected to the processor module; and the processor module is connected to the network interface module.

[0006] Preferably, the radio frequency module includes a radio frequency local oscillator module, a power amplification and mixing submodule, and an intermediate frequency bandpass filter submodule connected in sequence; the radio frequency local oscillator module is connected to the processor module; and the intermediate frequency bandpass filter submodule is connected to the decoding module.

[0007] Preferably, the radio frequency local oscillator module includes a first chip U10 of model HMC821LP6CE, a second chip U1 of model SCN-2-11+, capacitors C125, C149, C150, C152, inductors L131 and L133. Pin 28 of the first chip U10 is connected to one end of capacitor C152 and one end of inductor L31; the other end of inductor L31 is connected to the positive terminal of capacitor C150, one end of capacitor C125, one end of capacitor C149, and one end of inductor L133; the negative terminal of capacitor C150 is connected to the other end of capacitor C125 and the other end of capacitor C149, and is grounded; the other end of inductor L133 is connected to an external power supply VCC_PLL; the other end of capacitor C152 is connected to pin 2 of the second chip U1; pin 4 of the second chip U1 serves as the output terminal of the phase-locked loop source and is connected to the power amplifier and mixer submodule; pin 6 of the second chip U1 serves as the output terminal of the local oscillator source and is connected to the power amplifier and mixer submodule; pins 30, 31, 32, and 33 of the first chip U10 serve as local oscillator frequency control terminals and are all connected to the processor module.

[0008] Preferably, the power amplification and mixing submodule includes capacitor C10, a third chip U3 of model ADL5611, inductor L4, capacitors C9, C8, and C7, resistor R12, grounding capacitor C6, inductor L3, capacitor C11, a fourth chip U2 of model RA03M8894M, capacitor C12, a fifth chip W2 of model LFCN-1000+, a sixth chip U4 of model RCP890A10, capacitor C1, antenna J1, inductor L13, a seventh chip W3 and an eighth chip W4 of model LFCN-1000+, capacitor C2, resistors R15, R16, and R17, capacitor C34, grounding capacitor C32, a ninth chip U6 of model LT5575EUF, capacitors C24, C25, C33, and C35; One end of capacitor C10 serves as the source receiver of the phase-locked loop and is connected to pin 4 of the second chip U1; the other end of capacitor C10 is connected to pin 1 of the third chip U3; pin 3 of the third chip U3 is connected to one end of capacitor C11 and one end of inductor L4; the other end of inductor L4 is connected to one end of capacitor C9, one end of capacitor C8, one end of capacitor C7, and one end of resistor R12; the other end of capacitor C9 is connected to the other ends of capacitor C8 and capacitor C7, and grounded; the other end of resistor R12 is connected to one end of inductor L3 and grounded capacitor C6; the other end of inductor L3 is connected to an external power supply VCC_RF. The other end of capacitor C11 is connected to pin 1 of the fourth chip U2; pin 4 of the fourth chip U2 is connected to one end of capacitor C12; the other end of capacitor C12 is connected to pin 1 of the fifth chip W2; pin 3 of the fifth chip W2 is connected to pin 2 of the sixth chip U4; pin 1 of the sixth chip U4 is connected to one end of capacitor C1; the other end of capacitor C1 is connected to antenna J1 to receive FM signals of 910~914MHz; pin 0 of the sixth chip U4 is connected to one end of inductor L13 and grounded; pin 4 of the sixth chip U4 is connected to the other end of inductor L13 and pin 1 of the seventh chip W3, respectively. Connections: Pin 3 of the seventh chip W3 is connected to pin 1 of the eighth chip W4; pin 3 of the eighth chip W4 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to one end of resistor R15 and one end of resistor R17; the other end of resistor R17 is connected to one end of resistor R16 and grounded; the other end of resistor R15 is connected to the other end of resistor R16 and one end of capacitor C34; the other end of capacitor C34 is connected to pin 2 of the ninth chip U6 and grounded capacitor C32; pin 10 of the ninth chip U6 is connected to one end of capacitor C33 and one end of capacitor C35; the other end of capacitor C33... The first pin serves as the local oscillator receiver and is connected to pin 6 of the second chip U1; pin 11 of the ninth chip U6 is connected to the other end of capacitor C35; pin 13 of the ninth chip U6 is connected to one end of capacitor C25 and serves as the QN output; pin 14 of the ninth chip U6 is connected to the other end of capacitor C25 and serves as the QP output; pin 15 of the ninth chip U6 is connected to one end of capacitor C24 and serves as the IN output; pin 16 of the ninth chip U6 is connected to the other end of capacitor C24 and serves as the IP output; the QN, QP, IN, and IP outputs are all connected to the intermediate frequency bandpass filter submodule.

[0009] Preferably, the intermediate frequency bandpass filter submodule includes a tenth chip U12 of model THS4522, resistor R51, capacitor C66, resistor R52, capacitor C67, capacitor C61, capacitor C71, capacitor C72, capacitor C62, resistor R54, resistor R48, capacitor C70, resistor R53, capacitor C69, capacitor C64, resistor R43, capacitor C65, resistor R50, capacitor C63, capacitor C73, resistor R58, capacitor C81, capacitor C74, capacitor C77, capacitor C78, ​​capacitor C87, resistor R59, resistor R66, capacitor C79, resistor R60, capacitor C76, capacitor C85, resistor R65, capacitor C75, resistor R57, capacitor C76, and capacitor C86; One end of resistor R51 serves as the QN input terminal and is connected to one end of capacitor C25; the other end of resistor R51 is connected to one end of capacitor C66; the other end of capacitor C66 is connected to one end of resistor R52, one end of capacitor C67, and one end of capacitor C61 respectively; the other end of resistor R52 is connected to one end of capacitor C71, one end of capacitor C72, and one end of capacitor C62 respectively; the other end of capacitor C71 is connected to one end of resistor R54; the other end of resistor R54 serves as the QP input terminal and is connected to the other end of capacitor C25; the other end of capacitor C72 is connected to pin 3 of the tenth chip U12 and one end of resistor R48 respectively; the other end of resistor R48 is connected to... The other end of capacitor C62, pin 14 of the tenth chip U12, and one end of capacitor C70 are connected; the other end of capacitor C70 is connected to one end of resistor R53; the other end of resistor R53 is connected to one end of capacitor C69 and one end of capacitor C64, respectively, as the QinP output terminal; the other end of capacitor C67 is connected to pin 2 of the tenth chip U12 and one end of resistor R43, respectively; the other end of resistor R43 is connected to the other end of capacitor C61, pin 15 of the tenth chip U12, and one end of capacitor C65, respectively; the other end of capacitor C65 is connected to one end of resistor R50; the other end of resistor R50 is connected to the other end of capacitor C69 and one end of capacitor C63, and... As the QinN output terminal; the other end of capacitor C63 is connected to the other end of capacitor C64 and grounded; one end of resistor R56 serves as the IN input terminal and is connected to one end of capacitor C24; the other end of resistor R56 is connected to one end of capacitor C73; the other end of capacitor C73 is connected to one end of resistor R58, one end of capacitor C81, and one end of capacitor C74 respectively; the other end of resistor R58 is connected to one end of capacitor C77, one end of capacitor C78, ​​and one end of capacitor C87 respectively; the other end of capacitor C77 is connected to one end of resistor R59; the other end of resistor R59 serves as the IP input terminal and is connected to the other end of capacitor C24; the other end of capacitor C78 is connected to the tenth Pin 7 of chip U12 is connected to one end of resistor R66; the other end of resistor R66 is connected to the other end of capacitor C87, pin 10 of chip U12, and one end of capacitor C79; the other end of capacitor C79 is connected to one end of resistor R60; the other end of resistor R60 is connected to one end of capacitor C76 and one end of capacitor C85, and serves as the IINP output terminal; the other end of capacitor C81 is connected to one end of resistor R65, pin 11 of chip U12, and one end of capacitor C75; the other end of resistor R65 is connected to the other end of capacitor C74 and pin 6 of chip U12; the other end of capacitor C75 is connected to one end of resistor R57.The other end of resistor R57 is connected to one end of capacitor C76 and one end of capacitor C86, respectively, and serves as the IINN output terminal; the other end of capacitor C86 is connected to the other end of capacitor C85 and grounded; the Qinn, Qinp, IINN, and IINP output terminals are all connected to the decoding module.

[0010] Preferably, the decoding module includes an analog-to-digital conversion submodule and an FPGA submodule connected to the analog-to-digital conversion submodule; the analog-to-digital conversion submodule is connected to an intermediate frequency bandpass filter submodule; and the FPGA submodule is connected to a processor module. The analog-to-digital conversion submodule includes the eleventh chip U7 (model ADS1220), resistors R34, R35, R36, and R37, and capacitors C91 and C92. One end of resistor R34 serves as the IN input terminal and is connected to one end of capacitor C86; the other end of resistor R34 is connected to pin 16 of the eleventh chip U7 and one end of capacitor C91; the other end of capacitor C91 is connected to one end of resistor R35 and pin 15 of the eleventh chip U7; the other end of resistor R35 serves as the IP input terminal and is connected to one end of capacitor C85; one end of resistor R36 serves as the QN input terminal and is connected to one end of capacitor C63; the other end of resistor R36 is connected to pin 16 of the eleventh chip U7 and one end of capacitor C91; Pin 5 of chip U7 is connected to one end of capacitor C92; the other end of capacitor C92 is connected to one end of resistor R37 and pin 6 of chip U7; the other end of resistor R37 serves as the QP input terminal and is connected to one end of capacitor C64; pins 11, 12, 10, and 9 of chip U7 serve as the B15L10N, B15L10P, B15L7N, and B15L7P output terminals respectively, and are all connected to the FPGA submodule. The FPGA submodule includes the twelfth chip U11A (model XC7A100T-1CSG324I), the thirteenth chip U11B (model XC7A35T-1CSG324I), resistors R4 and R5, the fourteenth chip U30 (model W25Q128), resistors R18, R19, and R20. The K17, K18, L14, M14, and L13 pins of the twelfth chip U11A are respectively used as QSPID0, QSPID1, QSPID2, QSPID3, and QSPICS terminals, and are all connected to the processor module. The B16, B17, B18, and A18 pins of the thirteenth chip U11B are respectively used as B15L7P, B15L7N, B15L10P, and B15L10N input terminals, and are connected to the 9th, 10th, 12th, and 11th pins of the eleventh chip U7. The C16 and C17 pins of the thirteenth chip U11B are connected to one end of resistor R4 and one end of resistor R5, respectively. The other end of resistor R4 serves as the FPGA. The TX terminal of the 14th chip U30 and the other end of resistor R5 serve as the RX terminal of the FPGA, both connected to the processor module. The first pin of the 14th chip U30 is connected to one end of resistor R20 and the L13 pin of the 13th chip U11B. The other end of resistor R20 is connected to an external power supply VCC3V3. The 5th and 2nd pins of the 14th chip U30 are connected to the K17 and K18 pins of the 13th chip U11B respectively. The 3rd pin of the 14th chip U30 is connected to one end of resistor R19 and the L14 pin of the 13th chip U11B. The other end of resistor R19 is connected to one end of resistor R18 and connected to an external power supply VCC3V3. The 7th pin of the 14th chip U30 is connected to the other end of resistor R18 and the M14 pin of the 13th chip U11B.

[0011] Preferably, the magnet signal processing module includes four identical magnet signal processing sub-modules; Each of the four magnet signal processing submodules includes resistor R104, capacitor C173, resistor R100, resistor R106, resistor R97, capacitor C166, grounding capacitor 180, capacitor C175, resistor R107, resistor 102, resistor R105, resistor R115, resistor R114, antenna TP7, bidirectional trigger diode D5 of model BAT54S, grounding capacitor C176, and fifteenth chip U27 and sixteenth chip U28 of model OPA197IDBVR. One end of resistor R104 is connected to one end of capacitor C173 and one end of resistor R100, serving as the CG+ terminal; the other end of resistor R104 is connected to the other end of capacitor C173 and one end of resistor R106, serving as the CG- terminal; the other end of resistor R100 is connected to one end of resistor R97, one end of capacitor C166, and pin 1 of the fifteenth chip U27; the other end of resistor R97 is connected to the other end of capacitor C166 and ground capacitor C180, and connected to external power supply VCC_Bias; the other end of resistor R106 is connected to pin 3 of the fifteenth chip U27, one end of capacitor C175, and one end of resistor R107; the other end of capacitor C175 is connected to resistor R104... The other end of resistor R102 is connected to pin 4 of the fifteenth chip U27; the other end of resistor R102 is connected to pin 1 of the sixteenth chip U28; pin 4 of the sixteenth chip U28 is connected to one end of resistor R105 and one end of resistor R115 respectively; the other end of resistor R115 is connected to pin 3 of the sixteenth chip U28 and one end of resistor R114 respectively; the other end of resistor R114 is grounded; the other end of resistor R105 is connected to antenna TP7, the third end of bidirectional trigger diode D5, and grounding capacitor C176 respectively, serving as the CGADC output terminal; the first end of bidirectional trigger diode D5 is grounded; the second end of bidirectional trigger diode D5 is connected to the external power supply VCC_MCU; The four magnet signal processing submodules have CGADC output terminals of CG1ADC, CG2ADC, CG3ADC and CG4ADC respectively, and are all connected to the processor module.

[0012] Preferably, the processor module includes the seventeenth chip U8 of model STM32F405RGT6 and the eighteenth chip U9 of model W25Q64; Pins 29, 53, 51, and 52 of the seventeenth chip U8 are connected to pins 30, 31, 32, and 33 of the first chip U10, respectively. Pins 42 and 43 of the seventeenth chip U8 are connected to the other ends of resistors R5 and R4, respectively. Pins 8, 9, 10, and 11 of the seventeenth chip U8 are connected to the CG1ADC output terminal, the CG2ADC output terminal, and the CG3ADC output terminal, respectively. The DC output terminal and the CG4ADC output terminal are connected one-to-one; pins 33, 34, 35, 36 and 37 of the seventeenth chip U8 are all connected to the network interface module; the eighteenth chip U9 is a serial data memory externally expanded by the seventeenth chip U8 through the SPI1 port; pins 1, 2, 5 and 6 of the eighteenth chip U9 are connected one-to-one with pins 24, 22, 23 and 21 of the seventeenth chip U8.

[0013] Preferably, the network interface module includes a nineteenth chip U17 of model W5550, resistors R63 and R66, capacitors C129 and C130, resistors R74 and R75, a twentieth chip U18 of model HR641680E, and an RJ45 terminal J7. Pins 32, 33, 34, 35, and 37 of the nineteenth chip U17 are connected one-to-one with pins 33, 34, 35, 36, and 37 of the seventeenth chip U8; pin 1 of the nineteenth chip U17 is connected to one end of resistor R63 and pin 3 of the twentieth chip U18; pin 2 of the nineteenth chip U17 is connected to one end of resistor R66 and pin 1 of the twentieth chip U18; the other ends of resistors R63 and R66 are connected and connected to an external power supply W55_VCCD; the nineteenth chip U17... Pin 5 of the 19th chip U17 is connected to one end of resistor R74 and one end of capacitor C129; the other end of capacitor C129 is connected to pin 8 of the 20th chip U18; pin 6 of the 19th chip U17 is connected to one end of resistor R74 and one end of capacitor C130; the other end of capacitor C130 is connected to pin 6 of the 20th chip U18; the other end of resistor R75 is connected to the other end of resistor R74; pins 9, 11, 14 and 16 of the 20th chip U18 are connected to pins 4, 3, 2 and 1 of RJ45 terminal J7 respectively.

[0014] The beneficial effects of this utility model are as follows: This utility model provides a small digital vehicle number antenna, which integrates a radio frequency module, a decoding module, a magnet signal processing module, a processor module, and a network interface module into the vehicle number antenna. It generates a message based on the received actual tag data with vehicle number information and the acquired and converted magnet digital signal with vehicle positioning information. The message is transmitted to a remote host computer through the network interface, so that the remote host computer can parse the received message to obtain the magnet waveform and vehicle number data, thereby performing axle counting, vehicle counting, speed measurement, and vehicle positioning. This utility model avoids frequent maintenance, requires no disassembly, and realizes highly digital and networked automatic identification of railway vehicle numbers.

[0015] Other advantages of this invention will be analyzed in more detail in the following embodiments. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a block diagram of a small digital vehicle number antenna according to an embodiment of the present invention.

[0018] Figure 2 This is a circuit diagram of the radio frequency local oscillator module in an embodiment of this utility model.

[0019] Figure 3 This is a circuit diagram of the power amplification and mixing submodule in an embodiment of the present invention.

[0020] Figure 4 This is a circuit diagram of the intermediate frequency bandpass filter submodule in an embodiment of this utility model.

[0021] Figure 5 This is a circuit diagram of the analog-to-digital conversion submodule in an embodiment of this utility model.

[0022] Figure 6 This is a schematic diagram of the first part of the FPGA submodule in an embodiment of this utility model.

[0023] Figure 7 This is a schematic diagram of the second part of the FPGA submodule in an embodiment of this utility model.

[0024] Figure 8 This is the circuit schematic diagram of the third part of the FPGA submodule in this embodiment of the present invention.

[0025] Figure 9 This is a circuit diagram of the magnet signal processing submodule in an embodiment of this utility model.

[0026] Figure 10 This is a circuit schematic diagram of the first part of the processor module in an embodiment of this utility model.

[0027] Figure 11 This is a circuit schematic diagram of the second part of the processor module in an embodiment of this utility model.

[0028] Figure 12 This is a schematic diagram of the first part of the network interface module in this embodiment of the present invention.

[0029] Figure 13 This is a circuit diagram of the second part of the network interface module in this embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0031] like Figure 1 As shown, in one embodiment of the present invention, the present invention provides a small digital vehicle number antenna, including a radio frequency module, a decoding module, a magnet signal processing module, a processor module and a network interface module; The radio frequency module is connected to both the processor module and the decoding module; the decoding module is connected to the processor module; the magnet signal processing module is connected to the processor module; and the processor module is connected to the network interface module.

[0032] The radio frequency module includes a radio frequency local oscillator module, a power amplification and mixing submodule, and an intermediate frequency bandpass filter submodule connected in sequence; the radio frequency local oscillator module is connected to the processor module; and the intermediate frequency bandpass filter submodule is connected to the decoding module.

[0033] like Figure 2As shown, the radio frequency local oscillator module includes a first chip U10 with model number HMC821LP6CE, a second chip U1 with model number SCN-2-11+, capacitors C125, C149, C150, C152, inductors L131 and L133. Pin 28 of the first chip U10 is connected to one end of capacitor C152 and one end of inductor L31; the other end of inductor L31 is connected to the positive terminal of capacitor C150, one end of capacitor C125, one end of capacitor C149, and one end of inductor L133; the negative terminal of capacitor C150 is connected to the other end of capacitor C125 and the other end of capacitor C149, and is grounded; the other end of inductor L133 is connected to an external power supply VCC_PLL; the other end of capacitor C152 is connected to pin 2 of the second chip U1; pin 4 of the second chip U1 serves as the output terminal of the phase-locked loop source and is connected to the power amplifier and mixer submodule; pin 6 of the second chip U1 serves as the output terminal of the local oscillator source and is connected to the power amplifier and mixer submodule; pins 30, 31, 32, and 33 of the first chip U10 serve as local oscillator frequency control terminals and are all connected to the processor module.

[0034] like Figure 3 As shown, the power amplification and mixing submodule includes capacitor C10, third chip U3 (model ADL5611), inductor L4, capacitors C9, C8, and C7, resistor R12, grounding capacitor C6, inductor L3, capacitor C11, fourth chip U2 (model RA03M8894M), capacitor C12, fifth chip W2 (model LFCN-1000+), sixth chip U4 (model RCP890A10), capacitor C1, antenna J1, inductor L13, seventh and eighth chips W3 and W4 (model LFCN-1000+), capacitor C2, resistors R15, R16, and R17, capacitor C34, grounding capacitor C32, ninth chip U6 (model LT5575EUF), capacitors C24, C25, C33, and C35; One end of capacitor C10 serves as the source receiver of the phase-locked loop and is connected to pin 4 of the second chip U1; the other end of capacitor C10 is connected to pin 1 of the third chip U3; pin 3 of the third chip U3 is connected to one end of capacitor C11 and one end of inductor L4; the other end of inductor L4 is connected to one end of capacitor C9, one end of capacitor C8, one end of capacitor C7, and one end of resistor R12; the other end of capacitor C9 is connected to the other ends of capacitor C8 and capacitor C7, and grounded; the other end of resistor R12 is connected to one end of inductor L3 and grounded capacitor C6; the other end of inductor L3 is connected to an external power supply VCC_RF. The other end of capacitor C11 is connected to pin 1 of the fourth chip U2; pin 4 of the fourth chip U2 is connected to one end of capacitor C12; the other end of capacitor C12 is connected to pin 1 of the fifth chip W2; pin 3 of the fifth chip W2 is connected to pin 2 of the sixth chip U4; pin 1 of the sixth chip U4 is connected to one end of capacitor C1; the other end of capacitor C1 is connected to antenna J1 to receive FM signals of 910~914MHz; pin 0 of the sixth chip U4 is connected to one end of inductor L13 and grounded; pin 4 of the sixth chip U4 is connected to the other end of inductor L13 and pin 1 of the seventh chip W3, respectively. Connections: Pin 3 of the seventh chip W3 is connected to pin 1 of the eighth chip W4; pin 3 of the eighth chip W4 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to one end of resistor R15 and one end of resistor R17; the other end of resistor R17 is connected to one end of resistor R16 and grounded; the other end of resistor R15 is connected to the other end of resistor R16 and one end of capacitor C34; the other end of capacitor C34 is connected to pin 2 of the ninth chip U6 and grounded capacitor C32; pin 10 of the ninth chip U6 is connected to one end of capacitor C33 and one end of capacitor C35; the other end of capacitor C33... The antenna J1 serves as the local oscillator receiver and is connected to pin 6 of the second chip U1; pin 11 of the ninth chip U6 is connected to the other end of capacitor C35; pin 13 of the ninth chip U6 is connected to one end of capacitor C25 and serves as the QN output; pin 14 of the ninth chip U6 is connected to the other end of capacitor C25 and serves as the QP output; pin 15 of the ninth chip U6 is connected to one end of capacitor C24 and serves as the IN output; pin 16 of the ninth chip U6 is connected to the other end of capacitor C24 and serves as the IP output; the QN, QP, IN, and IP outputs are all connected to the intermediate frequency bandpass filter submodule. In this scheme, the 910~914MHz FM signal received by antenna J1 contains vehicle number information.

[0035] like Figure 4 As shown, the intermediate frequency bandpass filter submodule includes the tenth chip U12 of model THS4522, resistor R51, capacitor C66, resistor R52, capacitor C67, capacitor C61, capacitor C71, capacitor C72, capacitor C62, resistor R54, resistor R48, capacitor C70, resistor R53, capacitor C69, capacitor C64, resistor R43, capacitor C65, resistor R50, capacitor C63, capacitor C73, resistor R58, capacitor C81, capacitor C74, capacitor C77, capacitor C78, ​​capacitor C87, resistor R59, resistor R66, capacitor C79, resistor R60, capacitor C76, capacitor C85, resistor R65, capacitor C75, resistor R57, capacitor C76, and capacitor C86; One end of resistor R51 serves as the QN input terminal and is connected to one end of capacitor C25; the other end of resistor R51 is connected to one end of capacitor C66; the other end of capacitor C66 is connected to one end of resistor R52, one end of capacitor C67, and one end of capacitor C61 respectively; the other end of resistor R52 is connected to one end of capacitor C71, one end of capacitor C72, and one end of capacitor C62 respectively; the other end of capacitor C71 is connected to one end of resistor R54; the other end of resistor R54 serves as the QP input terminal and is connected to the other end of capacitor C25; the other end of capacitor C72 is connected to pin 3 of the tenth chip U12 and one end of resistor R48 respectively; the other end of resistor R48 is connected to... The other end of capacitor C62, pin 14 of the tenth chip U12, and one end of capacitor C70 are connected; the other end of capacitor C70 is connected to one end of resistor R53; the other end of resistor R53 is connected to one end of capacitor C69 and one end of capacitor C64, respectively, as the QinP output terminal; the other end of capacitor C67 is connected to pin 2 of the tenth chip U12 and one end of resistor R43, respectively; the other end of resistor R43 is connected to the other end of capacitor C61, pin 15 of the tenth chip U12, and one end of capacitor C65, respectively; the other end of capacitor C65 is connected to one end of resistor R50; the other end of resistor R50 is connected to the other end of capacitor C69 and one end of capacitor C63, and... As the QinN output terminal; the other end of capacitor C63 is connected to the other end of capacitor C64 and grounded; one end of resistor R56 serves as the IN input terminal and is connected to one end of capacitor C24; the other end of resistor R56 is connected to one end of capacitor C73; the other end of capacitor C73 is connected to one end of resistor R58, one end of capacitor C81, and one end of capacitor C74 respectively; the other end of resistor R58 is connected to one end of capacitor C77, one end of capacitor C78, ​​and one end of capacitor C87 respectively; the other end of capacitor C77 is connected to one end of resistor R59; the other end of resistor R59 serves as the IP input terminal and is connected to the other end of capacitor C24; the other end of capacitor C78 is connected to the tenth Pin 7 of chip U12 is connected to one end of resistor R66; the other end of resistor R66 is connected to the other end of capacitor C87, pin 10 of chip U12, and one end of capacitor C79; the other end of capacitor C79 is connected to one end of resistor R60; the other end of resistor R60 is connected to one end of capacitor C76 and one end of capacitor C85, and serves as the IINP output terminal; the other end of capacitor C81 is connected to one end of resistor R65, pin 11 of chip U12, and one end of capacitor C75; the other end of resistor R65 is connected to the other end of capacitor C74 and pin 6 of chip U12; the other end of capacitor C75 is connected to one end of resistor R57.The other end of resistor R57 is connected to one end of capacitor C76 and one end of capacitor C86, respectively, and serves as the IINN output terminal; the other end of capacitor C86 is connected to the other end of capacitor C85 and grounded; the Qinn, Qinp, IINN, and IINP output terminals are all connected to the decoding module.

[0036] The decoding module includes an analog-to-digital conversion submodule and an FPGA submodule connected to the analog-to-digital conversion submodule; the analog-to-digital conversion submodule is connected to an intermediate frequency bandpass filter submodule; and the FPGA submodule is connected to a processor module. like Figure 5 As shown, the analog-to-digital conversion submodule includes the eleventh chip U7 of model ADS1220, resistors R34, R35, R36, and R37, and capacitors C91 and C92. One end of resistor R34 serves as the IN input terminal and is connected to one end of capacitor C86; the other end of resistor R34 is connected to pin 16 of the eleventh chip U7 and one end of capacitor C91; the other end of capacitor C91 is connected to one end of resistor R35 and pin 15 of the eleventh chip U7; the other end of resistor R35 serves as the IP input terminal and is connected to one end of capacitor C85; one end of resistor R36 serves as the QN input terminal and is connected to one end of capacitor C63; the other end of resistor R36 is connected to pin 16 of the eleventh chip U7 and one end of capacitor C91; Pin 5 of chip U7 is connected to one end of capacitor C92; the other end of capacitor C92 is connected to one end of resistor R37 and pin 6 of chip U7; the other end of resistor R37 serves as the QP input terminal and is connected to one end of capacitor C64; pins 11, 12, 10, and 9 of chip U7 serve as the B15L10N, B15L10P, B15L7N, and B15L7P output terminals respectively, and are all connected to the FPGA submodule. like Figure 6 , Figure 7 and Figure 8 As shown, the FPGA submodule includes the twelfth chip U11A (model XC7A100T-1CSG324I), the thirteenth chip U11B (model XC7A35T-1CSG324I), resistors R4 and R5, the fourteenth chip U30 (model W25Q128), resistors R18, R19, and R20; The K17, K18, L14, M14, and L13 pins of the twelfth chip U11A are respectively used as QSPID0, QSPID1, QSPID2, QSPID3, and QSPICS terminals, and are all connected to the processor module. The B16, B17, B18, and A18 pins of the thirteenth chip U11B are respectively used as B15L7P, B15L7N, B15L10P, and B15L10N input terminals, and are connected to the 9th, 10th, 12th, and 11th pins of the eleventh chip U7. The C16 and C17 pins of the thirteenth chip U11B are connected to one end of resistor R4 and one end of resistor R5, respectively. The other end of resistor R4 serves as the FPGA. The TX terminal of the 14th chip U30 and the other end of resistor R5 serve as the RX terminal of the FPGA, both connected to the processor module. The first pin of the 14th chip U30 is connected to one end of resistor R20 and the L13 pin of the 13th chip U11B. The other end of resistor R20 is connected to an external power supply VCC3V3. The 5th and 2nd pins of the 14th chip U30 are connected to the K17 and K18 pins of the 13th chip U11B respectively. The 3rd pin of the 14th chip U30 is connected to one end of resistor R19 and the L14 pin of the 13th chip U11B. The other end of resistor R19 is connected to one end of resistor R18 and connected to an external power supply VCC3V3. The 7th pin of the 14th chip U30 is connected to the other end of resistor R18 and the M14 pin of the 13th chip U11B.

[0037] like Figure 9 As shown, the magnet signal processing module includes four identical magnet signal processing sub-modules; Each of the four magnet signal processing submodules includes resistor R104, capacitor C173, resistor R100, resistor R106, resistor R97, capacitor C166, grounding capacitor 180, capacitor C175, resistor R107, resistor 102, resistor R105, resistor R115, resistor R114, antenna TP7, bidirectional trigger diode D5 of model BAT54S, grounding capacitor C176, and fifteenth chip U27 and sixteenth chip U28 of model OPA197IDBVR. One end of resistor R104 is connected to one end of capacitor C173 and one end of resistor R100, serving as the CG+ terminal; the other end of resistor R104 is connected to the other end of capacitor C173 and one end of resistor R106, serving as the CG- terminal; the other end of resistor R100 is connected to one end of resistor R97, one end of capacitor C166, and pin 1 of the fifteenth chip U27; the other end of resistor R97 is connected to the other end of capacitor C166 and ground capacitor C180, and connected to external power supply VCC_Bias; the other end of resistor R106 is connected to pin 3 of the fifteenth chip U27, one end of capacitor C175, and one end of resistor R107; the other end of capacitor C175 is connected to resistor R104... The other end of resistor R102 is connected to pin 4 of the fifteenth chip U27; the other end of resistor R102 is connected to pin 1 of the sixteenth chip U28; pin 4 of the sixteenth chip U28 is connected to one end of resistor R105 and one end of resistor R115 respectively; the other end of resistor R115 is connected to pin 3 of the sixteenth chip U28 and one end of resistor R114 respectively; the other end of resistor R114 is grounded; the other end of resistor R105 is connected to antenna TP7, the third end of bidirectional trigger diode D5, and grounding capacitor C176 respectively, serving as the CGADC output terminal; the first end of bidirectional trigger diode D5 is grounded; the second end of bidirectional trigger diode D5 is connected to the external power supply VCC_MCU; The four magnet signal processing submodules have CGADC output terminals of CG1ADC, CG2ADC, CG3ADC and CG4ADC respectively, and are all connected to the processor module.

[0038] like Figure 10 and Figure 11 As shown, the processor module includes the seventeenth chip U8 of model STM32F405RGT6 and the eighteenth chip U9 of model W25Q64; Pins 29, 53, 51, and 52 of the seventeenth chip U8 are connected to pins 30, 31, 32, and 33 of the first chip U10, respectively. Pins 42 and 43 of the seventeenth chip U8 are connected to the other ends of resistors R5 and R4, respectively. Pins 8, 9, 10, and 11 of the seventeenth chip U8 are connected to the CG1ADC output terminal, the CG2ADC output terminal, and the CG3ADC output terminal, respectively. The DC output terminal and the CG4ADC output terminal are connected one-to-one; pins 33, 34, 35, 36 and 37 of the seventeenth chip U8 are all connected to the network interface module; the eighteenth chip U9 is a serial data memory externally expanded by the seventeenth chip U8 through the SPI1 port; pins 1, 2, 5 and 6 of the eighteenth chip U9 are connected one-to-one with pins 24, 22, 23 and 21 of the seventeenth chip U8.

[0039] like Figure 12 and Figure 13 As shown, the network interface module includes the nineteenth chip U17 of model W5550, resistors R63 and R66, capacitors C129 and C130, resistors R74 and R75, the twentieth chip U18 of model HR641680E, and RJ45 terminal J7. Pins 32, 33, 34, 35, and 37 of the nineteenth chip U17 are connected one-to-one with pins 33, 34, 35, 36, and 37 of the seventeenth chip U8; pin 1 of the nineteenth chip U17 is connected to one end of resistor R63 and pin 3 of the twentieth chip U18; pin 2 of the nineteenth chip U17 is connected to one end of resistor R66 and pin 1 of the twentieth chip U18; the other ends of resistors R63 and R66 are connected and connected to an external power supply W55_VCCD; the nineteenth chip U17... Pin 5 of the 19th chip U17 is connected to one end of resistor R74 and one end of capacitor C129; the other end of capacitor C129 is connected to pin 8 of the 20th chip U18; pin 6 of the 19th chip U17 is connected to one end of resistor R74 and one end of capacitor C130; the other end of capacitor C130 is connected to pin 6 of the 20th chip U18; the other end of resistor R75 is connected to the other end of resistor R74; pins 9, 11, 14 and 16 of the 20th chip U18 are connected to pins 4, 3, 2 and 1 of RJ45 terminal J7 respectively.

[0040] In this solution, the small digital vehicle number antenna is powered by a DC 15-24V power supply, which is then regulated internally to the operating voltage required by each module, such as DC 5V, DC 3.3V, DC 8V, etc.

[0041] The working principle of this utility model is as follows: By connecting pins 29, 53, 51, and 52 of the seventeenth chip U8 to pins 30, 31, 32, and 33 of the first chip U10, the processor module controls the RF local oscillator module to generate different local oscillator frequencies, thereby obtaining the phase-locked loop source signal and the RF local oscillator source signal. One end of capacitor C10 is connected to pin 4 of the second chip U1, the other end of capacitor C33 is connected to pin 6 of the second chip U1, and the 910~914MHz frequency modulation signal with vehicle number information is received through antenna J1. This allows the power amplification and mixing submodule to amplify and mix the phase-locked loop source signal and the radio frequency local oscillator source signal to obtain an intermediate frequency signal with vehicle number information. By connecting one end of resistor R51 to one end of capacitor C25, the other end of resistor R54 to the other end of capacitor C25, one end of resistor R56 to one end of capacitor C24, and the other end of resistor R59 to the other end of capacitor C24, the intermediate frequency bandpass filter submodule filters and down-converts the intermediate frequency signal containing vehicle number information to generate two sets of differential baseband signals with vehicle number information, namely I-channel and Q-channel. By connecting one end of resistor R34 to one end of capacitor C86, the other end of resistor R35 to one end of capacitor C85, one end of resistor R36 to one end of capacitor C63, and the other end of resistor R37 to one end of capacitor C64, high-speed acquisition of two sets of differential baseband signals with vehicle number information in the I and Q channels is realized based on the analog-to-digital conversion submodule, and the two sets of digital differential baseband signals with vehicle number information in the I and Q channels are obtained. By connecting pins B16, B17, B18, and A18 of the thirteenth chip U11B to pins 9, 10, 12, and 11 of the eleventh chip U7, the digital differential baseband signals with vehicle number information in the I and Q channels are digitally decoded based on the FPGA submodule to obtain the actual tag data with vehicle number information. By connecting pins 1, 5, 2, 3, and 7 of the fourteenth chip U30 to pins L13, K17, K18, L14, and M14 of the thirteenth chip U11B, the FPGA submodule stores the actual tag data containing vehicle number information into the serial memory corresponding to the fourteenth chip U30, ensuring data power-off protection. By connecting the other ends of resistor R5 and resistor R4 to pins 42 and 43 of the seventeenth chip U8, the FPGA submodule transmits the actual tag data with vehicle number information to the processor module through the serial port. The vehicle number information is reflected by the frequency and power of the antenna. The 8th, 9th, 10th and 11th pins of the 17th chip U8 are connected one-to-one with the output terminals of CG1ADC, CG2ADC, CG3ADC and CG4ADC, so that the four magnet signal processing sub-modules transmit the four magnet signals to the processor module. The processor module obtains the magnet digital signal with vehicle positioning information after AD conversion. Each magnet signal processing sub-module filters and amplifies the original magnet signal with differential input and vehicle positioning information to obtain the corresponding magnet signal. By connecting pins 1, 2, 5 and 6 of the eighteenth chip U9 to pins 24, 22, 23 and 21 of the seventeenth chip U8, the external serial data memory corresponding to the eighteenth chip U9 can store important data such as IP addresses that require power-down protection. The processor module connects to the network interface chip (U17) via pins 33, 34, 35, 36, and 37 of the seventeenth chip U8, corresponding to pins 32, 33, 34, 35, and 37 of the nineteenth chip U17. This enables the processor module to drive the network interface to restart and transmit the message generated by the processor module based on the magnetic steel digital signal containing vehicle positioning information and the actual tag data containing vehicle number information to the network chip of the network interface module, namely the nineteenth chip U17. The message is transmitted via pins 1 and 2 of the nineteenth chip U17. The pins are connected one-to-one with pins 3 and 1 of the 20th chip; the other end of capacitor C129 and the other end of capacitor C130 are connected one-to-one with pins 8 and 6 of the 20th chip; and pins 9, 11, 14 and 16 of the 20th chip U18 are connected one-to-one with pins 4, 3, 2 and 1 of RJ45 terminal J7. This allows the network interface module to transmit messages containing vehicle location information and license plate number information to the host computer through the RJ45 terminal, thereby realizing vehicle counting, speed measurement and vehicle number location.

[0042] In a practical example, based on message parsing, the waveform of the magnet and the vehicle number data collected throughout the process can be obtained. It can be read that the first vehicle number data was collected when the second axle of the vehicle pressed the fourth magnet, that is, the vehicle number data is close to the second axle and belongs to the positive direction of the A end; the second vehicle number data was also collected when the second axle of the same vehicle pressed the fourth magnet, and the vehicle number data was also close to the second axle and belonged to the positive direction of the A end.

[0043] The above description is only a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model.

Claims

1. A small digital vehicle number antenna, characterized in that, It includes an RF module, a decoding module, a magnet signal processing module, a processor module, and a network interface module; The radio frequency module is connected to both the processor module and the decoding module; the decoding module is connected to the processor module; the magnet signal processing module is connected to the processor module; and the processor module is connected to the network interface module.

2. The miniature digital vehicle number antenna according to claim 1, characterized in that, The radio frequency module includes a radio frequency local oscillator module, a power amplification and mixing submodule, and an intermediate frequency bandpass filter submodule connected in sequence; the radio frequency local oscillator module is connected to the processor module; and the intermediate frequency bandpass filter submodule is connected to the decoding module.

3. The miniature digital vehicle number antenna according to claim 2, characterized in that, The radio frequency local oscillator module includes a first chip U10 with model number HMC821LP6CE, a second chip U1 with model number SCN-2-11+, capacitors C125, C149, C150, C152, inductors L131 and L133. Pin 28 of the first chip U10 is connected to one end of capacitor C152 and one end of inductor L31; the other end of inductor L31 is connected to the positive terminal of capacitor C150, one end of capacitor C125, one end of capacitor C149, and one end of inductor L133; the negative terminal of capacitor C150 is connected to the other end of capacitor C125 and the other end of capacitor C149, and is grounded; the other end of inductor L133 is connected to an external power supply VCC_PLL; the other end of capacitor C152 is connected to pin 2 of the second chip U1; pin 4 of the second chip U1 serves as the output terminal of the phase-locked loop source and is connected to the power amplifier and mixer submodule; pin 6 of the second chip U1 serves as the output terminal of the local oscillator source and is connected to the power amplifier and mixer submodule; pins 30, 31, 32, and 33 of the first chip U10 serve as local oscillator frequency control terminals and are all connected to the processor module.

4. The miniature digital vehicle number antenna according to claim 3, characterized in that, The power amplification and mixing submodule includes capacitor C10, third chip U3 (model ADL5611), inductor L4, capacitors C9, C8, and C7, resistor R12, grounding capacitor C6, inductor L3, capacitor C11, fourth chip U2 (model RA03M8894M), capacitor C12, fifth chip W2 (model LFCN-1000+), sixth chip U4 (model RCP890A10), capacitor C1, antenna J1, inductor L13, seventh and eighth chips W3 and W4 (model LFCN-1000+), capacitor C2, resistors R15, R16, and R17, capacitor C34, grounding capacitor C32, ninth chip U6 (model LT5575EUF), capacitors C24, C25, C33, and C35; One end of capacitor C10 serves as the source receiver of the phase-locked loop and is connected to pin 4 of the second chip U1; the other end of capacitor C10 is connected to pin 1 of the third chip U3; pin 3 of the third chip U3 is connected to one end of capacitor C11 and one end of inductor L4; the other end of inductor L4 is connected to one end of capacitor C9, one end of capacitor C8, one end of capacitor C7, and one end of resistor R12; the other end of capacitor C9 is connected to the other ends of capacitor C8 and capacitor C7, and grounded; the other end of resistor R12 is connected to one end of inductor L3 and grounded capacitor C6; the other end of inductor L3 is connected to an external power supply VCC_RF. The other end of capacitor C11 is connected to pin 1 of the fourth chip U2; pin 4 of the fourth chip U2 is connected to one end of capacitor C12; the other end of capacitor C12 is connected to pin 1 of the fifth chip W2; pin 3 of the fifth chip W2 is connected to pin 2 of the sixth chip U4; pin 1 of the sixth chip U4 is connected to one end of capacitor C1; the other end of capacitor C1 is connected to antenna J1 to receive FM signals of 910~914MHz; pin 0 of the sixth chip U4 is connected to one end of inductor L13 and grounded; pin 4 of the sixth chip U4 is connected to the other end of inductor L13 and pin 1 of the seventh chip W3, respectively. Connections: Pin 3 of the seventh chip W3 is connected to pin 1 of the eighth chip W4; pin 3 of the eighth chip W4 is connected to one end of capacitor C2; the other end of capacitor C2 is connected to one end of resistor R15 and one end of resistor R17; the other end of resistor R17 is connected to one end of resistor R16 and grounded; the other end of resistor R15 is connected to the other end of resistor R16 and one end of capacitor C34; the other end of capacitor C34 is connected to pin 2 of the ninth chip U6 and grounded capacitor C32; pin 10 of the ninth chip U6 is connected to one end of capacitor C33 and one end of capacitor C35; the other end of capacitor C33... The first pin serves as the local oscillator receiver and is connected to pin 6 of the second chip U1; pin 11 of the ninth chip U6 is connected to the other end of capacitor C35; pin 13 of the ninth chip U6 is connected to one end of capacitor C25 and serves as the QN output; pin 14 of the ninth chip U6 is connected to the other end of capacitor C25 and serves as the QP output; pin 15 of the ninth chip U6 is connected to one end of capacitor C24 and serves as the IN output; pin 16 of the ninth chip U6 is connected to the other end of capacitor C24 and serves as the IP output; the QN, QP, IN, and IP outputs are all connected to the intermediate frequency bandpass filter submodule.

5. The miniature digital vehicle number antenna according to claim 4, characterized in that, The intermediate frequency bandpass filter submodule includes the tenth chip U12 (model THS4522), resistor R51, capacitor C66, resistor R52, capacitor C67, capacitor C61, capacitor C71, capacitor C72, capacitor C62, resistor R54, resistor R48, capacitor C70, resistor R53, capacitor C69, capacitor C64, resistor R43, capacitor C65, resistor R50, capacitor C63, capacitor C73, resistor R58, capacitor C81, capacitor C74, capacitor C77, capacitor C78, ​​capacitor C87, resistor R59, resistor R66, capacitor C79, resistor R60, capacitor C76, capacitor C85, resistor R65, capacitor C75, resistor R57, capacitor C76, and capacitor C86. One end of resistor R51 serves as the QN input terminal and is connected to one end of capacitor C25; the other end of resistor R51 is connected to one end of capacitor C66; the other end of capacitor C66 is connected to one end of resistor R52, one end of capacitor C67, and one end of capacitor C61 respectively; the other end of resistor R52 is connected to one end of capacitor C71, one end of capacitor C72, and one end of capacitor C62 respectively; the other end of capacitor C71 is connected to one end of resistor R54; the other end of resistor R54 serves as the QP input terminal and is connected to the other end of capacitor C25; the other end of capacitor C72 is connected to pin 3 of the tenth chip U12 and one end of resistor R48 respectively; the other end of resistor R48 is connected to... The other end of capacitor C62, pin 14 of the tenth chip U12, and one end of capacitor C70 are connected; the other end of capacitor C70 is connected to one end of resistor R53; the other end of resistor R53 is connected to one end of capacitor C69 and one end of capacitor C64, respectively, as the QinP output terminal; the other end of capacitor C67 is connected to pin 2 of the tenth chip U12 and one end of resistor R43, respectively; the other end of resistor R43 is connected to the other end of capacitor C61, pin 15 of the tenth chip U12, and one end of capacitor C65, respectively; the other end of capacitor C65 is connected to one end of resistor R50; the other end of resistor R50 is connected to the other end of capacitor C69 and one end of capacitor C63, and... As the QinN output terminal; the other end of capacitor C63 is connected to the other end of capacitor C64 and grounded; one end of resistor R56 serves as the IN input terminal and is connected to one end of capacitor C24; the other end of resistor R56 is connected to one end of capacitor C73; the other end of capacitor C73 is connected to one end of resistor R58, one end of capacitor C81, and one end of capacitor C74 respectively; the other end of resistor R58 is connected to one end of capacitor C77, one end of capacitor C78, ​​and one end of capacitor C87 respectively; the other end of capacitor C77 is connected to one end of resistor R59; the other end of resistor R59 serves as the IP input terminal and is connected to the other end of capacitor C24; the other end of capacitor C78 is connected to the tenth Pin 7 of chip U12 is connected to one end of resistor R66; the other end of resistor R66 is connected to the other end of capacitor C87, pin 10 of chip U12, and one end of capacitor C79; the other end of capacitor C79 is connected to one end of resistor R60; the other end of resistor R60 is connected to one end of capacitor C76 and one end of capacitor C85, and serves as the IINP output terminal; the other end of capacitor C81 is connected to one end of resistor R65, pin 11 of chip U12, and one end of capacitor C75; the other end of resistor R65 is connected to the other end of capacitor C74 and pin 6 of chip U12; the other end of capacitor C75 is connected to one end of resistor R57.The other end of resistor R57 is connected to one end of capacitor C76 and one end of capacitor C86, respectively, and serves as the IINN output terminal; the other end of capacitor C86 is connected to the other end of capacitor C85 and grounded; the Qinn, Qinp, IINN, and IINP output terminals are all connected to the decoding module.

6. The miniature digital vehicle number antenna according to claim 5, characterized in that, The decoding module includes an analog-to-digital conversion submodule and an FPGA submodule connected to the analog-to-digital conversion submodule; the analog-to-digital conversion submodule is connected to an intermediate frequency bandpass filter submodule; and the FPGA submodule is connected to a processor module. The analog-to-digital conversion submodule includes the eleventh chip U7 (model ADS1220), resistors R34, R35, R36, and R37, and capacitors C91 and C92. One end of resistor R34 serves as the IN input terminal and is connected to one end of capacitor C86; the other end of resistor R34 is connected to pin 16 of the eleventh chip U7 and one end of capacitor C91; the other end of capacitor C91 is connected to one end of resistor R35 and pin 15 of the eleventh chip U7; the other end of resistor R35 serves as the IP input terminal and is connected to one end of capacitor C85; one end of resistor R36 serves as the QN input terminal and is connected to one end of capacitor C63; the other end of resistor R36 is connected to pin 16 of the eleventh chip U7 and one end of capacitor C91; Pin 5 of chip U7 is connected to one end of capacitor C92; the other end of capacitor C92 is connected to one end of resistor R37 and pin 6 of chip U7; the other end of resistor R37 serves as the QP input terminal and is connected to one end of capacitor C64; pins 11, 12, 10, and 9 of chip U7 serve as the B15L10N, B15L10P, B15L7N, and B15L7P output terminals respectively, and are all connected to the FPGA submodule. The FPGA submodule includes the twelfth chip U11A (model XC7A100T-1CSG324I), the thirteenth chip U11B (model XC7A35T-1CSG324I), resistors R4 and R5, the fourteenth chip U30 (model W25Q128), resistors R18, R19, and R20. The K17, K18, L14, M14, and L13 pins of the twelfth chip U11A are respectively used as QSPID0, QSPID1, QSPID2, QSPID3, and QSPICS terminals, and are all connected to the processor module. The B16, B17, B18, and A18 pins of the thirteenth chip U11B are respectively used as B15L7P, B15L7N, B15L10P, and B15L10N input terminals, and are connected to the 9th, 10th, 12th, and 11th pins of the eleventh chip U7. The C16 and C17 pins of the thirteenth chip U11B are connected to one end of resistor R4 and one end of resistor R5, respectively. The other end of resistor R4 serves as the FPGA. The TX terminal of the 14th chip U30 and the other end of resistor R5 serve as the RX terminal of the FPGA, both connected to the processor module. The first pin of the 14th chip U30 is connected to one end of resistor R20 and the L13 pin of the 13th chip U11B. The other end of resistor R20 is connected to an external power supply VCC3V3. The 5th and 2nd pins of the 14th chip U30 are connected to the K17 and K18 pins of the 13th chip U11B respectively. The 3rd pin of the 14th chip U30 is connected to one end of resistor R19 and the L14 pin of the 13th chip U11B. The other end of resistor R19 is connected to one end of resistor R18 and connected to an external power supply VCC3V3. The 7th pin of the 14th chip U30 is connected to the other end of resistor R18 and the M14 pin of the 13th chip U11B.

7. The miniature digital vehicle number antenna according to claim 6, characterized in that, The magnet signal processing module includes four identical magnet signal processing sub-modules; Each of the four magnet signal processing submodules includes resistor R104, capacitor C173, resistor R100, resistor R106, resistor R97, capacitor C166, grounding capacitor 180, capacitor C175, resistor R107, resistor 102, resistor R105, resistor R115, resistor R114, antenna TP7, bidirectional trigger diode D5 of model BAT54S, grounding capacitor C176, and fifteenth chip U27 and sixteenth chip U28 of model OPA197IDBVR. One end of resistor R104 is connected to one end of capacitor C173 and one end of resistor R100, serving as the CG+ terminal; the other end of resistor R104 is connected to the other end of capacitor C173 and one end of resistor R106, serving as the CG- terminal; the other end of resistor R100 is connected to one end of resistor R97, one end of capacitor C166, and pin 1 of the fifteenth chip U27; the other end of resistor R97 is connected to the other end of capacitor C166 and ground capacitor C180, and connected to external power supply VCC_Bias; the other end of resistor R106 is connected to pin 3 of the fifteenth chip U27, one end of capacitor C175, and one end of resistor R107; the other end of capacitor C175 is connected to resistor R104... The other end of resistor R102 is connected to pin 4 of the fifteenth chip U27; the other end of resistor R102 is connected to pin 1 of the sixteenth chip U28; pin 4 of the sixteenth chip U28 is connected to one end of resistor R105 and one end of resistor R115 respectively; the other end of resistor R115 is connected to pin 3 of the sixteenth chip U28 and one end of resistor R114 respectively; the other end of resistor R114 is grounded; the other end of resistor R105 is connected to antenna TP7, the third end of bidirectional trigger diode D5, and grounding capacitor C176 respectively, serving as the CGADC output terminal; the first end of bidirectional trigger diode D5 is grounded; the second end of bidirectional trigger diode D5 is connected to the external power supply VCC_MCU; The four magnet signal processing submodules have CGADC output terminals of CG1ADC, CG2ADC, CG3ADC and CG4ADC respectively, and are all connected to the processor module.

8. The miniature digital vehicle number antenna according to claim 7, characterized in that, The processor module includes the seventeenth chip U8 of model STM32F405RGT6 and the eighteenth chip U9 of model W25Q64; Pins 29, 53, 51, and 52 of the seventeenth chip U8 are connected to pins 30, 31, 32, and 33 of the first chip U10, respectively. Pins 42 and 43 of the seventeenth chip U8 are connected to the other ends of resistors R5 and R4, respectively. Pins 8, 9, 10, and 11 of the seventeenth chip U8 are connected to the CG1ADC output terminal, the CG2ADC output terminal, and the CG3ADC output terminal, respectively. The DC output terminal and the CG4ADC output terminal are connected one-to-one; pins 33, 34, 35, 36 and 37 of the seventeenth chip U8 are all connected to the network interface module; the eighteenth chip U9 is a serial data memory externally expanded by the seventeenth chip U8 through the SPI1 port; pins 1, 2, 5 and 6 of the eighteenth chip U9 are connected one-to-one with pins 24, 22, 23 and 21 of the seventeenth chip U8.

9. The miniature digital vehicle number antenna according to claim 8, characterized in that, The network interface module includes the nineteenth chip U17 (model W5550), resistors R63 and R66, capacitors C129 and C130, resistors R74 and R75, the twentieth chip U18 (model HR641680E), and RJ45 terminal J7. Pins 32, 33, 34, 35, and 37 of the nineteenth chip U17 are connected one-to-one with pins 33, 34, 35, 36, and 37 of the seventeenth chip U8; pin 1 of the nineteenth chip U17 is connected to one end of resistor R63 and pin 3 of the twentieth chip U18; pin 2 of the nineteenth chip U17 is connected to one end of resistor R66 and pin 1 of the twentieth chip U18; the other ends of resistors R63 and R66 are connected and connected to an external power supply W55_VCCD; the nineteenth chip U17... Pin 5 of the 19th chip U17 is connected to one end of resistor R74 and one end of capacitor C129; the other end of capacitor C129 is connected to pin 8 of the 20th chip U18; pin 6 of the 19th chip U17 is connected to one end of resistor R74 and one end of capacitor C130; the other end of capacitor C130 is connected to pin 6 of the 20th chip U18; the other end of resistor R75 is connected to the other end of resistor R74; pins 9, 11, 14 and 16 of the 20th chip U18 are connected to pins 4, 3, 2 and 1 of RJ45 terminal J7 respectively.

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