Radio frequency front-end module and electronic device

Abstract

The application discloses a radio frequency front-end module and electronic equipment. By setting the capacitor unit on the output path of the power amplifier circuit as a finger capacitor, reasonably adjusting the setting positions of the resistor and the capacitor connected with the coupler, and reasonably adjusting the position of the direct-current blocking capacitor on the input path of the power amplifier circuit, the occupied area of the substrate can be effectively reduced, the overall size of the radio frequency front-end module can be reduced, and the miniaturization of the device is realized.

Description

[0001] This application claims priority to Chinese Patent Application No. 202511426077.X, filed on September 30, 2025, entitled "Radio Frequency Front-End Module and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of radio frequency technology, and in particular to a radio frequency front-end module and electronic device. Background Technology

[0003] Radio frequency (RF) front-end modules are core components in wireless communication systems. They integrate two or more discrete devices such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers for wireless signal transmission and reception, filtering, amplification, and frequency conversion. They are widely used in communication electronic devices such as smartphones, tablets, smartwatches, vehicle terminals, and routers.

[0004] Currently, with the rapid development of communication technology, device miniaturization has become a trend. Therefore, miniaturizing radio frequency front-end modules has become an urgent problem to be solved. Utility Model Content

[0005] This application provides a radio frequency front-end module and an electronic device that can achieve miniaturization of the radio frequency front-end module.

[0006] In a first aspect, embodiments of this application provide a radio frequency front-end module, including: A substrate and a power amplifier chip disposed on the substrate, wherein the power amplifier chip integrates the power amplifier circuit; The radio frequency front-end module also includes a capacitor unit, which is connected to the output path of the power amplifier circuit. The capacitor unit is an interdigitated capacitor.

[0007] Secondly, embodiments of this application provide a radio frequency front-end module, including: The system comprises a substrate, an antenna port disposed on the substrate, a switching chip, a power amplifier chip, and a coupler. The switching chip integrates a switching unit, and the power amplifier chip integrates a power amplifier circuit. The switching unit is connected to the output path between the output terminal of the power amplifier circuit and the antenna port. The coupler includes a main line connected to the transmission path between the switching unit and the antenna port, and a coupling line coupled to the main line. The isolation port of the coupling line is grounded through a resistor and a ninth capacitor. The resistor and the ninth capacitor are both integrated on the power amplifier chip or the switching chip.

[0008] Thirdly, embodiments of this application provide a radio frequency front-end module, including: The substrate, the first DC blocking unit, and the signal input port, the power amplifier chip, and the CMOS chip disposed on the substrate; the power amplifier chip integrates a power amplifier circuit, and the first DC blocking unit is connected to the input path between the signal input port and the input terminal of the power amplifier circuit; The first DC blocking unit includes a stacked capacitor, and the first DC blocking unit is disposed on the CMOS chip.

[0009] Fourthly, embodiments of this application provide an electronic device, including a radio frequency front-end module provided in any one of the first, second, and third aspects of this application.

[0010] The RF front-end module and electronic device provided in this application can effectively reduce the substrate area and the overall size of the RF front-end module by setting the capacitor unit on the output path of the power amplifier circuit as an interdigitated capacitor, reasonably adjusting the setting position of the resistor and capacitor connected to the coupler, and reasonably adjusting the position of the DC blocking capacitor on the input path of the power amplifier circuit. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the circuit structure of a radio frequency front-end module provided in an embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of another radio frequency front-end module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the circuit structure of another radio frequency front-end module provided in the embodiments of this application; Figure 4 This is a schematic diagram of a substrate layout for a radio frequency front-end module provided in an embodiment of this application; Figure 5 This is a schematic diagram of a specific circuit structure of the radio frequency front-end module provided in an embodiment of this application; Figure 6 This is another specific circuit structure diagram of the radio frequency front-end module provided in the embodiments of this application; Figure 7 This is a schematic diagram of the circuit structure of another radio frequency front-end module provided in the embodiments of this application; Figure 8This is a schematic diagram of the circuit structure of another radio frequency front-end module provided in the embodiments of this application; Figure 9 This is a schematic diagram of a substrate layout for a radio frequency front-end module provided in an embodiment of this application.

[0013] Explanation of icon numbers: 100. Substrate; 10. Filtering unit; 200. Power amplifier chip; 20. Power amplifier circuit; 21a. First power amplifier unit; 21b. Second power amplifier unit; 300. Switching chip; 30. Switching unit; 40. Matching network; 40a. First matching network; 41a. First primary-order matching circuit; 42a. Intermediate-order matching circuit; 43a. First final-order matching circuit; 40b. Second matching network; 41b. Second primary-order matching circuit; 42b. Second final-order matching circuit; 50. First DC blocking unit; 60. Second DC blocking unit; 400. CMOS chip. Detailed Implementation

[0014] To make the technical problems, technical solutions, and beneficial effects solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0015] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. The term "connection" in this application, unless otherwise specified, includes both direct and indirect connections (including electrical connections). Directional terms used in this application, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application. Furthermore, the terms "comprising," "may include," "includes," or "may contain" used in this application indicate the existence of the corresponding functions, operations, elements, etc., disclosed, and do not limit other one or more additional functions, operations, elements, etc.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0017] This application provides an electronic device, which includes a substrate and a radio frequency (RF) front-end module mounted on the substrate. The RF front-end module is configured to be electrically connected to an antenna module. The RF front-end module is a component that integrates two or more discrete devices such as RF switches, low-noise amplifiers, filters, duplexers, and RF power amplifiers into a single independent module, thereby improving integration and hardware performance, and miniaturizing the device.

[0018] In some implementations, the radio frequency front-end module includes a power amplifier and a switching unit. The power amplifier amplifies the radio frequency signal and then transmits it to the antenna port through the switching unit.

[0019] In some implementations, the RF front-end module includes a power amplifier, which comprises a power amplification circuit and an output matching circuit. As an example, the output matching circuit includes a capacitor and an inductor; the capacitor and inductor can be connected in series or in parallel, and the output matching circuit is used to achieve output impedance matching of the power amplifier.

[0020] In some implementations, the power amplifier further includes a harmonic suppression circuit, which includes a capacitor and an inductor. The capacitor and inductor can be connected in series or in parallel. The harmonic suppression circuit is used to suppress harmonic signals in the radio frequency amplified signal output by the power amplifier circuit.

[0021] In some implementations, capacitors and inductors can be integrated on a chip or disposed on a substrate. Capacitors can be MIM capacitors, MOM capacitors, SMD capacitors, or interdigitated capacitors. Inductors can be SMD inductors, wire-wound inductors, or implemented via jumpers.

[0022] In one embodiment, the substrate is a printed circuit board (PCB) used to fix and support the chips or components (e.g., power amplifier chips, switch chips, etc.) in the RF front-end module. Specifically, the substrate can be a copper-clad laminate, and circuits can be printed on the surface of the substrate by performing hole processing, chemical copper plating, electroplating, etching, etc. In other possible examples, the substrate can also be a high-resistivity silicon (HR-Si) substrate, an ultra-thin glass substrate, a low-temperature co-fired ceramic (LTCC) substrate, a thin-film piezoelectric insulating substrate (POI), etc. This application realizes signal reception and / or transmission through an RF front-end module.

[0023] For example, electronic devices may be computers, mobile phones, tablets, smartwatches, vehicle terminals, and navigation devices that need to receive and / or transmit radio frequency signals, and this application does not limit them.

[0024] Please see Figure 1 , Figure 1 This application provides an embodiment of a radio frequency front-end module. The radio frequency front-end module 1000 in this embodiment can support carrier aggregation, dual connectivity, and multiple-input multiple-output (MIMO).

[0025] Specifically, radio frequency front-end modules can be used in electronic devices such as computers, mobile phones, tablets, smartwatches, vehicle terminals, and navigation devices, as well as in communication devices including base stations and NFC (Near Field Communication) devices.

[0026] Specifically, the RF front-end module may include a signal input port, a filtering unit 10, a power amplification (PA) circuit 20, a switching unit 30, and an antenna port ANT, wherein the antenna port ANT is used to connect to the antenna module.

[0027] In this embodiment, the power amplifier circuit 20 amplifies the received signal to a sufficiently high level to ensure effective transmission of the radio frequency signal while minimizing distortion. The power amplifier circuit 20 sends the amplified signal to the filtering unit 10. The power amplifier circuit 20 may include multiple power amplification modules, which can amplify the power of low, medium, and high frequency radio frequency signals respectively.

[0028] In this embodiment, the filtering unit 10 may specifically include one or more of a filter, a duplexer, and a multiplexer to filter the power-amplified radio frequency signal to remove noise. The filtering unit 10 may specifically include multiple filtering channels to filter radio frequency signals of different frequency bands and send the filtered radio frequency signals of different frequency bands to the switching unit 30. The switching unit 30 selects an appropriate antenna port ANT for transmitting the radio frequency signals of different frequency bands.

[0029] In this embodiment, the radio frequency front-end module includes various modules in the transmission link.

[0030] In some implementations, the RF front-end module may also include various modules in the receiving link, specifically including a low-noise amplifier circuit. The weak RF signal received at the antenna port is filtered by the filtering unit and then sent to the low-noise amplifier circuit, where it is amplified by power and then sent to other modules.

[0031] In some implementations, the radio frequency front-end module may also include analog control circuitry for controlling the on and off states of the switching unit.

[0032] In some implementations, the RF front-end module may also include a coupler that proportionally distributes the RF signal power of the output path of the power amplifier circuit 20 to the coupling port. The coupling port is connected to a power detection unit, which is used to monitor the output power of the power amplifier circuit 20 in real time to ensure signal quality and adjust the transmit power.

[0033] Please see Figure 2 and Figure 4 , Figure 2 This application provides an embodiment of a radio frequency front-end module. Figure 4 This is a schematic diagram of a substrate layout for a radio frequency front-end module provided in an embodiment of this application. Specifically, as shown... Figure 4 As shown, the RF front-end module may include a substrate 100, a signal input port disposed on the substrate 100, an antenna port ANT, and a power amplifier chip 200. Figure 2 As shown, the power amplifier chip 200 integrates a power amplifier circuit 20, which is connected between the signal input port and the antenna port ANT. A capacitor unit C is connected to the output path of the power amplifier circuit 20, specifically in the transmission path between the power amplifier circuit 20 and the antenna port ANT. The capacitor unit C can be connected in series in the output path of the power amplifier circuit 20, or one end can be connected to a node in the output path of the power amplifier circuit 20, and the other end can be grounded.

[0034] In this embodiment, the capacitor unit C is an interdigitated capacitor.

[0035] It is understood that the interdigitated capacitors can be directly disposed on the substrate 100 or disposed on other chips, and this application embodiment does not limit this.

[0036] Understandable Figure 2 The positions of the power amplifier chip 200, the antenna port ANT, and the signal input port on the substrate 100 are only shown as examples, and the specific positions are not limited in this application embodiment.

[0037] In this embodiment, the capacitor unit C on the output path of the power amplifier circuit 20 uses interdigitated capacitors. Compared to surface-mount capacitors (SMD capacitors), interdigitated capacitors have a smaller area and lower cost for the same capacitance value. Compared to multilayer capacitors, the capacitance value of multilayer capacitors is more difficult to control and more difficult to achieve in terms of manufacturing process. Therefore, using interdigitated capacitors can achieve miniaturization of the RF front-end module, is easier to process, and reduces costs.

[0038] In one specific embodiment, when the substrate 100 has only two layers, including a first metal layer and a second metal layer, wherein the first metal layer is a ground layer, if the capacitor unit C is directly disposed on the substrate 100, then the capacitor unit C (interdigitated capacitor) is mainly disposed on the second metal layer; when the substrate 100 has more than two layers, including a first metal layer as a ground layer and other metal layers (multiple second metal layers) other than the ground layer, then the interdigitated capacitor can be disposed on any second metal layer, and this application embodiment does not limit this.

[0039] In one feasible implementation, the capacitance value of capacitor unit C is less than or equal to 0.8 pF (picofarad). That is, when the capacitance value of capacitor unit C on the output path of power amplifier circuit 20 is small, specifically less than or equal to 0.8 pF, interdigitated capacitors are used. Compared with SMD capacitors and stacked capacitors, interdigitated capacitors have greater advantages in terms of implementation difficulty and area occupation.

[0040] It is understood that capacitor unit C can refer to a single capacitor or a collection of multiple capacitors. For example, in some embodiments, all capacitors on the output path of the power amplifier circuit 20 may be interdigitated capacitors, and thus collectively referred to as capacitor units; in other embodiments, some capacitors on the output path of the power amplifier circuit 20 may be interdigitated capacitors, such as capacitors with a capacitance value less than 0.8pF, capacitors in the matching circuit, capacitors in the resonant circuit, capacitors in the harmonic suppression circuit used to suppress harmonic signals, etc., and thus these capacitors may be collectively referred to as capacitor units. This application does not limit this.

[0041] In some implementations, the RF front-end module further includes a resonant circuit connected to the output path of the power amplifier circuit 20. Specifically, this resonant circuit includes an inductor and a capacitor, forming an LC resonant circuit. The capacitor is an interdigitated capacitor. That is, the capacitor in the resonant circuit on the output path of the power amplifier circuit 20 is preferably an interdigitated capacitor, which reduces the size of the RF front-end module and simplifies implementation.

[0042] In one specific embodiment, the capacitor unit may specifically include a first capacitor unit, and the resonant circuit may be a parallel resonant circuit connected in the output path of the power amplifier circuit 20. The parallel resonant circuit includes a first inductor unit and a first capacitor unit connected in parallel; therefore, the first capacitor unit is an interdigitated capacitor. The parallel resonant circuit is connected in series in the output path of the power amplifier circuit 20.

[0043] In another specific embodiment, the capacitor unit may specifically include a second capacitor unit, and the resonant circuit may be a series resonant circuit connected to the output path of the power amplifier circuit 20. The series resonant circuit includes a second inductor unit and a second capacitor unit connected in series; therefore, the second capacitor unit is an interdigitated capacitor. One end of the series resonant circuit is connected to a node on the output path of the power amplifier circuit, and the other end of the series resonant circuit is grounded.

[0044] In another specific embodiment, the resonant circuit may include either a parallel resonant circuit or a series resonant circuit. The parallel resonant circuit is connected in series on the output path of the power amplifier circuit 20, one end of the series resonant circuit is connected to a node on the output path of the power amplifier circuit, and the other end of the series resonant circuit is grounded.

[0045] In a preferred embodiment, the resonant circuit, whether it is a parallel resonant circuit or a series resonant circuit, includes capacitors whose capacitance value is less than or equal to 0.8pF, and interdigitated capacitors can be used.

[0046] In this embodiment, the resonant circuit connected on the output path of the power amplifier circuit 20 includes interdigitated capacitors as capacitor units. Preferably, interdigitated capacitors are used for capacitor units with smaller capacitance values, which is more conducive to miniaturizing the RF front-end module and reducing the processing difficulty.

[0047] In some implementations, please refer to Figure 3 and Figure 4 , Figure 3 Another circuit structure diagram of the RF front-end module is shown. A switch chip 300 is also provided on the substrate 100. The switch chip 300 integrates a switch unit 30, which is connected to the output path between the output terminal of the power amplifier circuit 20 and the antenna port ANT.

[0048] It is understandable that the switch chip 300 can be an SOI chip.

[0049] In other embodiments, the RF front-end module further includes a matching network 40, one end of which is connected to the output of the power amplifier circuit 20, and the second end of which is connected to the switching unit 30.

[0050] In this embodiment, the aforementioned resonant circuit can be connected in the path between the switching unit 30 and the antenna port ANT, or in the path between the power amplifier circuit 20 and the switching unit 30. Alternatively, the aforementioned resonant circuit can be connected between the switching unit 30 and the antenna port ANT, as well as between the power amplifier circuit 20 and the switching unit 30. This embodiment does not limit the specific connection.

[0051] In one specific embodiment, the resonant circuit is connected on the path between the switching unit 30 and the antenna port ANT, and the capacitor unit in the resonant circuit is an interdigitated capacitor.

[0052] It is understood that the resonant circuit connected in the path between the switching unit 30 and the antenna port ANT can be a series LC resonant circuit or a parallel LC resonant circuit. Specifically, the resonant circuit can be a notch filter (tank) circuit to suppress higher harmonic signals. These higher harmonic signals can be, for example, harmonic signals with frequencies greater than or equal to twice the fundamental frequency f0, such as 2f0, 3f0, 4f0, 5f0, 6f0, etc., which are not limited in this embodiment. Therefore, in the path near the antenna port ANT, the capacitor unit in the resonant circuit for suppressing higher harmonic signals, due to its small capacitance value (e.g., less than or equal to 0.8pF), can be an interdigitated capacitor. For the same capacitance value, it has a smaller area compared to SMD capacitors and is simpler to manufacture compared to stacked capacitors.

[0053] In one exemplary implementation, such as Figure 5 As shown, Figure 5 This is a schematic diagram of a specific circuit structure of the radio frequency front-end module provided in the embodiments of this application. The resonant circuit may specifically include a capacitor C32 and an inductor L32 connected in parallel. One end of the capacitor C32 and the inductor L32 connected in parallel is connected to the switching unit 30, and the other end is connected to the antenna port ANT.

[0054] In another exemplary implementation, such as Figure 6 As shown, Figure 6 This is a schematic diagram of a specific circuit structure of the radio frequency front-end module provided in the application embodiment. The resonant circuit may specifically include a capacitor C32 and an inductor L32 connected in series. One end of the capacitor C32 is connected to the path between the switching unit 30 and the antenna port ANT, and the other end is connected to one end of the inductor L32. The other end of the inductor L32 is grounded.

[0055] In some implementations, please refer to Figure 5 and Figure 6 The power amplifier circuit 20 may specifically include a first power amplifier unit 21a and a second power amplifier unit 21b, with the first power amplifier unit 21a and the second power amplifier unit 21b operating at different frequency bands.

[0056] It is understood that the first power amplification unit 21a and the second power amplification unit 21b can both be integrated on the same power amplification chip 200, or they can be integrated on different amplification chips. For example, the power amplification chip 2000 includes a first amplification chip and a second amplification chip, and the first power amplification unit 21a and the second power amplification unit 21b are respectively integrated on the first amplification chip and the second amplification chip.

[0057] It is understood that the power amplifier chip 200 can be an HBT chip or a CMOS chip. Preferably, the power amplifier chip 200 is an HBT chip.

[0058] In this embodiment, the operating frequency band of the first power amplification unit 21a may be lower than or higher than the operating frequency band of the second power amplification unit 21b. This embodiment does not impose any limitation.

[0059] In one specific embodiment, the operating frequency band of the first power amplification unit 21a is lower than that of the second power amplification unit 21b. For example, the first power amplification unit 21a can be used to amplify the power of low-frequency radio frequency signals, and the second power amplification unit 21a can be used to amplify the power of mid-frequency or high-frequency radio frequency signals. Alternatively, the first power amplification unit 21a can be used to amplify the power of mid-frequency radio frequency signals, and the second power amplification unit 21a can be used to amplify the power of high-frequency radio frequency signals. The low-frequency band frequency can be, for example, in the range of 600MHz-920MHz, the mid-frequency band frequency can be, for example, in the range of 1710MHz-2200MHz, and the high-frequency band frequency can be, for example, in the range of 2300MHz-2690MHz.

[0060] In one exemplary embodiment, when the operating frequency band of the first power amplification unit 21a is lower than that of the second power amplification unit 21b, the resonant circuit can be connected to the output path of the second power amplification unit 21b. Specifically, it can be connected between the second power amplification unit 21b and the switching unit 20. Therefore, on two transmission paths with different operating frequency bands, the resonant circuit connected to the output path of the power amplification unit with the larger operating frequency band can use interdigitated capacitors (especially capacitors with smaller capacitance values), which is more conducive to reducing the overall size of the RF front-end module.

[0061] Preferably, when the capacitance value of the capacitor unit is small, for example, less than or equal to 0.8pF, interdigitated capacitors are used. Compared with SMD capacitors, they have a smaller area for the same capacitance value. Compared with stacked capacitors, they are easier to process. Therefore, using interdigitated capacitors is more conducive to reducing the overall size of the RF front-end module, and the processing is simple and the cost is reduced.

[0062] In this embodiment, the RF front-end module may include multiple transmission links. For example, the RF front-end module includes two transmission links: a low-band (LB) transmission link and a mid-band (MB) transmission link. With multiple transmission paths, the capacitor units on the output path of the power amplifier circuit 20, especially the capacitor units of the resonant circuit, have a capacitance value less than or equal to 0.8pF. Using interdigitated capacitors can more effectively reduce the overall size of the RF front-end module.

[0063] In some embodiments, where the power amplifier circuit 20 includes a first power amplifier unit 21a and a second power amplifier unit 21b, the matching network 40 correspondingly includes a first matching network 40a and a second matching network 40b. For example... Figure 5 and Figure 6 As shown, the LB signal input port is connected to the input of the first power amplifier unit 21a, and the output of the first power amplifier unit 21a is connected to the first matching network 40a. The MB signal input port is connected to the input of the second power amplifier unit 21b, and the output of the second power amplifier unit 21b is connected to the second matching network 40b. The resonant circuit can be specifically connected to the output of the second matching network 40b. The output of the first matching network 40a and the output of the resonant circuit are connected to the same node P. The capacitance value of the capacitor unit in this resonant circuit is generally small, and interdigitated capacitors can be used to meet the miniaturization requirements of the RF front-end module.

[0064] In some implementations, the resonant circuit can be used to suppress higher harmonic signals. It is understood that the frequency of higher harmonic signals is generally greater than or equal to twice the fundamental frequency f0, such as 2f0, 3f0, 4f0, 5f0, 6f0, etc. The embodiments of this application do not limit this.

[0065] In one exemplary implementation, such as Figure 5 As shown, the resonant circuit connected to the output path of the second power amplifier unit 21b may include a seventh inductor L23 and a seventh capacitor C23 connected in parallel. One end of the parallel connection between the seventh capacitor C23 and the seventh inductor L23 is connected to the output terminal of the second matching network 40b, and the other end is connected to node P to suppress high-order harmonic signals. Since the capacitance value of the seventh capacitor C23, which is configured to suppress high-order harmonic signals, is generally small, an interdigitated capacitor is used and disposed on the substrate 100 to reduce the area occupied on the substrate 100.

[0066] In yet another exemplary embodiment, the resonant circuit connected to the output path of the second power amplifier unit 21b may include a first resonant unit and a second resonant unit.

[0067] It is understood that the first resonant unit and the second resonant unit can be connected between the second power amplifier unit 21b and the second matching network 40b, or between the second matching network 40b and node P, or respectively between the second power amplifier unit 21b and the second matching network 40b and the second matching network 40b and node P. This application does not limit the specific embodiments.

[0068] In a preferred embodiment, the first resonant unit and the second resonant unit are connected between the second matching network 40b and node P. For example... Figure 5 As shown, the first resonant unit includes a seventh inductor L23 and a seventh capacitor C23 connected in parallel, and the second resonant unit includes an eighth inductor L26 and an eighth capacitor C25 connected in series. One end of the first resonant unit is connected to the output of the second matching network 40b, and the other end is connected to node P; one end of the second resonant unit is connected between the first resonant unit and node P, and the other end is grounded.

[0069] It is understood that the positions of the first resonant unit and the second resonant unit can be interchanged, and the connection positions of the eighth inductor L26 and the eighth capacitor C25 can also be interchanged; this application does not limit these possibilities. Specifically, the second resonant unit may be closer to the output terminal of the second matching network 40 than the first resonant unit; one end of the eighth capacitor C25 may be grounded. Figure 5 An example is shown where one end of the eighth capacitor C25 is connected to the path between the first resonant unit and node P, and the other end is connected to one end of the eighth inductor L26, the other end of which is grounded.

[0070] In this embodiment, both the first resonant unit and the second resonant unit can be used to suppress high-order harmonic signals. Therefore, the capacitance values ​​of the seventh capacitor C23 and the eighth capacitor C25 included therein are generally small, and interdigitated capacitors can be used, which is beneficial to reducing the size of the RF front-end module. The seventh capacitor C23 and the eighth capacitor C25 can be directly disposed on the substrate 100.

[0071] For example, the second resonant unit can be used to suppress a third harmonic signal, wherein the frequency of the third harmonic signal is greater than or equal to four times the fundamental frequency.

[0072] In this embodiment of the application, the first matching network 40a may include a multi-order matching circuit, and the second matching network 40b may also include a multi-order matching circuit. The order of the matching circuit included in the first matching network 40a may be greater than, less than or equal to the order of the matching circuit included in the second matching network 40b. This embodiment of the application does not limit this.

[0073] In some implementations, the first matching network 40a includes at least a two-order matching circuit, and the second matching network 40b includes at least a one-order matching circuit. The order of the matching circuit included in the first matching network is greater than or equal to the order of the matching circuit included in the second matching network.

[0074] In a preferred embodiment, the order of the matching circuit included in the first matching network 40a is greater than the order of the matching circuit included in the second matching network 40b.

[0075] It is understood that the matching circuit can be a π-type matching circuit, an L-type matching circuit, or a T-type matching circuit. In the first matching network 40a or the second matching network 40b, the matching circuits of each order can adopt the same type of matching circuit or different types of matching circuits, and this application embodiment does not limit this.

[0076] In this embodiment, since the LB band is lower than the MB band, the output impedance of the first power amplifier unit 20a in the LB band is lower than that of the second power amplifier unit 20b in the MB band. Therefore, a larger impedance variation range and a wider bandwidth are required. Consequently, the first matching network 40a connected to the first power amplifier unit 20a requires a matching circuit of a higher order to achieve the requirement of a larger impedance variation range.

[0077] In one exemplary implementation, such as Figure 5 and Figure 6 As shown, the first power amplifier unit 20a operates in the frequency band of [600MHz, 920MHz]. The first matching network 40a includes three-order matching circuits connected in series on the output path of the first power amplifier unit 20a, namely the first primary matching circuit 41a, the middle matching circuit 42a, and the first final matching circuit 43a. The second power amplifier unit 20b operates in the frequency band of [1710MHz, 2200MHz]. The second matching network 40b includes two-order matching circuits connected in series on the output path of the second power amplifier unit 20b, namely the second primary matching circuit 41b and the second final matching circuit 42b.

[0078] In one feasible implementation, the first primary matching circuit 41a includes a first inductor L11, a second inductor L14, a first capacitor C111, and a second capacitor C112. The first end of the first inductor L11 is connected to the output end of the first power amplifier unit 20a. The first capacitor C111 and the second capacitor C112 are connected in parallel. One end of the parallel-connected first capacitor C111 and the second capacitor C112 is connected to the second end of the first inductor L11, and the other end is connected to the first end of the second inductor L14. The second end of the second inductor L14 is grounded.

[0079] In this embodiment of the application, the parallel equivalent capacitance of the first capacitor C111 and the second capacitor C112 is greater than or equal to 10pF.

[0080] It is understandable that the first capacitor C111 and the second capacitor C112 can be SMD capacitors. With the same capacitance value, using SMD capacitors is beneficial to reducing the occupied area.

[0081] Optionally, the first capacitor C111 and the second capacitor C112 can be directly disposed on the substrate 100.

[0082] In this embodiment, the first primary matching circuit 41a has a smaller impedance than the intermediate matching circuit 42a and the first final matching circuit 43a because it is close to the output terminal of the first power amplifier unit 20a on the output path. Therefore, the current flowing through the first primary matching circuit 41a is relatively large. Consequently, a capacitor with a large capacitance value, such as greater than 10pF, is used in the first primary matching circuit 41a. However, if the capacitance value of a single capacitor (especially an SMD capacitor) is too large, it will reduce the Q value of the first primary matching circuit 41a and increase losses. Furthermore, since the transmit link has high requirements for the Q value of the first primary matching circuit 41a, the capacitor in the first primary matching circuit 41a is split into two capacitors with smaller capacitance values ​​connected in parallel, namely the first capacitor C111 and the second capacitor C112. This can reduce the size to a certain extent and improve the Q value of the first primary matching circuit 41a, thereby reducing losses.

[0083] In another feasible implementation, such as Figure 5 As shown, the intermediate-order matching circuit 42a may include a third inductor L12, a fourth inductor L15, and a third capacitor C12; the first end of the third inductor L12 is connected to the output end of the first primary-order matching circuit 41a (e.g., the second end of the first inductor L11), the second end of the third inductor L12 is connected to the first end of the third capacitor C12, the second end of the third capacitor C12 is connected to the first end of the fourth inductor L15, and the second end of the fourth inductor L15 is grounded.

[0084] In another feasible implementation, such as Figure 6 As shown, the RF front-end module may also include a fourth capacitor C14, which is connected in parallel across the two ends of the third inductor L12. The fourth capacitor C14 may be an interdigitated capacitor.

[0085] It is understandable that since the fourth capacitor C14 is connected in parallel with the third inductor L12 in the intermediate matching circuit 42a, it is farther from the output terminal of the power amplifier circuit 20 than the first primary matching circuit 41a on the output path of the power amplifier circuit 20. Therefore, the fourth capacitor C14 can be preferentially placed on the substrate 100 to reduce the use of jumpers and simplify the substrate layout.

[0086] Specifically, the fourth capacitor C14 and the third inductor L12 are connected in parallel to form a resonant circuit to suppress the first harmonic signal, the frequency of which is greater than or equal to 5 times the fundamental frequency.

[0087] In this embodiment, a fourth capacitor C14 is connected in parallel with the third inductor L12 of the intermediate-order matching circuit 42a to form a harmonic circuit that can suppress high-order harmonic signals. Since the capacitance value of the fourth capacitor C14 is generally small, an interdigitated capacitor can be used to reduce the area occupied on the substrate 100, thereby reducing the overall size of the RF front-end module while suppressing high-order harmonic signals.

[0088] In another feasible implementation, the first final-order matching circuit 43a includes inductors L13 and L16 and capacitor C13. L13 is connected in series between the second end of the third inductor L12 and node P. C13 is connected in series with L16, wherein one end of C13 is connected between L13 and node P, and one end of L16 is grounded.

[0089] In one feasible implementation, such as Figure 5 As shown, the second primary matching circuit 41b includes a fifth inductor L21, a sixth inductor L24, and a fifth capacitor C21; the first end of the fifth inductor L21 is connected to the output end of the second power amplifier unit 20b, the second end of the fifth inductor L21 is connected to the first end of the fifth capacitor C21, the second end of the fifth capacitor C21 is connected to the first end of the sixth inductor L24, and the second end of the sixth inductor L24 is grounded.

[0090] It is understandable that the fifth capacitor C21 has a large capacitance value, and can be an SMD capacitor or a stacked capacitor. The fifth capacitor C21 can be directly set on the substrate 100.

[0091] Optionally, since the second primary matching circuit 41b is located near the output terminal of the second power amplifier unit 20b on the output path, its impedance is smaller than that of the second final matching circuit 42b. Therefore, the current flowing through the second primary matching circuit 41b is relatively large. Consequently, a capacitor with a larger capacitance value, such as greater than 10pF, is used in the second primary matching circuit 41b. However, if the capacitance value of a single capacitor (especially an SMD capacitor) is too large, it will reduce the Q value of the second primary matching circuit 41b and increase losses. Furthermore, since the transmit link has relatively high Q value requirements for the second primary matching circuit 41b, the fifth capacitor C21 in the second primary matching circuit 41b can also be split into two smaller capacitors connected in parallel. This can reduce the size to some extent while improving the Q value of the second primary matching circuit 41b and reducing losses.

[0092] In another feasible implementation, such as Figure 6 As shown, the RF front-end module may also include a sixth capacitor C24, which is connected in parallel across the two ends of the fifth inductor L21. The sixth capacitor C24 may be an interdigitated capacitor.

[0093] Specifically, the sixth capacitor C24 and the fifth inductor L21 are connected in parallel to form a resonant circuit to suppress the second harmonic signal, the frequency of which is greater than or equal to three times the fundamental frequency.

[0094] In this embodiment, a sixth capacitor C24 is connected in parallel with the fifth inductor L21 of the second primary matching circuit 41b to form a harmonic circuit that can suppress high-order harmonic signals. Since the capacitance value of the sixth capacitor C24 is generally small, interdigitated capacitors can be used to reduce the area occupied on the substrate 100, thereby reducing the overall size of the RF front-end module while suppressing high-order harmonic signals.

[0095] In another feasible implementation, the second final-order matching circuit 42b may include inductors L22 and L25 and capacitor C22. L22 is connected in series between the second terminal of the fifth inductor L21 and node P. C22 is connected in series with L25, wherein one end of C22 is connected between L22 and node P, and one end of L25 is grounded. Specifically, the first end of L22 may be connected to the second terminal of the fifth inductor L21, and the first end of L22 may be connected to one end of the seventh inductor L23 and the seventh capacitor C23 connected in parallel.

[0096] Optionally, the sixth capacitor C24 is an interdigitated capacitor, which can be set on the power amplifier chip 200, specifically on the amplifier chip where the second power amplifier unit 21b is located.

[0097] Optionally, the fifth inductor L21 can be implemented using bonding wires. For example, it can be connected from the first end of the fifth capacitor C21 to the power amplifier chip 200 via bonding wires, specifically to the amplifier chip where the second power amplifier unit 21b is located.

[0098] In this embodiment, since the operating frequency band of the first power amplifier unit 21a is lower than that of the second power amplifier unit 21b, the capacitance value of the capacitor in its first matching network 40a is about twice that of the capacitor in the second matching network 40b. If the capacitor in the first matching network 40a is an interdigitated capacitor, it will occupy a larger area compared to SMD capacitors and stacked capacitors. The sixth capacitor C24 has a small capacitance value, for example, less than 0.8pF, and is connected in parallel with the fifth inductor L21 in the second primary matching circuit 41b. Therefore, it is close to the power amplifier chip 200. Thus, the sixth capacitor C24 can be placed on the power amplifier chip 200, and the fifth inductor L21 can be implemented using bonding wires, which helps to reduce the overall size of the RF front-end module and achieve miniaturization.

[0099] In some implementations, please refer to Figure 3 and Figure 4 The radio frequency front-end module may also include a second DC blocking unit 60, which is connected between the switching unit 30 and the antenna port ANT. Specifically, one end of the second DC blocking unit 60 is connected to the switching unit 30.

[0100] Specifically, such as Figure 5 and Figure 6 As shown, the second DC blocking unit 60 can specifically be a DC blocking capacitor C31. One end of the DC blocking capacitor C31 is connected to the switching unit 30, and the other end is connected to one end of a resonant circuit (specifically, a capacitor C32 and an inductor L32 connected in parallel).

[0101] In this embodiment, the DC blocking capacitor C32 can be an SMD capacitor disposed on the substrate 100, or it can be a stacked capacitor disposed on the switching chip 300 where the switching unit 30 is located. This embodiment does not limit the specific application.

[0102] In some embodiments, a first set of wire-wound inductors with a first linewidth is connected between the signal input port and the output of the power amplifier circuit 20; a second set of wire-wound inductors with a second linewidth is connected between the output of the power amplifier circuit 20 and the second DC blocking unit 60; and a third set of wire-wound inductors with a third linewidth is connected between the second DC blocking unit 60 and the antenna port ANT.

[0103] In one specific embodiment, the first line width is smaller than the second line width.

[0104] In one specific embodiment, the third line width is also smaller than the second line width.

[0105] In one specific embodiment, the first line width is smaller than the second line width, and the third line width is also smaller than the second line width.

[0106] In one specific embodiment, the first line width can be greater than or less than the third line width. Preferably, the first line width is greater than the third line width.

[0107] In this embodiment, the inductor in the RF front-end module can be an SMD inductor, an inductor implemented by bonding wires (or jumpers), a wire-wound inductor directly disposed on the substrate 100, etc. This embodiment does not limit the inductor.

[0108] It should be noted that, in this application, the first group of wire-wound inductors can be understood as inductors connected between the signal input port and the output terminal of the power amplifier circuit 20 and implemented by wire winding. In the circuit of the RF front-end module, there may be one inductor or multiple inductors. This application embodiment does not limit this.

[0109] Similarly, the second set of wire-wound inductors can be understood as inductors connected between the output of the power amplifier circuit 20 and the second DC blocking unit 60, implemented using a wire-wound method. Specifically, it can be one or more inductors in the matching network 40, such as L11, L14, L15, L24, L25, etc. The third set of wire-wound inductors can be understood as inductors connected between the second DC blocking unit 60 and the antenna port ANT, implemented using a wire-wound method. For example, it can be... Figure 5 L32, etc.

[0110] It is understood that the first line width can be the minimum line width, the maximum line width, or the average line width in the first group of wound inductors. Similarly, the second line width can be the minimum line width, the maximum line width, or the average line width in the second group of wound inductors, and the third line width can be the minimum line width, the maximum line width, or the average line width in the third group of wound inductors. This application does not limit this.

[0111] It is understood that the thicknesses of the three sets of wire-wound inductors may be approximately equal or unequal. In an exemplary embodiment, the thicknesses of the first set of wire-wound inductors and the third set of wire-wound inductors are both greater than the thickness of the second set of wire-wound inductors.

[0112] In this embodiment, the overcurrent gradually increases from the input signal port to the second DC blocking unit 60. If a thinner inductor is used along this path, it is easily burned out. If an inductor with the same linewidth is used, the area occupied by the substrate 100 increases. Therefore, the linewidth of the wire-wound inductor between the signal input port and the second DC blocking unit 60 can be gradually increased. Specifically, the first group of wire-wound inductors is closer to the signal input port than the second group of wire-wound inductors; therefore, the first linewidth is smaller than the second linewidth. Since the second DC blocking unit 60 isolates the DC signal, the inductance between the second DC blocking unit 60 and the antenna port ANT is unaffected. Therefore, the third linewidth of the third group of wire-wound inductors is at least smaller than the second linewidth of the second group of wire-wound inductors.

[0113] Through the embodiments of this application, the linewidth of the winding inductor can be flexibly set according to the magnitude of the overcurrent, which not only helps to reduce the area occupied by the substrate 100, but also prevents the inductor from being burned out and improves the stability of the RF front-end module.

[0114] In other implementations, such as Figure 4 As shown, the substrate 100 is also provided with a power supply port and a CMOS chip 400. The power supply port is used to provide power to the power amplifier chip 200. The CMOS chip can integrate analog control circuitry to control the opening and closing of the switching unit.

[0115] In one specific embodiment, the power amplifier chip 200 is located closer to the power supply port than other chips (e.g., the CMOS chip 400), and the CMOS chip 400 is located closer to the signal input port than the power amplifier chip 200. It is understood that... Figure 4 The location of the signal input port, antenna port, and power supply port is only shown as an example. When there are multiple signal input ports, such as LB signal input port and MB signal input port, the CMOS chip 400 can be set in a position close to both signal input ports. This will not be described in detail in the embodiments of this application.

[0116] In one feasible implementation, the substrate 100 includes a first region and a third region. The first region and the third region may be arranged adjacently or spaced apart. This application embodiment does not limit the specific arrangement.

[0117] For example, such as Figure 4 As shown, the first and third regions are spaced apart. The signal input port and the power supply port are located on the same side of the substrate 100. The CMOS chip 400 and the power amplifier chip 200 are both located in the first region, and the switch chip 200 is located in the third region. The distance between the switch chip 300 and the CMOS chip 400 is less than the distance between the switch chip 300 and the power amplifier chip 200.

[0118] In another feasible embodiment, the substrate 100 further includes a second region located between the first region and the third region, and adjacent to both the first region and the third region, as shown below. Figure 4 As shown. The aforementioned first group of wire-wound inductors, second group of wire-wound inductors, and third group of wire-wound inductors are all disposed on the substrate 100. The first group of wire-wound inductors is located in the first region and is disposed around the periphery of the power amplifier chip 200. The second group of wire-wound inductors is located in the second region, and the third group of wire-wound inductors is located in the third region. The arrangement of each group of wire-wound inductors according to the flow direction of the radio frequency signal can simplify the substrate layout to the greatest extent and reduce the substrate area occupied, which is conducive to reducing the overall size of the radio frequency front-end module and realizing miniaturization.

[0119] It is understandable that the first set of wire-wound inductors can be specifically located on the left side of the power amplifier chip 200 (the area between the power amplifier chip 200 and the CMOS chip 400 near the power amplifier chip 200), the right side of the power amplifier chip 200, and the area between the power amplifier chip 200 and the power supply port.

[0120] It is understandable that within the same group of wire-wound inductors (e.g., the first group of wire-wound inductors), the line widths of each wire-wound inductor can be the same or different.

[0121] In an exemplary embodiment, for example in the second set of wire-wound inductors, the wire-wound inductors closer to the output terminal of the power amplifier circuit 20 have smaller line widths, while the wire-wound inductors closer to the second DC blocking unit 60 have wider line widths.

[0122] In this embodiment, the power amplifier circuit 20 may employ at least one first-order amplification unit. In one implementation, the power amplifier circuit 20 includes a first power amplifier unit 21a and a second power amplifier unit 21b. The first power amplifier unit 21a may employ at least one first-order amplification unit, and the second power amplifier unit 21b may also employ at least one first-order amplification unit. The order of the amplification unit in the first power amplifier unit 21a and the order of the second power amplifier unit 21b may be the same or different. For example, as... Figure 5 and Figure 6 As shown, both the first power amplifier unit 21a and the second power amplifier unit 21b include a third-order amplifier unit.

[0123] In some embodiments, the power amplifier circuit 20 includes a first-order amplification unit and a second-order amplification unit, the second-order amplification unit being the next-order amplification unit after the first-order amplification unit; the first set of wire-wound inductors includes a first wire-wound inductor and a second wire-wound inductor, one end of the first wire-wound inductor being connected to the first-order amplification unit and the other end being connected to the power supply port (not shown in the figure); one end of the second wire-wound inductor being connected to the second-order amplification unit and the other end being connected to the power supply port (not shown in the figure); the linewidth of the first wire-wound inductor is smaller than the linewidth of the second wire-wound inductor. The first-order amplification unit and the second amplification unit are any two amplification units in the first power amplifier unit 21a.

[0124] In this embodiment, the first-order amplification unit is located closer to the input terminal of the power amplifier circuit 20 than the second-order amplification unit.

[0125] It is understandable that the first and second wire-wound inductors can be power supply inductors, which, together with capacitors, can achieve voltage conversion and ripple suppression, so as to provide stable power supply to the amplification transistors included in each stage of the amplification unit.

[0126] In this embodiment, each amplification unit may include multiple amplification transistors, specifically MOS transistors, such as NMOS transistors or PMOS transistors. A MOS transistor includes a gate (G), a source (S), and a drain (D). For example, when an NMOS transistor is used, the drain is connected to the power supply port; when a PMOS transistor is used, the source is connected to the power supply port. The amplification transistor may also be a BJT transistor, specifically including an emitter (E), a base (B), and a collector (C). When a BJT transistor is used, the collector is connected to the power supply port.

[0127] In this embodiment, the power supply inductor connected to the amplification unit is a wire-wound inductor. The closer it is to the input terminal of the power amplifier circuit 20, the smaller the overcurrent; the closer it is to the output terminal of the power amplifier circuit 20, the larger the overcurrent. Therefore, the linewidth of the first wire-wound inductor near the input terminal of the power amplifier circuit 20 is smaller than the linewidth of the second wire-wound inductor near the output terminal of the power amplifier circuit 20. The wire-wound inductor is placed on the substrate 100. By adopting this embodiment, the inductor linewidth can be flexibly set, which can both prevent the inductor from being burned out and help reduce the size of the RF front-end module.

[0128] In one specific embodiment, the power amplifier circuit 20 includes a first power amplifier unit 21a and a second power amplifier unit 21b. Each of the first power amplifier unit 21a and the second power amplifier unit 21b includes a multi-stage amplification unit. The amplification unit closer to the input end is connected to a wire-wound inductor with a smaller linewidth. The amplification unit closer to the output end is connected to a wire-wound inductor with a larger linewidth. This flexible setting of the wirewidth of the wire-wound inductor can both prevent the inductor from burning out and help reduce the size of the RF front-end module.

[0129] In some implementations, the radio frequency front-end module also includes an electrostatic discharge (ESD) protection unit. The first end of the ESD protection unit is connected to a node on the output path of the power amplifier circuit 20 and close to the antenna port, and the second end of the ESD protection unit is grounded.

[0130] In one specific implementation, such as Figure 5 and Figure 6 As shown, the electrostatic protection unit may include a ninth inductor L31, the inductance value of which is in the range of [22nH, 33nH].

[0131] Specifically, one end of the ninth inductor L31 is connected to the path between the parallel-connected capacitor C32 and the other end of the inductor L32 (resonant circuit) and the antenna port ANT, while the other end of the ninth inductor L31 is grounded.

[0132] Specifically, the inductance value of the ninth inductor L31 can be 22nH, 25nH, 27nH, 30nH, 33nH, etc., and this application embodiment does not limit it.

[0133] In this embodiment, the inductance value of the ninth inductor L31 is mainly based on a trade-off between electrostatic discharge (ESD) signals and radio frequency (RF) signals. A larger inductance value of the ninth inductor L31 has less impact on the RF signal, but an excessively large inductance value will affect the ESD signal. Therefore, the inductance value of the ninth inductor L31 is within this range, which can take into account the impact of both RF signals and ESD signals.

[0134] In some implementations, such as Figure 7 As shown in the figure, the RF front-end module also includes a first DC blocking unit 50, which is connected to the input path of the power amplifier circuit 20. Specifically, the first DC blocking unit 50 is connected between the signal input port and the input port of the power amplifier circuit 20.

[0135] In one specific embodiment, the first DC blocking unit 50 includes a capacitor, which is a stacked capacitor.

[0136] In one feasible implementation, please refer to Figure 4 The radio frequency front-end module also includes a CMOS chip 400 disposed on the substrate 100, and the first DC blocking unit 50 may be disposed on the CMOS chip 400.

[0137] In this embodiment, the signal input port is closer to the CMOS chip 400 than the power amplifier chip 200, and the capacitance of the first DC blocking unit 50 is relatively large. If directly mounted on the substrate 100, an SMD capacitor would typically be used. However, for the same capacitance value, a stacked capacitor has a smaller area than an SMD capacitor. Therefore, using a stacked capacitor for the capacitance of the first DC blocking unit 50 connected to the input path of the power amplifier circuit 20, and mounting it on the CMOS chip, is more advantageous in terms of saving space compared to directly mounting it on the substrate 100. Furthermore, mounting the stacked capacitor on the CMOS chip is more cost-effective than mounting it on the power amplifier chip 200.

[0138] Specifically, the signal input port can be connected to the first DC blocking unit 50 on the CMOS chip via a third bonding wire, and then led out from the first DC blocking unit 50 via a fourth bonding wire to the input port on the power amplifier chip 200.

[0139] In one exemplary implementation, such as Figure 5 and Figure 6 As shown, the power amplifier circuit 20 includes a first power amplifier unit 21a and a second power amplifier unit 21b. The signal input ports include, for example, an LB signal input port and an MB signal input port. The first DC blocking unit 50 includes a first DC blocking capacitor C1 and a second DC blocking capacitor C2. The first DC blocking capacitor C1 is connected between the LB signal input port and the first power amplifier unit 21a, and the second DC blocking capacitor C2 is connected between the MB signal input port and the second power amplifier unit 21b.

[0140] In this embodiment, both the first DC blocking capacitor C1 and the second DC blocking capacitor C2 are stacked capacitors and are both disposed on the CMOS chip, which can reduce the area occupied by the substrate 100 and save costs.

[0141] In some implementations, such as Figures 4-6 As shown, the RF front-end module also includes a coupler CPL, which is disposed on the substrate 100. Specifically, the coupler CPL includes a main line connected to the transmission path between the switching unit 30 and the antenna port ANT, and a coupling line coupled to the main line. The isolation port of the coupling line is grounded through a resistor R1 and a ninth capacitor C33; wherein, the resistor R1 and the ninth capacitor C33 are both integrated on the power amplifier chip 200 or the switching chip 300.

[0142] In this embodiment, integrating the resistor R1 and the ninth capacitor C33 of the coupler CPL onto the power amplifier chip 200 or the switch chip 300 can help save space and cost.

[0143] Please see Figure 8 and Figure 9 This application also provides a radio frequency front-end module. Figure 8 This is a circuit structure diagram of an RF front-end module. Figure 9 This is a layout diagram of a substrate for an RF front-end module. Specifically, as shown... Figure 8 and Figure 9 As shown, the RF front-end module includes a substrate 100 and an antenna port ANT, a signal input port, a power amplifier chip 200, a switch chip 300, and a coupler CPL disposed on the substrate. The switch chip 300 integrates a switch unit 30, and the power amplifier chip 20 integrates a power amplifier circuit 20. The power amplifier circuit 20 is connected between the signal input port and the antenna port ANT, and the switch unit 30 is connected between the power amplifier circuit 20 and the antenna port ANT. The coupler CPL includes a main line connected to the transmission path between the switch unit 30 and the antenna port ANT, and a coupling line coupled to the main line. The isolation port of the coupling line is grounded through a resistor R1 and a ninth capacitor C33; wherein, both the resistor R1 and the ninth capacitor C33 are integrated on the power amplifier chip 200 or the switch chip 300.

[0144] in, Figure 9 The locations of the signal input port and the antenna port ANT are shown only as examples, and the specific locations are not limited in the embodiments of this application.

[0145] In this embodiment, the resistor R1 and the ninth capacitor C33 of the coupler CPL are integrated on the power amplifier chip 200 or the switch chip 300. Compared with directly setting them on the substrate 100, this can reduce the number of SMD components (resistors and capacitors) on the substrate, which not only saves space but also saves costs.

[0146] In some implementations, the distance between the coupler CPL and the switching chip 300 is less than the distance between the coupler CPL and the power amplifier chip 200.

[0147] For example, resistor R1 and ninth capacitor C33 are integrated on switch chip 300.

[0148] In this embodiment, since the coupler CPL is closer to the switch chip 300, integrating both resistor R1 and the ninth capacitor C33 onto the switch chip 300 reduces the use of SMD components, saving both space and cost. Furthermore, since the power amplifier chip 200 contains high-power radio frequency signals, integrating resistor R1 and the ninth capacitor C33 onto the power amplifier chip 200 would negatively impact its coupler performance to some extent. Therefore, integrating resistor R1 and the ninth capacitor C33 onto the switch chip 300 helps minimize the impact on coupler performance.

[0149] In other implementations, the coupler CPL is positioned closer to the antenna port than the switch chip 300 and the power amplifier chip 200.

[0150] In the embodiments of this application, the coupler is positioned near the antenna port, which facilitates the detection of the output power of the power amplifier circuit to ensure signal quality and adjust the transmission power.

[0151] In other embodiments, the switching unit 30 in the switching chip 300 is connected to components disposed on the substrate 100 via at least two first bonding wires, and the isolation port of the coupling line disposed on the substrate 100 is connected to the resistor R1 and the ninth capacitor C33 disposed on the switching chip 300 via a second bonding wire. There is a first distance between any first bonding wire and the second bonding wire, and a second distance between any two adjacent first bonding wires. The first distance is greater than or equal to the second distance.

[0152] It is understood that the switching unit 30 in the switching chip 300 can be connected to other components on the substrate 100 via multiple first bonding wires, for example, such as Figure 5 As shown, it is connected to the DC blocking capacitor C31, the first matching network 40a, and the seventh capacitor C23 and the seventh inductor L23 connected in parallel. The first distance can be understood as the distance between any one first bonding wire and the second bonding wire, or as the minimum distance among the distances between multiple first bonding wires and the second bonding wires. The second distance can be understood as the maximum, minimum, or average distance among the distances between two adjacent first bonding wires. In other words, the distance between the second bonding wire and the surrounding first bonding wires should be as large as possible, and at least not less than the distance between two adjacent first bonding wires.

[0153] In this embodiment, resistor R1 and ninth capacitor C33 are integrated on switch chip 300, and the second bonding line connected to resistor R1 and ninth capacitor C33 is set as far away as possible from the first bonding line in switch chip 300 that transmits radio frequency signals, so as to ensure that the directivity of the coupler is greater than 13 in the frequency range of 600MHz-2700MHz, which helps to reduce the impact of radio frequency signals on the performance of the coupler.

[0154] In a preferred embodiment, the first distance is greater than the second distance, which is more conducive to reducing the impact of radio frequency signals on coupler performance.

[0155] This application also provides an embodiment of a radio frequency front-end module, such as... Figure 4 and Figure 7 As shown, the RF front-end module specifically includes a substrate 100, a signal input port, an antenna port ANT, a power amplifier chip 200, and a CMOS chip 400 disposed on the substrate 100. The power amplifier chip 200 integrates a power amplifier circuit 20, which is connected between the signal input port and the antenna port ANT. A first DC blocking unit 50 is connected to the input path of the power amplifier circuit 20; specifically, the first DC blocking unit 50 is connected between the signal input port and the power amplifier circuit 20. The first DC blocking unit 50 is disposed on the CMOS chip 400.

[0156] In some embodiments, the first DC blocking unit 50 includes a capacitor, which is a stacked capacitor.

[0157] In this embodiment, the signal input port is closer to the CMOS chip 400 than the power amplifier chip 200. The capacitance of the first DC blocking unit 50 is relatively large. If it were directly mounted on the substrate 100, an SMD capacitor would typically be used. However, for the same capacitance value, a stacked capacitor has a smaller area than an SMD capacitor. Therefore, using a stacked capacitor for the capacitance of the first DC blocking unit 50 connected to the input path of the power amplifier circuit 20, and mounting it on the CMOS chip, is more advantageous in terms of saving space compared to mounting it directly on the substrate 100. Furthermore, mounting the stacked capacitor on the CMOS chip is more cost-effective than mounting it on the power amplifier chip 200.

[0158] Specifically, the signal input port can be connected to the first DC blocking unit 50 on the CMOS chip via a third bonding wire, and then led out from the first DC blocking unit 50 via a fourth bonding wire to the input port on the power amplifier chip 200.

[0159] In one exemplary implementation, such as Figure 5 and Figure 6As shown, the power amplifier circuit 20 includes a first power amplifier unit 21a and a second power amplifier unit 21b. The signal input ports include, for example, an LB signal input port and an MB signal input port. The first DC blocking unit 50 includes a first DC blocking capacitor C1 and a second DC blocking capacitor C2. The first DC blocking capacitor C1 is connected between the LB signal input port and the first power amplifier unit 21a, and the second DC blocking capacitor C2 is connected between the MB signal input port and the second power amplifier unit 21b.

[0160] In this embodiment, both the first DC blocking capacitor C1 and the second DC blocking capacitor C2 are stacked capacitors and are both disposed on the CMOS chip, which can reduce the area occupied by the substrate 100 and save costs.

[0161] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A radio frequency front-end module, characterized in that, include: A substrate and a power amplifier chip disposed on the substrate, wherein the power amplifier chip integrates a power amplifier circuit. The radio frequency front-end module also includes a capacitor unit, which is connected to the output path of the power amplifier circuit. The capacitor unit is an interdigitated capacitor.

2. The radio frequency front-end module according to claim 1, characterized in that, The radio frequency front-end module also includes a resonant circuit, which is connected to the output path of the power amplifier circuit, and the resonant circuit includes the capacitor unit.

3. The radio frequency front-end module according to claim 2, characterized in that, The capacitor unit includes a first capacitor unit; the resonant circuit includes a parallel resonant circuit connected to the output path of the power amplifier circuit; the parallel resonant circuit includes a first inductor unit and the first capacitor unit connected in parallel; the first capacitor unit is an interdigitated capacitor; and / or... The capacitor unit includes a second capacitor unit, and the resonant circuit includes a series resonant circuit connected to the output path of the power amplifier circuit. The series resonant circuit includes a second inductor unit and a second capacitor unit connected in series, and the second capacitor unit is an interdigitated capacitor.

4. The radio frequency front-end module according to claim 3, characterized in that, The parallel resonant circuit is connected in series on the output path of the power amplifier circuit; one end of the series resonant circuit is connected to a node on the output path of the power amplifier circuit, and the other end of the series resonant circuit is grounded.

5. The radio frequency front-end module according to claim 1, characterized in that, The capacitance value of the capacitor unit is less than or equal to 0.8pF.

6. The radio frequency front-end module according to claim 1, characterized in that, The substrate includes a first metal layer and at least one second metal layer, wherein the first metal layer is a ground layer and the capacitor unit is disposed on any of the second metal layers.

7. The radio frequency front-end module according to claim 2, characterized in that, The substrate is also provided with a switch chip and an antenna port. The switch chip integrates a switch unit, which is connected between the power amplifier circuit and the antenna port. The RF front-end module also includes a matching network. The first end of the matching network is connected to the output end of the power amplifier circuit, and the second end of the matching network is connected to the switch unit.

8. The radio frequency front-end module according to claim 7, characterized in that, The resonant circuit is connected between the switching unit and the antenna port.

9. The radio frequency front-end module according to claim 7, characterized in that, The power amplifier circuit includes a first power amplifier unit and a second power amplifier unit, wherein the operating frequency of the first power amplifier unit is lower than the operating frequency of the second power amplifier unit; the resonant circuit is connected between the second power amplifier unit and the switching unit.

10. The radio frequency front-end module according to claim 9, characterized in that, The matching network includes a first matching network and a second matching network. The output terminal of the first power amplifier unit is connected to the first matching network, and the second matching network is connected between the output terminal of the second power amplifier unit and the resonant circuit. The output terminal of the first matching network and the output terminal of the resonant circuit are connected to the same node.

11. The radio frequency front-end module according to claim 10, characterized in that, The first matching network includes at least a two-order matching circuit, and the second matching network includes at least a one-order matching circuit. The order of the matching circuit in the first matching network is greater than or equal to the order of the matching circuit in the second matching network.

12. The radio frequency front-end module according to claim 11, characterized in that, Any of the matching circuits described herein is a π-type matching circuit, an L-type matching circuit, or a T-type matching circuit.

13. The radio frequency front-end module according to claim 10, characterized in that, The first power amplifier unit operates in the frequency band of [600MHz, 920MHz], and the first matching network includes a third-order matching circuit connected in the output path of the first power amplifier unit; the second power amplifier unit operates in the frequency band of [1710MHz, 2200MHz], and the second matching network includes a second-order matching circuit connected in the output path of the second power amplifier unit.

14. The radio frequency front-end module according to claim 13, characterized in that, The third-order matching circuit includes a first primary-order matching circuit, which includes a first inductor, a second inductor, a first capacitor, and a second capacitor. The first end of the first inductor is connected to the output end of the first power amplifier unit. The first capacitor and the second capacitor are connected in parallel. One end of the first capacitor and the second capacitor connected in parallel is connected to the second end of the first inductor, and the other end is connected to the first end of the second inductor. The second end of the second inductor is grounded.

15. The radio frequency front-end module according to claim 14, characterized in that, The parallel equivalent capacitance of the first capacitor and the second capacitor is greater than or equal to 10pF.

16. The radio frequency front-end module according to claim 13, characterized in that, The third-order matching circuit includes a mid-order matching circuit, which includes a third inductor, a fourth inductor, and a third capacitor. The first terminal of the third inductor is connected to the output terminal of the first primary-order matching circuit, the second terminal of the third inductor is connected to the first terminal of the third capacitor, the second terminal of the third capacitor is connected to the first terminal of the fourth inductor, and the second terminal of the fourth inductor is grounded. The radio frequency front-end module also includes a fourth capacitor, which is connected in parallel with the third inductor. The fourth capacitor is an interdigitated capacitor.

17. The radio frequency front-end module according to claim 16, characterized in that, The fourth capacitor and the third inductor are configured to suppress a first harmonic signal, the frequency of which is greater than or equal to 5 times the fundamental frequency.

18. The radio frequency front-end module according to claim 13, characterized in that, The two-stage matching circuit includes a second primary-stage matching circuit, which includes a fifth inductor, a sixth inductor, and a fifth capacitor. The first terminal of the fifth inductor is connected to the output terminal of the second power amplifier unit, the second terminal of the fifth inductor is connected to the first terminal of the fifth capacitor, the second terminal of the fifth capacitor is connected to the first terminal of the sixth inductor, and the second terminal of the sixth inductor is grounded. The radio frequency front-end module also includes a sixth capacitor, which is connected in parallel with the fifth inductor. The sixth capacitor is an interdigitated capacitor.

19. The radio frequency front-end module according to claim 18, characterized in that, The fifth inductor is a bonding wire connecting the first end of the fifth capacitor to the power amplifier chip; and / or, the sixth capacitor is disposed on the power amplifier chip.

20. The radio frequency front-end module according to claim 18, characterized in that, The sixth capacitor and the fifth inductor are configured to suppress a second harmonic signal, the frequency of which is greater than or equal to three times the fundamental frequency.

21. The radio frequency front-end module according to claim 9, characterized in that, The resonant circuit includes a first resonant unit and a second resonant unit connected sequentially on the output path of the second power amplifier unit. The first resonant unit includes a seventh inductor and a seventh capacitor connected in parallel. One end of the second resonant unit is connected to the output path of the second power amplifier unit, and the other end is grounded. The second resonant unit includes an eighth inductor and an eighth capacitor connected in series. The seventh capacitor and the eighth capacitor are interdigitated capacitors.

22. The radio frequency front-end module according to claim 21, characterized in that, The second resonant unit is configured to suppress a third harmonic signal, the frequency of which is greater than or equal to four times the fundamental frequency.

23. The radio frequency front-end module according to claim 9, characterized in that, Both the first power amplification unit and the second power amplification unit are integrated on the power amplification chip; or, the power amplification chip includes a first amplification chip and a second amplification chip, with the first power amplification unit and the second power amplification unit respectively integrated on the first amplification chip and the second amplification chip.

24. The radio frequency front-end module according to claim 7, characterized in that, The RF front-end module further includes a signal input port and a second DC blocking unit. The second DC blocking unit is connected between the switching unit and the antenna port, and one end of the second DC blocking unit is connected to the switching unit. The signal input port is connected to the power amplifier circuit. The first set of wire-wound inductors connected between the signal input port and the output terminal of the power amplifier circuit has a first linewidth; the second set of wire-wound inductors connected between the output terminal of the power amplifier circuit and the second DC blocking unit has a second linewidth; and the third set of wire-wound inductors connected between the second DC blocking unit and the antenna port has a third linewidth. The first line width is smaller than the second line width, and the third line width is smaller than the second line width.

25. The radio frequency front-end module according to claim 24, characterized in that, The substrate is also provided with the signal input port, the power supply port and the CMOS chip. The CMOS chip is located closer to the signal input port than the power amplifier chip, and the power amplifier chip is located closer to the power supply port than the CMOS chip. The substrate includes a first region and a third region. The power amplifier chip and the CMOS chip are located in the first region, and the switch chip is located in the third region. The distance between the switch chip and the CMOS chip is less than the distance between the switch chip and the power amplifier chip.

26. The radio frequency front-end module according to claim 25, characterized in that, The substrate further includes a second region, which is located between the first region and the third region and is adjacent to the first region and the third region; The first group of wire-wound inductors, the second group of wire-wound inductors, and the third group of wire-wound inductors are disposed on the substrate; The first group of wire-wound inductors is located in the first region and on the periphery of the power amplifier chip; the second group of wire-wound inductors is located in the second region; and the third group of wire-wound inductors is located in the third region.

27. The radio frequency front-end module according to claim 24, characterized in that, The power amplifier circuit includes a first-order amplification unit and a second-order amplification unit, wherein the second-order amplification unit is the next-order amplification unit after the first-order amplification unit; the first set of wire-wound inductors includes a first wire-wound inductor and a second wire-wound inductor, one end of the first wire-wound inductor is connected to the first-order amplification unit, and the other end is connected to the power supply port; one end of the second wire-wound inductor is connected to the second-order amplification unit, and the other end is connected to the power supply port; the line width of the first wire-wound inductor is smaller than the line width of the second wire-wound inductor; the first-order amplification unit and the second-order amplification unit are any two of the first power amplifier units.

28. The radio frequency front-end module according to claim 1, characterized in that, The radio frequency front-end module also includes a first DC blocking unit, which is connected to the input path of the power amplifier circuit. The first DC blocking unit includes a stacked capacitor.

29. The radio frequency front-end module according to claim 28, characterized in that, The radio frequency front-end module also includes a CMOS chip disposed on the substrate, and the first DC blocking unit is disposed on the CMOS chip.

30. The radio frequency front-end module according to claim 1, characterized in that, The substrate is also provided with an antenna port, and the radio frequency front-end module also includes an electrostatic discharge (ESD) protection unit. The first end of the ESD protection unit is connected to the node on the output path of the power amplifier circuit and close to the antenna port, and the second end of the ESD protection unit is grounded.

31. The radio frequency front-end module according to claim 30, characterized in that, The electrostatic protection unit includes a ninth inductor, the inductance value of which is in the range of [22nH, 33nH].

32. The radio frequency front-end module according to claim 7, characterized in that, The substrate is also provided with a coupler, the coupler including a main line connected to the transmission path between the switching unit and the antenna port, and a coupling line coupled to the main line, the isolation port of the coupling line being grounded through a resistor and a ninth capacitor; The resistor and the ninth capacitor are both integrated on the power amplifier chip or the switch chip.

33. A radio frequency front-end module, characterized in that, include: The system comprises a substrate, an antenna port disposed on the substrate, a switching chip, a power amplifier chip, and a coupler. The switching chip integrates a switching unit, and the power amplifier chip integrates a power amplifier circuit. The switching unit is connected to the output path between the output terminal of the power amplifier circuit and the antenna port. The coupler includes a main line connected to the transmission path between the switching unit and the antenna port, and a coupling line coupled to the main line. The isolation port of the coupling line is grounded through a resistor and a ninth capacitor. The resistor and the ninth capacitor are both integrated on the power amplifier chip or the switching chip.

34. The radio frequency front-end module according to claim 33, characterized in that, The distance between the coupler and the switching chip is less than the distance between the coupler and the power amplifier chip.

35. The radio frequency front-end module according to claim 33, characterized in that, The coupler is positioned closer to the antenna port than the switching chip and the power amplifier chip.

36. The radio frequency front-end module according to claim 33, characterized in that, The switching unit in the switching chip is connected to the components disposed on the substrate through at least two first bonding wires. The isolation port of the coupling line disposed on the substrate is connected to the resistor and the ninth capacitor disposed on the switching chip through a second bonding wire. There is a first distance between any first bonding wire and the second bonding wire, and a second distance between any two adjacent first bonding wires. The first distance is greater than or equal to the second distance.

37. A radio frequency front-end module, characterized in that, include: The substrate, the first DC blocking unit, and the signal input port, the power amplifier chip, and the CMOS chip disposed on the substrate; the power amplifier chip integrates a power amplifier circuit, and the first DC blocking unit is connected to the input path between the signal input port and the input terminal of the power amplifier circuit; The first DC blocking unit is disposed on the CMOS chip.

38. The radio frequency front-end module according to claim 37, characterized in that, The first DC blocking unit includes a stacked capacitor.

39. The radio frequency front-end module according to claim 37, characterized in that, The CMOS chip is positioned closer to the signal input port than the power amplifier chip.

40. The radio frequency front-end module according to claim 37, characterized in that, The power amplifier circuit includes a first power amplifier unit and a second power amplifier unit, the signal input port includes a first signal input terminal and a second signal input terminal, and the first DC blocking unit includes a first DC blocking capacitor and a second DC blocking capacitor. The first DC blocking capacitor is connected between the first signal input terminal and the input terminal of the first power amplifier unit, and the second DC blocking capacitor is connected between the second signal input terminal and the input terminal of the second power amplifier unit. Both the first DC blocking capacitor and the second DC blocking capacitor are integrated on the CMOS chip.

41. An electronic device, characterized in that, The electronic device includes the radio frequency front-end module as described in any one of claims 1-40.

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