A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a programmable ultra-wideband direct radio frequency transceiving heterogeneous integrated chip, which comprises a large-scale programmable logic FPGA, two high-bandwidth radio frequency analog-to-digital converters RF-ADC1 to RF-ADC2 and two high-speed high-precision radio frequency digital-to-analog converters RF-DAC1 to RF-DAC2; the high-bandwidth radio frequency analog-to-digital converter and the high-speed high-precision radio frequency digital-to-analog converter are connected with the large-scale programmable logic FPGA; the large-scale programmable logic FPGA is used for configuring, data transmission and digital signal processing of the RF-ADC1, the RF-ADC2, the RF-DAC1 and the RF-DAC2; the high-bandwidth radio frequency analog-to-digital converter is used for directly collecting input radio frequency analog signals and converting the input radio frequency analog signals into digital signals; the high-speed high-precision radio frequency digital-to-analog converter is used for converting digital input signals and outputting radio frequency signals; the application forms a universal and standardized direct radio frequency integrated chip, and supports multi-mode, multi-frequency and multi-functional wireless communication.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip. Background Technology

[0002] Software-defined radio (SDR) technology aims to implement various wireless communication functions on a fixed hardware platform by adjusting the system software architecture and programming, enabling communication terminals to support multiple communication standards. However, traditional SDR hardware platforms are typically built using discrete components, including core RF front-end devices, FPGAs, ADCs, DACs, power amplifiers, etc. Building hardware platforms with discrete components has disadvantages such as large area, high cost, and low efficiency. With the diversification of wireless communication, the requirements for bandwidth and transmission rates are becoming increasingly demanding.

[0003] Existing integration solutions mainly integrate components in a modular manner or primarily integrate RF front-end devices. For example, patent application CN202122043263.9, entitled "A General-Purpose Core Module Based on Software Radio Technology," discloses a sequentially connected RF front-end circuit, a programmable RF transceiver chip, and a programmable system-on-a-chip; it also includes interface circuits and expansion circuits; the RF front-end circuit further includes an RF switch for signal path selection. On the one hand, the RF transceiver circuit and processor increase the integration in hardware design, reduce hardware costs, board area, and power consumption, and improve programmability; on the other hand, it achieves controllable communication link paths and link loopback self-testing. For example, the patent application CN201711177787.9, entitled "An Integrated Module for Ultra-Wideband High-Bandwidth Bidirectional Radio Frequency Transceiver," discloses a main control unit, a power supply unit, a microwave frequency synthesis unit, a radio frequency transmitting unit, a radio frequency receiving unit, a digital signal processing unit, and a radio frequency transceiver control unit. The main control unit mainly performs functions such as bus driving, data interaction, and signal processing. The power supply unit provides a highly stable, low-noise power supply. The microwave frequency synthesis unit, radio frequency transmitting unit, radio frequency receiving unit, and digital signal processing unit use microwave frequency synthesis technology, broadband frequency conversion technology, signal conditioning technology, broadband modulation and demodulation technology, and digital signal processing technology to achieve a maximum unidirectional 8×8 or bidirectional 4×4 radio frequency transceiver. The radio frequency transceiver control unit realizes radio frequency transceiver control.

[0004] The aforementioned existing technologies have all met the requirements of large-scale MIMO radio frequency multiplexing and transceiver, but they still have problems such as narrow bandwidth, low integration density, lack of programming resources, and insufficient application flexibility. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip. The chip structure includes: a large-scale programmable logic FPGA, two high-bandwidth radio frequency analog-to-digital converters (RF-ADC1~RF-ADC2), and two high-speed, high-precision radio frequency digital-to-analog converters (RF-DAC1~RF-DAC2). Both the high-bandwidth RF-ADCs and the high-speed, high-precision RF-DACs are connected to the large-scale programmable logic FPGA. The large-scale programmable logic FPGA is used for configuring RF-ADC1, RF-ADC2, RF-DAC1, and RF-DAC2, data transmission, and digital signal processing. The high-bandwidth RF-ADCs are used to directly acquire input radio frequency analog signals and convert them into digital signals. The high-speed, high-precision RF-DACs are used to convert digital input signals and output radio frequency signals.

[0006] The beneficial effects of this invention are:

[0007] This invention enables the development of direct RF heterogeneous integrated chips with 1 transmit / receive, 2 transmit / receive, or 4 transmit / receive configurations. The ADC achieves a maximum sampling rate of 3.2 GHz, an analog input bandwidth of up to 9 GHz, and a maximum DAC conversion rate of 6.4 GHz. It effectively replaces five discrete components, achieving high-density packaging through RDL redistribution and ABF substrate, reducing size by over 40% and significantly simplifying system PCB design. This invention creates a universal, standardized direct RF integrated chip that supports multi-mode, multi-frequency, and multi-functional wireless communication. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the heterogeneous integrated chip architecture of the present invention;

[0009] Figure 2 This is a schematic diagram of the heterogeneous integrated chip process structure of the present invention;

[0010] Figure 3 This is a schematic diagram of the back side of the ABF substrate of the present invention;

[0011] Figure 4 This is a schematic diagram of the ABF substrate surface of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] This invention provides a programmable ultra-wideband radio frequency (RF) direct heterogeneous integrated chip, achieving 4-receive and 4-transmit RF functions, while possessing high-performance programmable resources to implement digital signal processing algorithms. It effectively replaces multiple discrete components, reducing area and cost. This results in a general-purpose, standardized direct RF integrated chip that supports multi-mode, multi-frequency, and multi-functional wireless communication.

[0014] A programmable ultra-wideband direct RF transceiver heterogeneous integrated chip, such as Figure 1 As shown, it includes: a large-scale programmable logic FPGA, two high-bandwidth radio frequency analog-to-digital converters (RF-ADC1~RF-ADC2), and two high-speed, high-precision radio frequency digital-to-analog converters (RF-DAC1~RF-DAC2); the high-bandwidth RF-ADCs and the high-speed, high-precision RF-DACs are all connected to the large-scale programmable logic FPGA; the large-scale programmable logic FPGA is used for configuring RF-ADC1, RF-ADC2, RF-DAC1, and RF-DAC2, data transmission, and digital signal processing; the high-bandwidth RF-ADCs are used for directly acquiring input RF analog signals and converting them into digital signals; the high-speed, high-precision RF-DACs are used for converting digital input signals and outputting RF signals.

[0015] Specifically, the heterogeneous integrated architecture includes a large-scale programmable logic array (FPGA), a high-bandwidth radio frequency analog-to-digital converter (RF-ADC), and a high-speed, high-precision radio frequency digital-to-analog converter (RF-DAC). The FPGA primarily handles the configuration of the RF-ADC and RF-DAC, JESD-204B data transmission, and digital signal processing. The RF-ADC directly acquires the input RF analog signal and converts it into a digital signal, with a maximum sampling rate of 3.2 GHz. The RF-DAC converts the digital input signal and outputs an RF signal, with a maximum conversion rate of 6.4 GHz. This heterogeneous integrated chip allows for configurable transmit / receive channels, enabling direct RF signal conversion and digital signal processing functions such as 1-receive-1-transmit, 2-receive-2-transmit, or 4-receive-4-transmit.

[0016] In this embodiment, the circuit structure of the high-bandwidth radio frequency analog-to-digital converter (RF-ADC) needs to balance "high bandwidth" and "high precision," and mainly consists of four modules: a high-speed sampling module, a quantization and encoding module, and a digital post-processing module.

[0017] The high-speed sampling module is the core of the RF-ADC and adopts a "time-interleaved ADC" (TI-ADC) architecture. It arranges multiple low-speed ADCs in parallel and uses a clock distribution network to allow each ADC to sample alternately, achieving an overall sampling rate far exceeding that of a single ADC (for example, interleaving eight 1GSPS ADCs can achieve a total sampling rate of 8GSPS).

[0018] The quantization and encoding module performs "layering" and "encoding" on the sampled analog voltage values. By comparing the analog signal with a reference voltage through a comparator array, the quantization range to which it belongs is determined, and then the range is converted into the corresponding binary digital code (e.g., a 12-bit ADC can output 4096 different codes).

[0019] The digital post-processing module corrects errors during the conversion process and improves the quality of the output signal. It mainly includes a calibration unit (correcting the gain and offset errors of each sub-ADC in the TI-ADC) and a digital filtering unit (further suppressing noise). Some high-end products also integrate signal demodulation functions to directly output the baseband digital signal.

[0020] The workflow of an RF-ADC follows the logic of "high-speed sampling → quantization encoding → error correction → digital output". The key is to "directly skip down-conversion and realize the digitization of the RF signal in one step". The specific steps are as follows:

[0021] High-speed sampling (core component): The sampling module employs a time-interleaved architecture, controlling multiple sub-ADCs to work alternately via a high-speed clock signal. Assuming a total sampling rate of 8 GSPS, composed of eight 1 GSPS sub-ADCs, the clock distribution network causes each sub-ADC to sample sequentially within a time interval of "1 / 8 GSPS". Finally, the eight low-speed sampling results are concatenated to obtain an 8 GSPS high-speed sampling sequence, achieving "real-time capture" of RF signals.

[0022] Quantization and Encoding: The sampled analog voltage value is sent to the quantization module. The quantization module has a built-in set of reference voltages. The input voltage is compared with the reference voltage by a comparator to determine its corresponding quantization level (e.g., if the voltage falls in the 1000th reference interval, the corresponding quantization value is 1000). The quantization level is then converted into binary code (1000 corresponds to 12 bits, which is 001111101000 in binary).

[0023] Digital post-processing and output: The encoded digital signal first passes through a calibration unit to correct errors such as gain differences and sampling time deviations among the sub-ADCs in the time-interleaved architecture; then, it passes through a digital filter to suppress quantization noise and high-frequency interference; finally, it outputs a digital signal that meets the requirements (such as baseband I / Q signals) for use by subsequent software algorithms (such as signal demodulation and data processing).

[0024] The heterogeneous integration process solution uses RDL redistribution to first fan out package the two RF-ADCs and two RF-DACs respectively. The fan out RF-ADCs, RF-DACs and FPGA dies are then flip-mounted onto the ABF substrate, and a metal cover plate is used on top of the chip to protect and dissipate heat.

[0025] The large-scale programmable logic FPGA contains more than 600k logic cells, 80 pairs of high-speed transceivers supporting JESD-204B, and a large number of configurable resources such as DSP, RAM, and PLL.

[0026] This high-bandwidth radio frequency analog-to-digital converter (RF-ADC) features two channels, each with 14-bit resolution, a 3.2GHz sampling rate, and a 9GHz analog input bandwidth. It includes an SPI configuration interface and a JESD-204B data interface, which can be configured with 1, 2, 4, or 8 channels. It also features input signal power monitoring.

[0027] This high-speed, high-precision RF-DAC features two channels, each with 16-bit resolution and a 6GHz conversion rate. It includes an SPI configuration interface and a JESD-204B data interface, configurable for 1, 2, 4, 6, or 8 channels. It also features an NCO (Network Control Unit) for DDS (Digital-to-Digital) functionality, achieving a maximum conversion rate of 12.6GHz. The circuit's full-scale output current is adjustable.

[0028] In this embodiment, the high-speed, high-precision radio frequency digital-to-analog converter consists of five core modules: a digital input and signal processing module, a high-speed data distribution and clock synchronization module, a parallel DAC core array, an analog signal synthesis and filtering module, and a radio frequency output driving module. These modules work together to achieve a balance between high speed and high precision.

[0029] Digital Input and Signal Processing Module: Receives external digital baseband signals (such as I / Q signals) and performs preprocessing. This module includes an interpolation filter (to increase the signal sampling rate and match the rate of the subsequent DAC core), a digital predistortion unit (to compensate for DAC nonlinear distortion and improve the purity of the output signal), and a data formatting unit (to convert the input data into a parallel or serial format recognizable by the DAC core).

[0030] The high-speed data distribution and clock synchronization module evenly distributes the processed high-speed digital signal to multiple parallel DAC sub-cores and provides a high-precision clock. The core is the clock distribution network, which requires strict control of the clock phase difference between each sub-core to avoid phase distortion during signal synthesis; this is crucial for achieving "high speed."

[0031] Parallel DAC core array: Employing a "parallel architecture" or "segmented architecture" to improve overall performance, it is the core of the RF-DAC.

[0032] Parallel architecture: Multiple medium-speed DAC sub-cores are arranged in parallel. Each sub-core processes a portion of the digital signal. The output analog signal is then synthesized to obtain a high-frequency radio frequency signal, which can break through the rate limit of a single DAC.

[0033] Segmented architecture: The high-resolution digital signal is split into high-bit and low-bit segments, which are processed by "high-bit DAC" (high precision, low speed) and "low-bit DAC" (high speed, low precision) respectively, and then synthesized by analog adders, balancing high precision and high speed.

[0034] Analog signal synthesis and filtering module: This module performs phase alignment and amplitude superposition on the analog signals output from multiple DAC sub-cores to synthesize the target RF signal. It also integrates an RF low-pass filter or band-pass filter to suppress spurious signals (such as image frequencies and harmonics) generated during the synthesis process, ensuring the purity of the output signal.

[0035] RF output driver module: Amplifies the power of the synthesized RF analog signal, adjusts the output impedance to match the external RF link (such as antenna, RF amplifier), ensures effective signal transmission, and avoids signal attenuation or reflection.

[0036] The workflow of an RF-DAC follows the logic of "digital signal input → preprocessing → high-speed distribution → parallel conversion → analog synthesis → filtering and driving → RF output". Its core principle is to "skip the traditional up-conversion stage and directly generate an RF analog signal from the digital signal". The specific steps are as follows:

[0037] Step 1: Digital Signal Input and Preprocessing: External digital baseband signals (such as I / Q digital signals for 5G communication) first enter the digital processing module. An interpolation filter increases the signal sampling rate to the high rate required by the DAC core (e.g., from 1 GSPS to 10 GSPS); the digital predistortion unit compensates for the digital signal in advance based on the DAC's nonlinear characteristics (e.g., correcting amplitude-phase distortion); the data formatting unit converts the signal into parallel data, adapting it to the input format of the subsequent DAC array.

[0038] Step 2, High-speed data distribution and clock synchronization: The pre-processed high-speed digital signal is evenly distributed to multiple DAC sub-cores (e.g., 10 1GSPS sub-cores, jointly processing a 10GSPS signal) through a data distribution network. Simultaneously, a high-precision clock module generates a synchronization clock, which is transmitted to each sub-core through the clock distribution network, ensuring that the conversion actions of all sub-cores are strictly aligned in time, avoiding phase deviations during signal synthesis.

[0039] Step 3, Parallel Digital-to-Analog Conversion: Each DAC sub-core receives the allocated digital signal and synchronization clock, converting the digital signal into the corresponding analog current or voltage signal. For example, in a segmented architecture DAC sub-core, the high-order digital signal controls the high-precision current source, and the low-order digital signal controls the high-speed current source. The analog signals output by both are initially superimposed within the sub-core to obtain an analog signal that combines accuracy and speed.

[0040] Step 4: Analog Signal Synthesis and Filtering: The analog signals output from all DAC sub-cores enter the analog synthesis network. This network, through impedance matching and phase adjustment, superimposes the analog signals from multiple sub-cores to synthesize a higher-frequency, more stable RF analog signal (e.g., synthesizing a 1GSPS sub-core signal into a 10GSPS RF signal). Subsequently, an RF filter removes spurious signals generated during the synthesis process (such as harmonics and image frequencies), improving the purity of the output signal (e.g., reducing the spurious rejection ratio, SFDR).

[0041] Step 5, RF Output Drive and Transmission: The filtered RF analog signal enters the output drive module. The drive module boosts the signal power through an RF power amplifier and adjusts the output impedance (usually 50Ω) to match it with the external RF link (such as an antenna or RF front end), ultimately outputting a qualified RF analog signal for use in communication, radar, and other scenarios.

[0042] The RDL redistribution uses a 4p4m structure, the substrate employs a 12-layer stack-up structure, and the bottom uses BGA solder balls fan-out, with dimensions ≤45mm×45mm. The substrate realizes the interconnection between the FPGA and RF-ADC, and between the FPGA and RF-DAC, and connects power, clock, reference, and other signals to the output terminals.

[0043] In addition to interconnecting with RF-ADC and RF-DAC, the FPGA has 32 pairs of high-speed transceivers exposed through its pins, which can expand the off-chip RF transceiver channels.

[0044] In this embodiment, Figure 1This is a schematic diagram of a heterogeneous integrated chip architecture, which mainly includes an FPGA, an RF-ADC, and an RF-DAC. The FPGA configures the RF-ADC and RF-DAC through the SPI interface and realizes high-speed serial data transmission through the JESD-204B interface.

[0045] Figure 2 This is a schematic diagram of the heterogeneous integrated chip process structure. The two ADCs and DACs are fanned out through RDL, and then together with the FPGA die, they are flipped onto the ABF substrate. The bottom of the substrate is fanned out using BGA solder balls, and the top is protected by a metal cover plate. The substrate is also cooled by thermal adhesive through contact with the back of the die.

[0046] In one implementation, the RF-ADC employs a dual-channel 3.2GHz sampling rate, 14-bit resolution ADC die, and has a 9GHz analog input bandwidth, along with input signal power monitoring functionality. Its SPI and JESD-204B interfaces interconnect with the FPGA, including coupling capacitors for the JESD-204B signals. The JESD-204B interface can be configured with 1, 2, 4, or 8 channels. The ADC's power supply pins, clock pins, reference pins, and other configuration-related pins are led out to the output terminals.

[0047] The RF-DAC employs a dual-channel 6.4GHz sampling rate, 16-bit resolution DAC die. Its SPI and JESD-204B interfaces interconnect with the FPGA, including coupling capacitors for the JESD-204B signal. The JESD-204B interface can be configured with 1, 2, 4, 6, or 8 channels. It features an NCO, enabling DDS functionality with a maximum conversion rate of 12.6GHz. The circuit's full-scale output current is adjustable. The DAC's power supply pins, clock pins, reference pins, and other configuration pins are routed to the output terminals.

[0048] The FPGA is a high-performance FPGA containing over 600k logic cells, 80 pairs of high-speed transceivers supporting JESD-204B, and a large amount of configurable resources such as DSP, RAM, and PLL. 32 pairs of high-speed transceivers interconnect with high-speed data interfaces for ADCs and DACs, and 32 spare pairs of high-speed transceivers are also exposed for expansion.

[0049] like Figure 3 and Figure 4 As shown, the ABF substrate adopts a 12-layer stacked structure, with a CORE layer in the middle and 1936 solder balls for lead-out on the back.

[0050] Surface mount devices and inverted soldering are performed on the surface of the ABF substrate.

[0051] Simulation design using an ABF substrate showed crosstalk between JESD-204B signals < -30dB, insertion loss < 0.5dB, and return loss > 20dB. The delay difference within the JESD-204B signal differential pair was < 0.5ps.

[0052] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip, characterized in that, include: The system comprises a large-scale programmable logic FPGA, two high-bandwidth radio frequency analog-to-digital converters (RF-ADC1~RF-ADC2), and two high-speed, high-precision radio frequency digital-to-analog converters (RF-DAC1~RF-DAC2). The high-bandwidth RF-ADCs and the high-speed, high-precision RF-DACs are all connected to the large-scale programmable logic FPGA. The large-scale programmable logic FPGA is used for configuring, transmitting data, and processing digital signals from RF-ADC1, RF-ADC2, RF-DAC1, and RF-DAC2. The high-bandwidth RF-ADCs are used to directly acquire input RF analog signals and convert them into digital signals. The high-speed, high-precision RF-DACs are used to convert digital input signals and output RF signals.

2. The programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 1, characterized in that, Two RF-ADCs and two RF-DACs are fan-out packaged using 2.3D packaging technology. The high-bandwidth RF analog-to-digital converter, the high-speed and high-precision RF digital-to-analog converter, and the FPGA are then soldered onto the ABF substrate using a flip-chip soldering method. The integrated sealing is achieved through a cover plate.

3. The programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 2, characterized in that, The cover is a metal cover used to dissipate heat from the chip.

4. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 2, characterized in that, In the fan-out packaging, the RDL-First process is used to fabricate a fine RDL adapter board on the ABF substrate. The RDL adapter board adopts a 4p4m structure with a minimum line width and line spacing of ≤10μm. The KGD chip is mounted on the RDL adapter board, and the pad distribution of the KGD chip is reconstructed.

5. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 4, characterized in that, The ABF substrate adopts a 12-layer stacked structure, with a substrate size of ≤45mm×45mm, and uses BGA solder balls fan-out at the bottom.

6. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 1, characterized in that, A large-scale programmable logic FPGA contains at least 600k logic cells, 80 pairs of high-speed transceivers supporting JESD-204B, and configurable resources such as DSP, RAM, and PLL.

7. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 1, characterized in that, The high-bandwidth RF analog-to-digital converter includes two channels, each with 14-bit resolution and 9 GHz analog input bandwidth. It features an SPI configuration interface and a JESD-204B data interface, which can be configured with 1, 2, 4, or 8 channels.

8. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 7, characterized in that, The high-bandwidth RF analog-to-digital converter has a maximum sampling rate of 3.2 GHz for RF analog signals.

9. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 1, characterized in that, The high-speed, high-precision RF digital-to-analog converter has two channels, each with 16-bit resolution, and features an SPI configuration interface and a JESD-204B data interface. The JESD-204B interface can be configured with channels 1, 2, 4, 6, or 8.

10. A programmable ultra-wideband direct radio frequency transceiver heterogeneous integrated chip according to claim 9, characterized in that, The high-speed, high-precision radio frequency digital-to-analog converter has a maximum conversion rate of 6.4 GHz for digital input signals.

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