Communication circuit between bmc and cpu and server

Abstract

The application discloses a communication circuit between a BMC and a CPU and a server, and relates to the technical field, which comprises a baseboard management controller (BMC), a CPU and a communication module; the BMC is electrically connected with the CPU through an LPC bus; the communication module is electrically connected with the BMC and the CPU respectively; the working mode of the communication module is full-duplex mode, so that the BMC can access the CPU. According to the application, the communication module is arranged between the BMC and the CPU, so that the BMC can access the CPU through the communication module, and when a system fault occurs, the BMC can actively access the CPU through the communication module to acquire system logs and hardware state information, so that the fault problem can be quickly located, and the efficiency of quick location and solution of the problem is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a communication circuit between a BMC and a CPU, and a server. Background Technology

[0002] In modern server design, the BMC (Baseboard Management Controller) is used to enable remote management and monitoring of the server. The CPU system typically provides external network ports via a PCIe (Peripheral Component Interconnect Express) network card, supporting operations such as software installation and upgrades, and data processing.

[0003] In traditional designs, the BMC connects to the RJ45 network port via an onboard network card (such as an I210 network card). Communication between the BMC and the CPU occurs via the LPC (Low Pin Count) bus, typically with the BIOS or PCH (Platform Controller Hub) acting as the master device and the BMC passively responding as a slave device. However, as a slave device, the BMC can only respond to command requests from the master device (such as the BIOS or PCH) and lacks the ability to actively access system data. When a system failure occurs, the BMC cannot proactively obtain system logs and hardware status information, reducing the efficiency of quickly locating and resolving problems.

[0004] Therefore, how to enable BMC to actively access the CPU is a problem that urgently needs to be solved. Utility Model Content

[0005] The main purpose of this application is to provide a communication circuit and server between the BMC and the CPU, aiming to solve the technical problem of how to enable the BMC to actively access the CPU.

[0006] To achieve the above objectives, this application provides a communication circuit between a BMC and a CPU, comprising: a baseboard management controller (BMC), a CPU, and a communication module;

[0007] The BMC is electrically connected to the CPU via the LPC bus;

[0008] The communication module is electrically connected to both the BMC and the CPU; the communication module operates in full-duplex mode, enabling the BMC to access the CPU.

[0009] Furthermore, the communication module includes a data conversion module and a PHY chip, wherein the PHY chip operates in full-duplex mode;

[0010] The data conversion module is electrically connected to the CPU via a PCIe interface;

[0011] The PHY chip is electrically connected to the BMC via the MDIO interface and the RGMII interface, respectively.

[0012] Furthermore, the data conversion module is electrically connected to the PHY chip via the RGMII interface.

[0013] Furthermore, the data conversion module is a PCIe to RGMII module, used to convert the format between the data corresponding to the PCIe interface and the data corresponding to the RGMII interface.

[0014] Furthermore, the PHY chip comprises multiple chips.

[0015] Furthermore, the MDIO bus includes MDC signal lines and MDIO signal lines;

[0016] The BMC is electrically connected to the MDC signal line and the MDIO signal line respectively through the MDIO interface;

[0017] Each of the PHY chips is electrically connected to the MDC signal line and the MDIO signal line respectively through the MDIO interface.

[0018] Furthermore, the BMC configures the parameters of the PHY chip through the MDIO interface, including network speed, full-duplex mode, and auto-negotiation.

[0019] Furthermore, after the parameters of the PHY chip are configured, the BMC accesses the CPU through the data conversion module and the PHY chip.

[0020] Furthermore, the CPU is electrically connected to the PCIe network card through the PCIe interface, and the BMC is electrically connected to the onboard network card through the PCIe interface.

[0021] In addition, to achieve the above objectives, this application also provides a server, which includes the aforementioned communication circuit between the BMC and the CPU.

[0022] This application establishes a communication module between the BMC and the CPU, enabling the BMC to access the CPU through the communication module. Consequently, when a system failure occurs, the BMC can proactively access the CPU through the communication module to obtain system logs and hardware status information, facilitating rapid fault location and improving the efficiency of problem identification and resolution.

[0023] After the BMC and CPU systems are started, the BMC can efficiently access the CPU system through the internally allocated local area network. This local area network is a gigabit network, which can provide high bandwidth transmission capabilities to meet the needs of large file transfer and efficient management. Furthermore, by adopting PCIe interface, RGMII interface and MDIO interface, the data transmission bandwidth between the BMC and the CPU is greatly improved, which can support larger capacity file transfer and efficient data interaction, reduce data transmission latency and improve data transmission efficiency.

[0024] The BMC configures the PHY chip's speed, duplex mode, and auto-negotiation parameters via the MDIO channel to ensure stable network connectivity. After system startup, the BMC can perform high-speed data interaction with the CPU system through the internal LAN. This gigabit LAN supports large file transfers and provides highly readable and easy-to-operate data, greatly improving system management efficiency. Compared to traditional LPC communication, the system data acquired by the BMC through this LAN is file-level data, which is easy to read and understand. Development and maintenance personnel can directly read the file content without requiring complex data parsing by the BMC, significantly reducing the BMC's workload and improving data transmission efficiency.

[0025] When a CPU system malfunctions, the BMC can quickly read system logs via its internal gigabit LAN for real-time fault analysis and rapid problem localization, thereby improving diagnostic efficiency. The BMC can also monitor and obtain real-time status information for CPU system hardware components (such as CPU, memory, hard drive, network card, RAID card, etc.), simplifying server operation and maintenance management without requiring additional agent program development, thus saving development costs.

[0026] Through the local area network (LAN), the BMC can quickly transfer business software to the CPU system and perform operations such as installation, deployment, and configuration. This simplifies the software installation and deployment process, saves development and maintenance time, and improves system management efficiency. When the network interface card (NIC) in the CPU system malfunctions, the BMC can directly access and analyze the NIC's anomaly information remotely via this LAN. This solves the problem of not being able to access the CPU system through a physical channel during network failures, enhancing system stability and maintenance capabilities. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the module structure provided in Embodiment 1 of the communication circuit between the BMC and the CPU in this application;

[0030] Figure 2 This is a schematic diagram of the module structure provided in Embodiment 2 of the communication circuit between the BMC and the CPU in this application.

[0031] Explanation of icon numbers:

[0032] 110 CPU 120 BMC 130 Data conversion module 140 PHY chip 150 PCIe network card 160 Onboard network card

[0033] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0034] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0035] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0036] The main solution of this application is: the communication circuit between the BMC and the CPU includes: a baseboard management controller (BMC), a CPU, and a communication module; the BMC is electrically connected to the CPU via an LPC bus; the communication module is electrically connected to both the BMC and the CPU; the communication module operates in full-duplex mode, so that the BMC can access the CPU.

[0037] In modern server designs, the BMC (Baseboard Management Controller) is used for remote management and monitoring of the server. The BMC connects to an RJ45 network port via an onboard network interface card (such as an I210 network card), providing access to management interfaces or dedicated interfaces for server management and control. Through the BMC's network interface, users can perform operations such as health status monitoring, firmware upgrades / downgrades, asset information retrieval, alarm logging, and audit logs. The CPU system typically provides external network ports via a PCIe (Peripheral Component Interconnect Express) network card, supporting software installation and upgrades, data processing, and other operations.

[0038] In traditional designs, the BMC connects to the RJ45 network port via an onboard network card (such as the I210 network card). The BMC communicates with the CPU via the LPC (Low Pin Count) bus. Typically, the BIOS (Basic Input Output System) or PCH (Platform Controller Hub) acts as the master device, while the BMC passively responds as a slave device.

[0039] However, as a slave device, the BMC can only respond to command requests from the master device (such as the BIOS or PCH) and lacks the ability to actively access system data. When a system failure occurs, the BMC cannot proactively obtain system logs and hardware status information, reducing the efficiency of rapid problem localization and resolution. Furthermore, when system errors occur, the BMC cannot directly access system data or logs, requiring the development of additional agent programs to send data to the BMC, increasing the complexity of development and maintenance.

[0040] The LPC bus has a low data transfer rate, small data volume per transfer, and the data is usually in binary format, requiring further parsing by the BMC, increasing its workload and reducing overall efficiency. Communication configuration via the LPC interface is typically complex, requiring frequent register operations, and the limited data volume and long transfer time per transfer reduce system response speed and management efficiency. Furthermore, the BMC cannot access real-time status information of network cards or other hardware devices within the system without a physical channel, making fault diagnosis and problem localization difficult, especially in the event of network card malfunctions.

[0041] Therefore, how to enable BMC to actively access the CPU is a problem that urgently needs to be solved.

[0042] This application establishes a communication module between the BMC and the CPU, enabling the BMC to access the CPU through the communication module. Consequently, when a system failure occurs, the BMC can proactively access the CPU through the communication module to obtain system logs and hardware status information, facilitating rapid fault location and improving the efficiency of problem identification and resolution.

[0043] This invention proposes a communication circuit between the BMC and the CPU.

[0044] Reference Figures 1 to 2 , Figure 1 This is a schematic diagram of the module structure provided in Embodiment 1 of the communication circuit between the BMC and the CPU in this application; Figure 2 This is a schematic diagram of the module structure provided in Embodiment 2 of the communication circuit between the BMC and the CPU in this application.

[0045] In the embodiments of this utility model, such as Figure 1 As shown, the communication circuit between the BMC and the CPU includes the baseboard management controller BMC120, the CPU110, and the communication module.

[0046] BMC120 is electrically connected to CPU110 via LPC (Low Pin Count) bus;

[0047] The communication module is electrically connected to both the BMC120 and the CPU110; the communication module operates in full-duplex mode so that the BMC120 can access the CPU110.

[0048] In one feasible implementation, such as Figure 1 As shown, the communication module includes a data conversion module 130 and a PHY chip 140, wherein the PHY chip 140 operates in full-duplex mode.

[0049] The data conversion module 130 is electrically connected to the CPU 110 via a PCIe interface;

[0050] The PHY chip 140 is electrically connected to the BMC 120 via the MDIO interface and the RGMII interface, respectively.

[0051] In this embodiment, the communication module includes a data conversion module 130 and a PHY (Physical Layer) chip. The data conversion module 130 is a PCIe (peripheral component interconnect express) to RGMII (Reduced Gigabit Media Independent Interface) module. When the PHY chip 140 is working normally, the PHY chip 140 operates in full-duplex mode, which can be set to full-duplex mode by the BMC 120.

[0052] The data conversion module 130 is electrically connected to the CPU 110 via a PCIe interface, enabling communication between the data conversion module 130 and the CPU 110. For example, when the BMC 120 accesses the CPU 110, the BMC 120 transmits the access request to the CPU 110 through the PHY chip 140 and the data conversion module 130. The CPU 110 then transmits the data corresponding to the access request to the BMC 120 through the data conversion module 130 and the PHY chip 140. This allows the BMC 120 to actively access the CPU 110 through the data conversion module 130 and the PHY chip 140 when a system failure occurs, in order to obtain system logs and hardware status information. This facilitates the analysis of system failures based on the system logs and hardware status information, enabling rapid fault location and improving the efficiency of problem identification and resolution.

[0053] In this embodiment, both the PHY chip 140 and the BMC 120 are provided with corresponding RGMII interfaces and MDIO (Management Data Input / Output) interfaces. The RGMII interface of the BMC 120 is electrically connected to the RGMII interface of the PHY chip 140, and the BMC 120 is electrically connected to the MDIO interface of the PHY chip 140 through its MDIO interface. Preferably, the communication circuit between the BMC 120 and the CPU 110 further includes an MDIO bus, with the MDIO interface of the BMC 120 connected to the MDIO bus, and the MDIO interface of the PHY chip 140 also connected to the MDIO bus.

[0054] In one feasible implementation, such as Figure 1 As shown, the data conversion module 130 is electrically connected to the PHY chip 140 via the RGMII interface.

[0055] In this embodiment, the data conversion module 130 is electrically connected to the PHY chip 140 through the RGMII interface. Specifically, the RGMII interface of the data conversion module 130 is electrically connected to the RGMII interface of the PHY chip 140.

[0056] Furthermore, such as Figure 1 As shown, the data conversion module 130 is a PCIe to RGMII module, used to convert the format between the data corresponding to the PCIe interface and the data corresponding to the RGMII interface.

[0057] In this embodiment, the data conversion module 130 is a PCIe to RGMII module. This PCIe to RGMII module is used to convert the format between the data corresponding to the PCIe interface and the data corresponding to the RGMII interface. For example, when the BMC120 accesses the CPU110, the PCIe to RGMII module converts the data corresponding to the RGMII interface into the data corresponding to the PCIe interface, and sends the converted data to the CPU110 through the PCIe interface. When the CPU110 responds with the data corresponding to the access request, the PCIe to RGMII module converts the data corresponding to the PCIe interface into the data corresponding to the RGMII interface, and sends the converted data to the BMC120 through the RGMII interface.

[0058] In one feasible implementation, such as Figure 1 As shown, CPU110 is electrically connected to PCIe network card 150 via PCIe interface, and BMC120 is electrically connected to onboard network card 160 via PCIe interface.

[0059] In this embodiment, the CPU 110 is electrically connected to the PCIe network card 150 via a PCIe interface. The PCIe network card 150 can be a PCIe 4.0 PCIe network card 150, allowing the CPU 110 to access network port 1 through the PCIe network card 150. The BMC 120 is electrically connected to the onboard network card 160 via a PCIe interface. The onboard network card 160 can be an I210 network card, allowing the BMC 120 to access network port 2 (e.g., an RJ45 network port) through the onboard network card 160.

[0060] In one feasible implementation, the BMC120 configures the parameters of the PHY chip 140 through the MDIO interface, including network speed, full-duplex mode, and auto-negotiation.

[0061] In this embodiment, after the communication circuit between BMC120 and CPU110 is powered on, BMC120 configures the parameters of PHY chip 140 through the MDIO interface. The configured parameters include network speed, full-duplex mode, and auto-negotiation. Auto-negotiation refers to the function of network devices automatically adjusting connection speed and duplex mode according to the capabilities of the peer. Auto-negotiation is implemented by PHY chip 140 at the physical layer. When both devices support auto-negotiation, information is exchanged through FLP fast connection pulse to determine the optimal connection configuration. Specifically, the configuration process of the PHY chip 140 by the BMC120 is as follows: When the BMC120 is powered on, the driver for the MDIO bus is initialized to initialize the MDIO bus. The MDIO bus is used to determine whether the PHY chip 140 is present. If the PHY chip 140 is present, the BMC120 configures the PHY chip 140. When the PHY chip 140 is configured, it is reset, the BMSR (Basic Mode Status Register) is configured, auto-negotiation is started, the speed is gigabit, and full-duplex mode is enabled. The BMSR is read to determine whether auto-negotiation is complete and waits for it to complete. The BMSR is read to determine whether the link establishment is complete. The LED display mode of the communication circuit between the BMC120 and the CPU110 indicates the network connection status. Error detection is enabled and network status monitoring begins. The PHY chip 140 is enabled and configured with a specified IP address in the same network segment as the CPU110. After that, communication between the BMC120 and the CPU110 can be carried out, enabling the BMC120 to actively access the CPU110.

[0062] In one feasible implementation, after the parameters of the PHY chip 140 are configured, the BMC 120 accesses the CPU 110 through the data conversion module 130 and the PHY chip 140.

[0063] In this embodiment, after the parameters of the PHY chip 140 are configured, the BMC 120 can access the CPU 110 through the data conversion module 130 and the PHY chip 140. For example, when the BMC 120 accesses the CPU 110, the BMC 120 sends an access request to the PHY chip 140 through the RGMII interface. The PHY chip 140 then sends the access request to the PCIe-to-RGMII module through the RGMII interface. The PCIe-to-RGMII module converts the access request received by the RGMII interface into an access request corresponding to the PCIe interface, and sends the PCIe interface-corresponding access request to the CPU 110 through the PCIe interface. The CPU 110 then uses the PCIe interface to transfer system logs and hardware... Access data, such as device status information, is sent to the PCIe to RGMII converter module. The PCIe to RGMII converter module converts the access data into access data corresponding to the RGMII interface, and then converts the access data corresponding to the RGMII interface into the PHY chip 140. The PHY chip 140 transmits the access data corresponding to the RGMII interface to the BMC 120 through the RGMII interface. Thus, when a system failure occurs, the BMC 120 can actively access the CPU 110 through the data conversion module 130 and the PHY chip 140 to obtain system logs and hardware status information. This allows for analysis of system failures based on the system logs and hardware status information, enabling rapid fault location and improving the efficiency of problem location and resolution.

[0064] In one feasible implementation, such as Figure 2 As shown, the PHY chip 140 includes multiple chips, and the MDIO bus includes MDC signal lines and MDIO signal lines;

[0065] The BMC120 is electrically connected to the MDC signal line and the MDIO signal line respectively via the MDIO interface;

[0066] Each PHY chip 140 is electrically connected to the MDC signal line and the MDIO signal line respectively through the MDIO interface.

[0067] In the embodiments of this application, such as Figure 2 As shown, the PHY chip 140 includes multiple chips, and the MDIO bus includes MDC signal lines and MDIO signal lines. The signals of the MDIO bus include MDC and MDIO. The BMC 120 is electrically connected to the MDC signal lines and MDIO signal lines respectively through the MDIO interface; each PHY chip 140 is electrically connected to the MDC signal lines and MDIO signal lines respectively through the MDIO interface.

[0068] MDC is the clock signal for management data, output by the manager (such as a processor, MAC, or BMC120) to the PHY chip 140, with a maximum speed exceeding 5MHz. MDIO is a bidirectional input / output interface for management data, where the data is synchronized with the MDC clock. The MDIO bus supports multi-device mode, meaning that up to 32 PHY chip 140 MDIO interfaces can be connected to a single MDIO bus. Each MDIO interface can connect to one PHY chip 140. Each PHY chip 140 has a 5-bit hardware address, consisting of a fixed part and a variable part. The variable part can be set via physical pull-up or grounding. During data transmission, the device address field in the data transmits different PHY device addresses to identify the corresponding PHY chip 140. If multiple PHY chips 140 are connected to the same MDIO bus simultaneously, different PHY device addresses can be set to distinguish between them. Each PHY chip 140 can have up to 32 registers for reading and writing. These 32 registers include the first 16 standard function registers defined by the IEEE 802.3 specification and the subsequent 16 custom function registers corresponding to the PHY chip 140. The first 16 standard function registers of all PHY chips 140 have the same function definition, while the subsequent 16 function registers can be customized according to actual needs.

[0069] The BMC120 is electrically connected to both the MDC and MDIO signal lines via MDIO interfaces, and each PHY chip 140 is electrically connected to both the MDC and MDIO signal lines via MDIO interfaces. Specifically, the BMC120 is electrically connected to the MDC signal line via one MDIO interface and to the MDIO signal line via another MDIO interface. For each PHY chip 140, the PHY chip 140 is electrically connected to the MDC signal line via one MDIO interface and to the MDIO signal line via another MDIO interface.

[0070] This application sets up a communication module between BMC120 and CPU110, enabling BMC120 to access CPU110 through the communication module. In the event of a system failure, BMC120 can actively access CPU110 through the communication module to obtain system logs and hardware status information, thereby facilitating rapid fault location and improving the efficiency of rapid problem location and resolution.

[0071] After the BMC120 and CPU110 systems boot up, the BMC120 can efficiently access the CPU110 system through its internally allocated local area network (LAN). This LAN is a gigabit network, providing high-bandwidth transmission capabilities to meet the needs of large file transfers and efficient management. Furthermore, by adopting PCIe, RGMII, and MDIO interfaces, the data transfer bandwidth between the BMC120 and CPU110 is significantly increased, enabling larger-capacity file transfers and efficient data interaction, reducing data transfer latency, and improving data transfer efficiency.

[0072] The BMC120 configures the speed, duplex mode, and auto-negotiation parameters of the PHY chip 140 via the MDIO channel to ensure stable network connectivity. After system startup, the BMC120 can perform high-speed data interaction with the CPU110 system through the internal LAN. This gigabit LAN supports large file transfers and provides highly readable and easy-to-operate data, greatly improving system management efficiency. Compared to traditional LPC communication, the system data acquired by the BMC120 through this LAN is file-level data, which is easy to read and understand. Development and maintenance personnel can directly read the file content without the need for complex data parsing by the BMC120, greatly reducing the burden on the BMC120 and improving data transmission efficiency.

[0073] When the CPU110 system malfunctions, the BMC120 can quickly read system logs via its internal gigabit LAN for real-time fault analysis and rapid problem localization, thereby improving diagnostic efficiency. The BMC120 can also monitor and obtain real-time status information for the CPU110 system's hardware (such as the CPU110, memory, hard drive, network card, RAID card, etc.), simplifying server operation and maintenance management without requiring additional agent program development, thus saving development costs.

[0074] Through the local area network (LAN), the BMC120 can quickly transfer business software to the CPU110 system and perform operations such as installation, deployment, and configuration. This simplifies the software installation and deployment process, saves development and maintenance time, and improves system management efficiency. When the network interface card (NIC) in the CPU110 system malfunctions, the BMC120 can directly access and analyze the NIC's anomaly information remotely via this LAN. This solves the problem of not being able to access the CPU110 system through a physical channel during network failures, enhancing system stability and maintenance capabilities.

[0075] This utility model also proposes a server, which includes a communication circuit between the BMC and the CPU. The specific structure of the communication circuit between the BMC and the CPU is as described in the above embodiments. Since this server adopts all the technical solutions of all the above embodiments, it also has all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0076] It should be noted that the technical solutions of the various embodiments of this utility model can be combined with each other, but only if they are feasible to be implemented by those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0077] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural transformations made based on the contents of the present utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present utility model.

Claims

1. A communication circuit between a BMC and a CPU, characterized in that, include: Baseboard management controller (BMC), CPU, and communication module; The BMC is electrically connected to the CPU via the LPC bus; The communication module is electrically connected to both the BMC and the CPU; the communication module operates in full-duplex mode, enabling the BMC to access the CPU.

2. The communication circuit between the BMC and the CPU as described in claim 1, characterized in that, The communication module includes a data conversion module and a PHY chip, wherein the PHY chip operates in full-duplex mode. The data conversion module is electrically connected to the CPU via a PCIe interface; The PHY chip is electrically connected to the BMC via the MDIO interface and the RGMII interface, respectively.

3. The communication circuit between the BMC and the CPU as described in claim 2, characterized in that, The data conversion module is electrically connected to the PHY chip via the RGMII interface.

4. The communication circuit between the BMC and the CPU as described in claim 3, characterized in that, The data conversion module is a PCIe to RGMII module, used to convert the format of data corresponding to the PCIe interface and the data corresponding to the RGMII interface.

5. The communication circuit between the BMC and the CPU as described in claim 3, characterized in that, The PHY chip comprises multiple chips.

6. The communication circuit between the BMC and the CPU as described in claim 5, characterized in that, The MDIO bus includes MDC signal lines and MDIO signal lines; The BMC is electrically connected to the MDC signal line and the MDIO signal line respectively through the MDIO interface; Each of the PHY chips is electrically connected to the MDC signal line and the MDIO signal line respectively through the MDIO interface.

7. The communication circuit between the BMC and the CPU as described in claim 3, characterized in that, The BMC configures the parameters of the PHY chip through the MDIO interface. The configured parameters include network speed, full-duplex mode, and auto-negotiation.

8. The communication circuit between the BMC and the CPU as described in claim 7, characterized in that, After the parameters of the PHY chip are configured, the BMC accesses the CPU through the data conversion module and the PHY chip.

9. The communication circuit between the BMC and the CPU as described in any one of claims 1 to 8, characterized in that, The CPU is electrically connected to the PCIe network card through the PCIe interface, and the BMC is electrically connected to the onboard network card through the PCIe interface.

10. A server, characterized in that, The server includes a communication circuit between the BMC and the CPU as described in any one of claims 1 to 9.

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