A communication circuit and an electronic device

Abstract

The utility model discloses a kind of communication circuit and electronic equipment, comprising: when communication circuit is in receiving mode, controller multiplexes as GPIO port to TX pin, and through GPIO port control control circuit switches to first state, after switching success, controller is converted to UART port to TX pin, and through TX pin sends data to communication chip;When communication circuit is in sending mode, controller multiplexes as GPIO port to RX pin, and through GPIO port control control circuit switches to second state, after switching success, controller is converted to UART port to RX pin, and through RX pin receives the data sent by communication chip.The technical scheme, by increasing control circuit in communication circuit, by controlling the control circuit, meet the control requirement of enabling pin when communicating, improve communication efficiency.

Description

Technical Field

[0001] This utility model belongs to the field of circuit technology, and in particular relates to a communication circuit and electronic equipment. Background Technology

[0002] In existing RS-485 communication circuits, the operating states are divided into idle state, message sending state, and receive state. When the RS-485 is in message sending state, TXD sends a series of square waves, and the enable pin of U3 (the RS-485 communication IC) changes with the TXD signal. When TXD is low, pins DE are enabled, and TXD transmits data. However, this circuit has drawbacks. Because when TXD is low, after a transistor conduction delay and a 5V pull-up delay, the U3 enable pin is not high. If the external device has a high communication baud rate, sending erroneous messages can cause communication failures. Therefore, this circuit is only suitable for low baud rate scenarios. Furthermore, when the CPU has limited available I / O ports in the RS-485 communication circuit, additional I / O ports are needed to control the IC enable, resulting in low control efficiency. Utility Model Content

[0003] This utility model provides a solution to address the technical problem in related technologies where traditional communication circuits require additional I / O ports to control IC enable, resulting in low control efficiency.

[0004] In a first aspect, this utility model provides a communication circuit, the communication circuit comprising: a communication chip, a controller, and a control circuit connected to a bus; The RO pin of the communication chip is connected to the RX pin of the controller, the DI pin of the communication chip is connected to the TX pin of the controller, the / RE pin and DE pin of the control circuit are respectively connected to the / RE pin and DE pin of the communication chip, and the RX pin and TX pin of the control circuit are respectively connected to the RX pin and TX pin of the controller. When the communication circuit is in receive mode, the controller multiplexes the TX pin as a GPIO port and controls the control circuit to switch to the first state through the GPIO port. After the switch is successful, the controller converts the TX pin to a UART port and sends data to the communication chip through the TX pin. When the communication circuit is in transmit mode, the controller multiplexes the RX pin as a GPIO port and controls the control circuit to switch to the second state through the GPIO port. After the switch is successful, the controller converts the RX pin to a UART port and receives the data sent by the communication chip through the RX pin.

[0005] Secondly, the present invention provides an electronic device including any of the communication circuits described in the first aspect or any possible implementation of the first aspect.

[0006] The technical solution provided by this utility model includes a communication circuit comprising: a communication chip, a controller, and a control circuit connected to a bus; the RO pin of the communication chip is connected to the RX pin of the controller, the DI pin of the communication chip is connected to the TX pin of the controller, the / RE pin and DE pin of the control circuit are respectively connected to the / RE pin and DE pin of the communication chip, and the RX pin and TX pin of the control circuit are respectively connected to the RX pin and TX pin of the controller; when the communication circuit is in receive mode, the controller multiplexes the TX pin as a GPIO port and controls the control circuit to switch to a first state through the GPIO port. After successful switching, the controller converts the TX pin to a UART port and sends data to the communication chip through the TX pin; when the communication circuit is in transmit mode, the controller multiplexes the RX pin as a GPIO port and controls the control circuit to switch to a second state through the GPIO port. After successful switching, the controller converts the RX pin to a UART port and receives data sent by the communication chip through the RX pin. This technical solution adds a control circuit to the communication circuit. By controlling this control circuit, the pins on the communication chip can be enabled. This solves the problem of meeting the control requirements of the enable pins during communication when the controller lacks I / O port resources, improves communication efficiency, and can also meet the communication requirements of different baud rates. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this utility model or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a first communication circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a second communication circuit provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a third communication circuit provided in an embodiment of this utility model; Figure 4 A schematic diagram of the structure of a fourth communication circuit provided in an embodiment of this utility model; Figure 5 This is a schematic diagram of a control circuit provided in one embodiment of the present invention. Detailed Implementation

[0008] The embodiments of this utility model are described in detail below, with examples of the embodiments shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0009] The terms "first" and "second," etc., used in the specification, claims, and drawings of this utility model embodiment are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0010] In existing RS-485 communication circuits, the operating states are divided into idle state, message sending state, and receive state. When the RS-485 is in message sending state, TXD sends a series of square waves, and the enable pin of U3 (the RS-485 communication IC) changes with the TXD signal. When TXD is low, pins DE are enabled, and TXD transmits data. This circuit has drawbacks because when TXD is low, there is a 5V pull-up delay after the transistor conduction delay before the U3 enable pin goes high. If the external device has a high baud rate, sending erroneous messages can cause communication failures. Therefore, this circuit is only suitable for low baud rate scenarios. Furthermore, when the CPU has limited available I / O ports in the RS-485 communication circuit, additional I / O ports are needed to control the IC enable, resulting in low control efficiency.

[0011] The technical solution of this utility model and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this utility model will now be described with reference to the accompanying drawings.

[0012] Figure 1 This is a schematic diagram of a communication circuit provided for an exemplary embodiment of the present invention. The communication circuit includes: a communication chip 13 connected to a bus, a controller 11, and a control circuit 12.

[0013] The RO pin of the communication chip 13 is connected to the RX pin of the controller 11, the DI pin of the communication chip 13 is connected to the TX pin of the controller 11, the / RE pin and DE pin of the control circuit 12 are respectively connected to the / RE pin and DE pin of the communication chip 13, and the RX pin and TX pin of the control circuit 12 are respectively connected to the RX pin and TX pin of the controller 11.

[0014] Specifically, the communication circuit can be a 485 communication circuit.

[0015] In an embodiment of this utility model, when the communication circuit is in receive mode, the controller multiplexes the TX pin as a GPIO port and controls the control circuit to switch to the first state through the GPIO port. After the switch is successful, the controller converts the TX pin to a UART port and sends data to the communication chip through the TX pin.

[0016] The first state refers to the second switch and the first switch in the control circuit being turned on, and the fourth switch and the third switch being turned off.

[0017] Specifically, when the communication circuit is in receive mode, the controller 11 multiplexes the TX pin as a GPIO port and controls the second switch and the first switch in the control circuit 12 to be turned on, and the fourth switch and the third switch to be turned off through the GPIO port. After the DE pin of the communication chip 13 is enabled, the controller 11 converts the TX pin to a UART port and sends data to the communication chip 13 through the TX pin.

[0018] Furthermore, combined Figure 1 , Figure 3 as well as Figure 5 As shown, when the communication circuit is in receive mode, the controller 11 has not yet sent data through the TX pin. At this time, the controller 11 multiplexes the TX pin as a GPIO port and sends a pulse waveform through the GPIO port, causing the second switch Q2 to turn on. Because the second switch Q2 is on, it pulls the gate voltage of the first switch Q1 to 0V, thus turning on the first switch Q1. After the first switch Q1 is on, the gate of the second switch Q2 is connected to the first power supply CC1, so the second switch Q2 is always on, while the fourth switch Q4 is always off. In this case, the / RE pin and the DE pin are always at a high level, so the DE pin is enabled. Finally, the controller 11 converts the TX pin to a UART port and sends data to the communication chip 13 through the TX pin.

[0019] In an embodiment of this utility model, when the communication circuit is in transmit mode, the controller multiplexes the RX pin as a GPIO port and controls the control circuit to switch to the second state through the GPIO port. After the switch is successful, the controller converts the RX pin to a UART port and receives the data sent by the communication chip through the RX pin.

[0020] The second state refers to the second switch and the first switch being off in the control circuit, and the fourth switch and the third switch being on.

[0021] Specifically, when the communication circuit is in transmit mode, the controller 11 multiplexes the RX pin as a GPIO port and controls the second switch and the first switch in the control circuit 12 to be turned off and the fourth switch and the third switch to be turned on through the GPIO port. After the / RE pin of the communication chip 13 is enabled, the controller 11 converts the RX pin to a UART port and receives the data sent by the communication chip 13 through the RX pin.

[0022] Furthermore, combined Figure 1 , Figure 3 as well as Figure 5 As shown, when the communication circuit is in transmit mode, the controller 11 has not yet received data sent by the communication chip 13 through the RX pin. The controller 11 multiplexes the RX pin as a GPIO port and sends a pulse waveform through the GPIO port, thereby causing the AND gate U2 to output a high level, resulting in the third switch Q3 being turned on. Because the third switch Q3 is turned on, it pulls the gate voltage of the second switch Q2 to 0V, so the second switch Q2 is not turned on. The gate voltage of the first switch Q1 is VCC1, so the first switch Q1 is not turned on. Because the gate voltage of the fourth switch Q4 is the voltage divider of the seventh resistor R7 and the eighth resistor R8, the fourth switch Q4 is turned on. At this time, the / RE pin and the DE pin are at a low level. After the / RE pin on the AND gate U2 is enabled, the controller 11 converts the RX pin to a UART port and receives data sent by the communication chip 13 through the RX pin.

[0023] In an embodiment of this utility model, when the communication circuit is in idle mode, the / RE pin and DE pin of the communication chip 13 are set to low level, the first switch, the second switch, the third switch in the control circuit 12 are turned off, and the fourth switch is turned on. The RX pin and TX pin of the controller 11 are both configured as UART ports.

[0024] Furthermore, combined Figure 1 , Figure 3 as well as Figure 5As shown, when the communication circuit is in idle mode, the IC of the communication circuit is in a state of continuous monitoring of the bus.

[0025] Because the TX pin is at a low level, the first switch Q1 and the second switch Q2 are not conducting, while the fourth switch Q4 is conducting. The RX pin is at a high level, and the AND gate U2 outputs a high level, so the third switch Q3 is not conducting.

[0026] In the embodiments of this utility model, the communication circuit described above can accommodate various communication baud rates of external devices, ensuring normal communication regardless of whether the baud rate is low or high. Furthermore, this communication circuit does not require additional I / O port resources; the IC can be enabled directly through the CPU, i.e., the TX or RX pin on the controller, enabling the communication circuit to send and receive data.

[0027] In the embodiments of this utility model, combined with Figure 2 As shown, the communication circuit also includes a filter circuit 14, and the communication chip 13 is connected to the bus 15 through the filter circuit 14; Specifically, the filtering circuit 14 is used to filter the signals of the bus 15.

[0028] In the embodiments of this utility model, combined with Figure 2 and Figure 3 As shown, the filter circuit 14 includes at least two first resistors R1 and two second capacitors C2.

[0029] Specifically, one end of each of the two first resistors R1 is connected to pins A and B of the communication chip 13, respectively, and the other end of each of the two first resistors R1 is connected to one end of each of the two second capacitors C2, and the other end of each of the two second capacitors C2 is grounded.

[0030] In some embodiments, the filtering circuit may employ other structures that also have filtering functions, such as filtering via an inductor. Specific configurations can be made according to actual conditions, and the relevant circuits will not be described in detail here.

[0031] In the embodiments of this utility model, combined with Figure 4 (The figure shows the control circuit 12) As shown, the communication circuit also includes a signal isolation circuit 16. One end of the signal isolation circuit 16 is connected to the DI pin and RO pin of the communication chip 13, and the other end of the signal isolation circuit 16 is connected to the RX pin and TX pin of the controller 11.

[0032] Specifically, the signal isolation circuit 16 is used to achieve electrical isolation between the controller 11 and the communication chip 13 through optocoupler or magnetic isolation, thereby suppressing common-mode interference.

[0033] Furthermore, the signal isolation circuit is an optocoupler.

[0034] In the embodiments of this utility model, combined with Figure 5 As shown, the specific structure of the control circuit 12 is as follows: The first terminal of AND gate U2 has an RX pin, an / RE pin, and a DE pin. The second terminal of AND gate U2 is connected to the first terminal of the fourth resistor R4. The first terminals of the fourth resistor R4 and the fifth resistor R5 are connected to the gate of the third switch. The first terminal of the fifth resistor R5 and the source of the third switch Q3 are connected to ground. The drain of the third switch Q3, the first terminal of the second resistor R2, and the first terminal of the third resistor R3 are connected to the gate of the second switch Q2. The source of the second switch Q2 and the second terminal of the third resistor R3 are grounded. The anode of the second diode D2 has a TX pin. The cathode of the second diode D2 and the drain of the first switch Q1 are connected to the second terminal of the second resistor R2. The source of the first switch Q1 is connected to the first terminal of the first power supply VCC1 and the first terminal of the sixth resistor R6. The second terminal of the first power supply VCC1 is grounded. The sixth resistor... The second end of R6 is connected to the gate of the first switch Q1, the drain of the second switch Q2, and one end of the cathode of the first diode D1. The anode of the first diode D1 is connected to the first end of the seventh resistor R7, the first end of the eighth resistor R8, and the gate of the fourth switch Q4. The second end of the eighth resistor R8, the source of the fourth switch Q4, and the first end of the first capacitor C1 are grounded. The drain of the fourth switch Q4 is connected to the first end of the ninth resistor R9 and the first end of the tenth resistor R10. The second end of the tenth resistor R10 is connected to the second end of the first capacitor C1, and an / RE pin and a DE pin are provided at the connection between the second end of the tenth resistor R10 and the second end of the first capacitor C1. The second ends of the seventh resistor R7 and the second ends of the ninth resistor R9 are connected to one end of the second power supply VCC2, and the second end of the second power supply VCC2 is grounded.

[0035] Specifically, the first switch Q1 is a P-MOSFET, and the second switch Q2, the third switch QQ3, and the fourth switch QQ4 are N-MOSFETs.

[0036] The technical solution provided by this utility model includes a communication circuit comprising a communication chip, a controller, and a control circuit connected to a bus; the RO pin of the communication chip is connected to the RX pin of the controller, the DI pin of the communication chip is connected to the TX pin of the controller, the / RE pin and DE pin of the control circuit are respectively connected to the / RE pin and DE pin of the communication chip, and the RX pin and TX pin of the control circuit are respectively connected to the RX pin and TX pin of the controller; when the communication circuit is in idle mode, the / RE pin and DE pin of the communication chip are set to low level, the first switch, the second switch, and the third switch in the control circuit are open, and the fourth switch is turned on; the RX pin and TX pin of the controller are both configured as UART ports; when the communication circuit is in receive mode... In the transmission mode, the controller multiplexes the TX pin as a GPIO port and controls the second and first switches in the control circuit to turn on, and the fourth and third switches to turn off through the GPIO port. After the DE pin of the communication chip is enabled, the controller converts the TX pin to a UART port and sends data to the communication chip through the TX pin. When the communication circuit is in transmit mode, the controller multiplexes the RX pin as a GPIO port and controls the second and first switches in the control circuit to turn off, and the fourth and third switches to turn on through the GPIO port. After the / RE pin of the communication chip is enabled, the controller converts the RX pin to a UART port and receives data sent by the communication chip through the RX pin. This technical solution, by adding a control circuit to the communication circuit, enables the pins on the communication chip, solving the problem of meeting the control requirements of the enable pin during communication when the controller lacks IO port resources, improving communication efficiency, and also meeting the communication requirements of different baud rates.

[0037] An exemplary embodiment of this utility model provides an electronic device, including the communication circuit described in the above embodiment.

[0038] For details on the specific implementation methods of this application, please refer to the foregoing content, which will not be repeated here.

[0039] The present invention will be further described in conjunction with the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent forms also fall within the scope defined in this application.

Claims

1. A communication circuit, characterized in that, The communication circuit includes: a communication chip, a controller, and a control circuit connected to the bus; The RO pin of the communication chip is connected to the RX pin of the controller, the DI pin of the communication chip is connected to the TX pin of the controller, the / RE pin and DE pin of the control circuit are respectively connected to the / RE pin and DE pin of the communication chip, and the RX pin and TX pin of the control circuit are respectively connected to the RX pin and TX pin of the controller. When the communication circuit is in receive mode, the controller multiplexes the TX pin as a GPIO port and controls the control circuit to switch to the first state through the GPIO port. After the switch is successful, the controller converts the TX pin to a UART port and sends data to the communication chip through the TX pin. When the communication circuit is in transmit mode, the controller multiplexes the RX pin as a GPIO port and controls the control circuit to switch to the second state through the GPIO port. After the switch is successful, the controller converts the RX pin to a UART port and receives the data sent by the communication chip through the RX pin.

2. The communication circuit according to claim 1, characterized in that, When the communication circuit is in idle mode, the / RE pin and DE pin of the communication chip are set to low level, the first switch, the second switch, the third switch in the control circuit are turned off, and the fourth switch is turned on. The RX pin and TX pin of the controller are both configured as UART ports.

3. The communication circuit according to claim 1, characterized in that, The first state refers to The second switch and the first switch in the control circuit are turned on, while the fourth switch and the third switch are turned off; The second state refers to the second switch and the first switch in the control circuit being open, and the fourth switch and the third switch being closed.

4. The communication circuit according to claim 1, characterized in that, The communication circuit further includes a filtering circuit, and the communication chip is connected to the bus through the filtering circuit. The filtering circuit is used to filter the signals of the bus.

5. The communication circuit according to claim 4, characterized in that, The filter circuit includes at least two first resistors and two second capacitors; One end of each of the two first resistors is connected to pin A and pin B of the communication chip, respectively, and the other end of each of the two first resistors is connected to one end of each of the two second capacitors, with the other end of each of the two second capacitors grounded.

6. The communication circuit according to claim 1, characterized in that, The communication circuit also includes a signal isolation circuit, one end of which is connected to the DI pin and RO pin of the communication chip, and the other end of which is connected to the RX pin and TX pin of the controller. The signal isolation circuit is used to achieve electrical isolation between the controller and the communication chip through optocoupler or magnetic isolation, and to suppress common-mode interference.

7. The communication circuit according to claim 6, characterized in that, The signal isolation circuit is an optocoupler.

8. The communication circuit according to claim 3, characterized in that, The control circuit includes: The first terminal of the AND gate has an RX pin, an / RE pin, and a DE pin. The second terminal of the AND gate is connected to the first terminal of a fourth resistor. The first terminal of the fourth resistor and the second terminal of a fifth resistor are connected to the gate of a third switch. The first terminal of the fifth resistor and the source of the third switch are connected to ground. The drain of the third switch, the first terminal of the second resistor, and the first terminal of the third resistor are connected to the gate of the second switch. The source of the second switch and the second terminal of the third resistor are grounded. One anode terminal of the second diode has a TX pin. One cathode terminal of the second diode and the drain of the first switch are connected to the second terminal of the second resistor. The source of the first switch is connected to the first terminal of a first power supply and the first terminal of a sixth resistor. The second terminal of the first power supply is grounded. The second end of the six resistors is connected to the gate of the first switch, the drain of the second switch, and one end of the cathode of the first diode. The anode of the first diode is connected to the first end of the seventh resistor, the first end of the eighth resistor, and the gate of the fourth switch. The second end of the eighth resistor, the source of the fourth switch, and the first end of the first capacitor are grounded. The drain of the fourth switch is connected to the first end of the ninth resistor and the first end of the tenth resistor. The second end of the tenth resistor is connected to the second end of the first capacitor. An / RE pin and a DE pin are provided at the connection between the second end of the tenth resistor and the second end of the first capacitor. The second end of the seventh resistor and the second end of the ninth resistor are connected to one end of the second power supply. The second end of the second power supply is grounded.

9. The communication circuit according to claim 8, characterized in that, The first switch is a P-MOSFET, and the second, third, and fourth switches are N-MOSFETs.

10. An electronic device, characterized in that, Includes the communication circuit described in any one of claims 1-9.

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