Circuit with dual-mipi image receiving function and endoscope host

Abstract

The utility model discloses a kind of circuit and endoscope host with double MIPI image receiving function, circuit with double MIPI image receiving function includes visual processing unit, it is equipped with the optical endoscope special circuit channel and the electronic endoscope special circuit channel that can be connected with optical endoscope and electronic endoscope respectively;Only with the power supply end electrical connection of optical endoscope special circuit channel's first analog power supply;Only with the power supply end electrical connection of electronic endoscope special circuit channel's second analog power supply;And power supply noise suppression module, its input end connects external power supply, its output end is connected to the input end of first analog power supply and the input end of second analog power supply respectively, for filtering ripple noise introduced by external power supply. So that optical endoscope and electronic endoscope can be used simultaneously, solve the problem of high procurement and operation cost due to equipment redundancy;Power supply noise suppression module can also completely isolate digital power supply ripple interference.

Description

Technical Field

[0001] This utility model relates to the field of endoscope circuit technology, specifically to a circuit with dual-channel MIPI image receiving function and an endoscope host. Background Technology

[0002] Traditional endoscope main control hardware generally adopts a single-channel MIPI (Mobile Industry Processor Interface) image receiving architecture, which can only be adapted to a single type of probe and cannot be compatible with optical endoscopes and electronic endoscopes at the same time. Multiple dedicated main units are required for different types of endoscopes, resulting in low equipment utilization and high costs. Utility Model Content

[0003] To solve at least one of the aforementioned problems, according to one aspect of the present invention, a circuit with dual-channel MIPI image receiving function is provided.

[0004] The circuit with dual-channel MIPI image receiving function includes a vision processing unit, which has a dedicated optical endoscope circuit channel that can be connected to an optical endoscope, a dedicated electronic endoscope circuit channel that can be connected to an electronic endoscope, a first analog power supply that is electrically connected only to the power supply terminal of the dedicated optical endoscope circuit channel, a second analog power supply that is electrically connected only to the power supply terminal of the dedicated electronic endoscope circuit channel, and a power supply noise suppression module, whose input terminal is connected to an external power supply and whose output terminal is connected to a common power supply node. The common power supply node is connected to the input terminals of the first analog power supply and the second analog power supply, respectively, for filtering out ripple noise introduced by the external power supply.

[0005] By setting up dedicated circuit channels for optical endoscopes and electronic endoscopes, as well as a first analog power supply, a second analog power supply, and a power supply noise suppression module, not only can optical endoscopes and electronic endoscopes connected to the dedicated circuit channels for optical endoscopes and electronic endoscopes be used simultaneously, solving the problems of equipment redundancy and high procurement and maintenance costs, but the power supply noise suppression module can also completely isolate digital power supply ripple interference.

[0006] In some implementations, the dedicated circuit channel for the optical endoscope includes a first data transmission pin group and a first auxiliary control pin group; the first data transmission pin group includes a 4-lane (data channel) MIPI differential clock pin and four differential data pins, all of which are connected to the MIPI_RX0 (0th receive pin) interface of the vision processing unit; the first auxiliary control pin group includes a first independent sensor clock pin, a first line synchronization pin, a first frame synchronization pin, and a first sensor reset pin; each pin is used for the transmission of the corresponding signal.

[0007] Because a separate MIPI hardware receiving channel (MIPI_RX0) is dedicated to the optical endoscope circuit, and standardized high-speed image electrical signal receiving pins are reserved, a hardware access port can be provided for the digital image signal after photoelectric conversion.

[0008] In some implementations, the dedicated circuit channel for the electronic endoscope includes a second data transmission pin group and a second auxiliary control pin group; the second data transmission pin group includes a 2-lane MIPI differential clock pin and two differential data pins, both of which are connected to the MIPI_RX1 (first receiving pin) interface of the vision processing unit; the second auxiliary control pin group includes a second independent sensor clock pin, a second line synchronization pin, a second frame synchronization pin, and a second sensor reset pin; each pin is used for the transmission of the corresponding signal.

[0009] In some implementations, the power supply noise suppression module includes an isolation element and a power supply filter capacitor. One end of the isolation element is connected to a 1.8V system power supply network, and the other end is connected to a common power supply node. The common power supply node is connected to a first analog power supply and a second analog power supply, respectively. One end of the power supply filter capacitor is connected to the common power supply node, and the other end is grounded. The isolation element and the power supply filter capacitor together form a (first-order or second-order) RC (resistor / capacitor) low-pass filter circuit, suitable for low-power MIPI auxiliary power supply line noise control. Thus, digital power supply ripple interference can be completely isolated through the isolation element and the power supply filter capacitor.

[0010] In some embodiments, the vision processing unit further includes an auxiliary interface for connecting an external image sensor; the auxiliary interface includes a sensor master clock output terminal, a sensor horizontal synchronization input terminal, a sensor vertical synchronization input terminal, a sensor reset output terminal, a first bus communication terminal, a second bus communication terminal, and a general-purpose digital input / output terminal; a first resistor is connected in series to the sensor master clock output terminal; the first bus communication terminal and the second bus communication terminal each include a data signal pin and a clock signal pin, and each data signal pin and each clock signal pin are respectively connected in series with a second resistor; the resistance values ​​of the first resistor and the second resistor are both 33Ω. Thus, the first resistor can be used for impedance matching of the clock signal during operation, reducing ringing, and the first and second resistors can protect the chip pins from being burned out by a sudden large current when the sensor is short-circuited or malfunctioning; simultaneously, since the vision processing unit of this invention divides all interactive pins into three functional areas—timing control, I2C (integrated circuit bus) communication, and general-purpose IO (input / output)—the PCB (printed circuit board) layout is divided into regional wiring, and various signal lines are physically isolated to avoid cross-wiring; isolation is achieved through physical wiring.

[0011] In some embodiments, the circuit with dual-channel MIPI image reception further includes a bidirectional level conversion module connected between the auxiliary communication bus interface of the vision processing unit and the external image sensor. The bidirectional level conversion module converts a first logic level on the bus communication side to a second logic level on the external image sensor side, and converts the second logic level on the external image sensor side back to the first logic level on the bus communication side. The first logic level is 1.8V, and the second logic level is higher than the first logic level. In some embodiments, the second logic level is 3.3V.

[0012] In some embodiments, the circuit with dual-channel MIPI image reception function further includes a security module; the security module is connected in series between the bidirectional level conversion module and the external image sensor; the first signal terminal of the security module is connected to the bidirectional level conversion module and is used to receive the high-level clock signal and high-level data signal output by the bidirectional level conversion module; the second signal terminal of the security module is connected to the reset signal output terminal of the vision processing unit and is used to receive the reset signal output by the vision processing unit and output the reset signal to the external image sensor.

[0013] In some embodiments, the bidirectional level conversion module includes a bidirectional level conversion chip, which is a TXS0102DCU chip and has a low-voltage side power supply pin, a high-voltage side power supply pin, a low-voltage side signal pin group, a high-voltage side signal pin group, an enable pin, and a ground pin; as well as pull-up resistors; the low-voltage side power supply pin and the enable pin are respectively connected to a first power supply network through pull-up resistors; the low-voltage side signal pin group is respectively connected to the I2C clock pin and the I2C data pin of the vision processing unit; the high-voltage side power supply pin is connected to a second power supply network, the voltage of the second power supply network being higher than that of the first power supply network; the high-voltage side signal pin group is respectively connected to a safety module for outputting a level-converted high-voltage I2C clock signal and a high-voltage I2C data signal to the safety module; and the ground pin is grounded.

[0014] In some implementations, the security module includes: a security encryption chip (model LKT4304), a first current-limiting resistor, a second current-limiting resistor, a third current-limiting resistor, a pull-up resistor, and a filter capacitor; the power supply pin of the security encryption chip is connected to a 3.3V power supply network, the ground pin is grounded, and the filter capacitor is connected in parallel between the power supply pin and ground; the first data pin of the security encryption chip is connected to the 3.3V I2C data signal output by the bidirectional level conversion module via the first current-limiting resistor, and the clock pin of the security encryption chip is connected to the 3.3V I2C clock signal output by the bidirectional level conversion module via the second current-limiting resistor; the reset pin of the security encryption chip is connected to the 3.3V power supply network via the pull-up resistor and to the reset control pin of the vision processing unit via the third current-limiting resistor.

[0015] In some implementations, the vision processing unit is an SS928V100 chip. Since the SS928V100 chip receives a 1.8V low-level signal (logic level), while the lens sensor and arthroscopic gyroscope receive a 3.3V high-level signal, the operating levels of the SS928V100 chip and the lens sensor and arthroscopic gyroscope are mismatched. Direct communication could easily lead to data read / write failures and device breakdown. This invention introduces a bidirectional level conversion module to perform level conversion before communication, ensuring data read / write stability and extending device lifespan.

[0016] According to one aspect of the present invention, an endoscope host is provided, which can be used as a 4K (referring to a resolution of 3840×2160 pixels) photoelectric split-type diagnostic and treatment host.

[0017] The endoscope host includes an optical endoscope interface and an electronic endoscope interface; as well as the aforementioned circuit with dual-channel MIPI image receiving function; wherein the optical endoscope interface and the electronic endoscope interface are respectively connected to the optical endoscope dedicated circuit channel and the electronic endoscope dedicated circuit channel of the vision processing unit.

[0018] In some preferred embodiments, the endoscope host also includes an optical endoscope, which is equipped with an external CMOS (Complementary Metal-Oxide-Semiconductor) image sensor. This allows the optical image to be first converted into a high-speed differential electrical signal in MIPI format, and then connected to the SS928V100 chip via a dedicated channel, thus realizing a conversion link from optical image to electrical signal to chip processing and solving the problem that optical signals cannot be directly connected to the processing chip. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the module structure of a circuit with dual-channel MIPI image receiving function according to the first embodiment of this application; Figure 2 This is a schematic diagram of the module structure of a circuit with dual-channel MIPI image receiving function according to the second embodiment of this application; Figure 3 This is a schematic diagram of the module structure of a circuit with dual-channel MIPI image receiving function according to the third embodiment of this application; Figure 4 This is a schematic diagram of the module structure of a circuit with dual-channel MIPI image receiving function according to the fourth embodiment of this application. Figure 5 This is a schematic diagram of the module structure of a circuit with dual-channel MIPI image receiving function according to the fifth embodiment of this application; Figure 6 This is a schematic diagram of the circuit structure of a dedicated circuit channel for an optical endoscope according to one embodiment of this application. Figure 7 This is a schematic diagram of the circuit structure of a dedicated circuit channel for an electronic endoscope according to one embodiment of this application. Figure 8 This is a schematic diagram of the circuit structure of a power supply noise suppression module according to an embodiment of this application; Figure 9 This is a partial circuit structure diagram of a circuit with dual-channel MIPI image receiving function according to an embodiment of this application. Figure 10 for Figure 9 The diagram shows a partial amplifier circuit structure of one part of a circuit with dual-channel MIPI image receiving function. Figure 11 for Figure 9 The diagram shows another partial amplifier circuit structure of the circuit with dual-channel MIPI image receiving function. Figure 12 This is a schematic diagram of the circuit structure of a bidirectional level conversion module according to one embodiment of this application; Figure 13 This is a schematic diagram of the circuit structure of a security module according to one embodiment of this application; Figure 14 This is a schematic diagram of the structure of an endoscope host according to one embodiment of this application; Figure 15 This is a schematic diagram of the endoscope host according to one embodiment of this application, omitting the top cover; Reference numerals: 11. Housing; 111. First receiving cavity; 112. Optical endoscope interface; 113. Electronic endoscope interface; 114. Cold light source interface; 1141. Cold light source module; 115. Display screen; 116. Switch; 12. Circuit with dual-channel MIPI image receiving function; 121. Power supply circuit module; 122. Image processing circuit module; 20. Vision processing unit; 21. Dedicated circuit channel for optical endoscope; 22. Dedicated circuit channel for electronic endoscope; 251. Sensor master clock output terminal; 252. Sensor horizontal synchronization input terminal; 253. Sensor vertical synchronization input terminal; 254. Sensor reset output terminal; 255. First bus communication terminal; 256. Second bus communication terminal; 257. General purpose digital input / output terminal; 31. First analog power supply; 32. Second analog power supply; 40. Power supply noise suppression module; 41. Isolation element; 42. Power supply filter capacitor; 50. Bidirectional level conversion module; 60. Safety module. Detailed Implementation

[0020] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0021] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising" or "including" include not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The terminology used herein is generally that commonly used by those skilled in the art; in case of any discrepancy with commonly used terminology, the terminology used herein shall prevail.

[0022] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0024] Figure 1 , Figure 6 and Figure 7 The circuit with dual-channel MIPI image receiving function according to the first embodiment of the present invention is shown schematically.

[0025] like Figure 1 As shown, the circuit 12 with dual-channel MIPI image receiving function includes a vision processing unit 20, a first analog power supply 31, a second analog power supply 32, and a power supply noise suppression module 40. The vision processing unit 20 is provided with an optical endoscope-specific circuit channel 21 that can be connected to an optical endoscope and an electronic endoscope-specific circuit channel 22 that can be connected to an electronic endoscope. The first analog power supply 31 is electrically connected only to the power supply terminal of the optical endoscope-specific circuit channel 21. The second analog power supply 32 is electrically connected only to the power supply terminal of the electronic endoscope-specific circuit channel 22. The power supply noise suppression module 40 has its input terminal connected to an external power supply and its output terminal connected to a common power supply node. The common power supply node is connected to the input terminals of the first analog power supply 31 and the second analog power supply 32, respectively, for filtering out ripple noise introduced by the external power supply.

[0026] In some embodiments, such as Figure 6As shown, the dedicated circuit channel 21 for the optical endoscope includes a first data transmission pin group and a first auxiliary control pin group. The first data transmission pin group includes a 4-lane MIPI differential clock pin and four differential data pins, all of which are connected to the MIPI_RX0 interface of the vision processing unit 20. The first auxiliary control pin group includes a first independent sensor clock pin, a first line synchronization pin, a first frame synchronization pin, and a first sensor reset pin. Each pin is used for the transmission of its corresponding signal. This maximizes the image transmission bandwidth, meeting the high-speed transmission requirements of high-definition image data.

[0027] In some embodiments, such as Figure 7 As shown, the dedicated circuit channel 22 for the electronic endoscope includes a second data transmission pin group and a second auxiliary control pin group. The second data transmission pin group includes a 2-lane MIPI differential clock pin and two differential data pins. The 2-lane MIPI differential clock pin and the two differential data pins are all connected to the MIPI_RX1 interface of the vision processing unit 20. The second auxiliary control pin group includes a second independent sensor clock pin, a second line synchronization pin, a second frame synchronization pin, and a second sensor reset pin. Each pin is used for the transmission of the corresponding signal.

[0028] In some preferred embodiments, the two MIPI differential traces are designed with strict 100Ω differential impedance in terms of board material, trace width, trace spacing, and reference layer; the P / N (positive / negative) signal lines in the same differential pair are strictly routed with equal length, and the data channels in different lanes are constrained to be of equal length within the group to avoid high-speed signal integrity degradation caused by impedance abrupt changes and timing offsets, and to achieve standard impedance control from the PCB physical layer.

[0029] As one embodiment of the vision processing unit 20, the vision processing unit 20 uses a chip of model SS928V100. In this embodiment, as... Figure 6As shown, the optical endoscope dedicated circuit channel 21 of the SS928V100 chip receives high-speed differential clock signals from an image sensor (such as an endoscope CMOS probe) via MIPI_RX0_CK0N [the negative / N pin of the 0th pair of clock signals in the 0th MIPI CSI-2 receiver interface, used to receive the high-speed differential clock signal], MIPI_RX0_CK0P (the positive pin of the 0th channel used to receive the 0th pair of MIPI differential clock signals from the endoscope image sensor), and MIPI_RX0_D0N [the 0th data lane of the 0th MIPI CSI-2 receiver interface (RX0)]. The negative / N pins of the MIPI receiver interface (0), MIPI_RX0_D0P (positive pin of data channel 0 of MIPI receiver interface 0), MIPI_RX0_D1N (negative pin of data channel 1 of MIPI receiver interface 0), MIPI_RX0_D1P (positive pin of data channel 1 of MIPI receiver interface 0), MIPI_RX0_D2N (negative pin of data channel 2 of MIPI receiver interface 0), MIPI_RX0_D2P (positive pin of data channel 2 of MIPI receiver interface 0), MIPI_RX0_D3N (negative pin of data channel 3 of MIPI receiver interface 0), and MIPI_RX0_D3P (positive pin of data channel 3 of MIPI receiver interface 0) are connected to the interface of the optical endoscope. In this embodiment, as shown... Figure 7As shown, the dedicated electronic endoscope circuit channel 22 of the SS928V100 chip is connected to the interface of the electronic endoscope through the pins MIPI_RX1_CK0N (negative pin of the 0th pair of clock signals in the 1st MIPI receiver interface), MIPI_RX1_CK0P (positive pin of the 0th pair of clock signals in the 1st MIPI receiver interface), MIPI_RX1_D0N (negative pin of the 0th data channel of the 1st MIPI receiver interface), MIPI_RX1_D0P (positive pin of the 0th data channel of the 1st MIPI receiver interface), MIPI_RX1_D1N (negative pin of the 1st data channel of the 1st MIPI receiver interface), and MIPI_RX1_D1P (positive pin of the 1st data channel of the 1st MIPI receiver interface). As can be seen, this circuit is configured with two completely independent 4-lane (data channel) MIPI image receiving channels; the four sets of differential clocks and four sets of differential image data output from the optical endoscope are connected to the MIPI_RX0 pin; the differential clocks and differential image data output from the electronic endoscope are connected to the MIPI_RX1 pin. In this embodiment, the first analog power supply 31 and the second analog power supply 32 of the SS928V100 chip are connected to the power supply noise suppression module 40 as follows: the AVDD18_MIPIRX1 (pin of the first MIPI receiver of the 1.8V analog power supply) and AVDD18_MIPIRX2 (pin of the second MIPI receiver of the 1.8V analog power supply) pins of the SS928V100 chip are both connected to the power supply noise suppression module 40.

[0030] As one embodiment of the power supply noise suppression module 40, combined with Figure 2 and Figure 8 As shown, the power supply noise suppression module 40 includes an isolation element 41 and a power supply filter capacitor 42. One end of the isolation element 41 is connected to a 1.8V system power supply network, and the other end is connected to a common power supply node. The common power supply node is connected to a first analog power supply 31 and a second analog power supply 32, respectively. One end of the power supply filter capacitor 42 is connected to the common power supply node, and the other end is grounded. In one embodiment of the isolation element 41, a 0Ω resistor is used; in another embodiment, a ferrite bead is used, with the 1.8V system power supply network connected to the input terminal of the ferrite bead and the output terminal of the ferrite bead connected to a common power supply node.

[0031] Since the first analog power supply 31 and the second analog power supply 32 respectively connect the optical endoscope dedicated circuit channel 21 and the electronic endoscope dedicated circuit channel 22 to the power supply noise suppression module 40, not only can the optical endoscope and the electronic endoscope connected to the optical endoscope dedicated circuit channel 21 and the electronic endoscope dedicated circuit channel 22 be used simultaneously, solving the problems of equipment redundancy and high procurement and maintenance costs; the power supply noise suppression module 40 can also completely isolate digital power supply ripple interference.

[0032] In some embodiments, combined with Figure 3 , Figures 9 to 11 As shown, the vision processing unit 20 also includes an auxiliary interface for connecting an external image sensor; the auxiliary interface includes a sensor master clock output terminal 251, a sensor horizontal synchronization input terminal 252, a sensor vertical synchronization input terminal 253, a sensor reset output terminal 254, a first bus communication terminal 255, a second bus communication terminal 256, and a general-purpose digital input / output terminal 257; the sensor master clock output terminal 251 is connected in series with a first resistor (the sensor master clock output terminal 251 is connected to the external image sensor via the first resistor); the first bus communication terminal 255 and the second bus communication terminal 256 each include a data signal pin and a clock signal pin, and each data signal pin and each clock signal pin are respectively connected in series with a second resistor; the resistance values ​​of the first resistor and the second resistor are both 33Ω.

[0033] In some specific embodiments, combined with Figure 9 and Figure 10 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the sensor master clock output terminal 251 can be implemented as the SENSOR0_CLK (master clock output of the 0th image sensor) pin of the SS928V100 chip, which is dedicated to the MIPI_RX0 channel; and the SENSOR1_CLK (master clock output of the 1st image sensor) pin, which is dedicated to the MIPI_RX1 channel. The SENSOR0_CLK and SENSOR1_CLK pins are output pins used to provide clock to the sensor. A first resistor needs to be connected in series with them, for example: R120 in series with the SENSOR0_CLK pin and R363 in series with the SENSOR1_CLK pin, so as to provide impedance matching for the clock signal during operation, reduce ringing, and protect the chip pins from being burned out by instantaneous large current when the sensor is short-circuited or abnormal. In some embodiments, SENSOR1_CLK is configured with two multiplexed alternative traces to resolve the GPIO (General Purpose Input / Output) pin function conflict caused by the PCIe (High-Speed ​​Serial Computer Expansion Bus Standard) high-speed port integrated in the hardware circuit where the SENSOR1_CLK pin is located. Specifically, one trace is connected in series with R363, and the other trace is connected in series with R122.

[0034] In some specific embodiments, combined with Figure 9 and Figure 10 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the sensor horizontal synchronization input terminal 252 can be implemented as the SENSOR0_HS (horizontal synchronization signal of the 0th image sensor) pin of the SS928V100 chip. This pin is an input pin used to receive the horizontal synchronization signal of the MIPI_RX0 channel sensor; the SENSOR1_HS (horizontal synchronization signal of the 1st image sensor) pin is an input pin used to receive the horizontal synchronization signal of the MIPI_RX1 channel sensor; the IO (input / output) voltage of these pins is 1.8V, therefore, their pull-up resistors must be connected to 1.8V; electronic endoscopes usually do not require a separate SENSOR0_HS connection, while optical endoscopes require an external horizontal synchronization signal to match the timing requirements of the external CMOS sensor. Therefore, optical endoscopes generally need to be connected to the SENSOR0_HS pin.

[0035] In some specific embodiments, combined with Figure 9 and Figure 10 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the sensor vertical synchronization input terminal 253 can be implemented as the SENSOR0_VS (vertical synchronization signal of the 0th image sensor) pin of the SS928V100 chip. This pin is an input pin used to receive the vertical synchronization signal of the MIPI_RX0 channel sensor; the SENSOR1_VS (vertical synchronization signal of the 1st image sensor) pin is an input pin used to receive the vertical synchronization signal of the MIPI_RX1 channel sensor; these pins generally also need to be connected to 1.8V.

[0036] In some specific embodiments, combined with Figure 9 and Figure 10 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the sensor reset output terminal 254 can be implemented as the SENSOR0_RSTN pin of the SS928V100 chip, which is a signal pin specifically used by the chip to control the hardware reset of the first image sensor (corresponding to the MIPI_RX0 channel); the SENSOR1_RSTN pin is a signal pin specifically used by the chip to control the hardware reset of the second image sensor (corresponding to the MIPI_RX1 channel). This pin is an output pin, and the SS928V100 chip actively controls the hardware reset of the external CMOS image chip by pulling the level of this pin low or high.

[0037] In some specific embodiments, combined with Figure 9 and Figure 11As shown, when the vision processing unit 20 uses a chip of model SS928V100, the first bus communication terminal 255 can be implemented as the SPI0_CSN / I2C3_SDA pin of the SS928V100 chip. When configured for I2C function, it is used as the data line of the I2C3 bus, which is a bidirectional data line used to transmit address and data in I2C communication.

[0038] In some specific embodiments, combined with Figure 9 and Figure 11 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the second bus communication terminal 256 can be implemented as the SPI1_SDI / I2C5_SCL pin of the SS928V100 chip. When configured for I2C function, this pin is used as the clock line of the I2C5 bus. The clock signal is generated by the master device and used to synchronize the data transmission on the bus. A first resistor, such as R121, needs to be connected in series with it to provide impedance matching for the clock signal during operation, reduce ringing, and protect the chip pin from being burned by a sudden large current when the sensor is short-circuited or abnormal.

[0039] In some specific embodiments, combined with Figure 9 and Figure 11 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the second bus communication terminal 256 can also be implemented as the SPI0_SDI / I2C3_SCL pin of the SS928V100 chip. When configured for I2C function, this pin is used as the clock line of the I2C3 bus. The clock signal is generated by the master device and used to synchronize data transmission on the bus.

[0040] In some specific embodiments, combined with Figure 9 and Figure 11 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the first bus communication terminal 255 can also be implemented as the SPI0_CSN / I2C5_SDA pin of the SS928V100 chip. When configured for I2C function, it is used as the data line of the I2C5 bus. This is a bidirectional data line used to transmit address and data in I2C communication. A first resistor, such as R214, needs to be connected in series on it to provide impedance matching for the data signal during operation, reduce ringing, and protect the chip pins from being burned by instantaneous large current when the sensor is short-circuited or abnormal.

[0041] In some embodiments, the SPI1_SDI / I2C5_SCL pin and the SPI0_CSN / I2C5_SDA pin are used to interface with the arthroscope handle gyroscope chip to collect real-time rotation and deflection attitude data of the arthroscope, providing hardware data support for the automatic image correction function.

[0042] In some specific embodiments, combined with Figure 9 and Figure 11 As shown, when the vision processing unit 20 uses the SS928V100 chip, the general-purpose digital input / output terminal 257 can be implemented as the GPIO12_3 pin of the SS928V100 chip. It is a general-purpose digital input / output pin, and its most basic function is a general-purpose I / O port that can be controlled by software. "12" usually refers to the GPIO port number to which it belongs; "3" refers to the specific pin number within the port. The pin can be configured by software to input mode (used to read the high and low levels of external signals) or output mode (used to output high / low level signals). In output mode, the pin can be controlled to output a high or low level to drive LEDs, control MOSFET switches, etc. In input mode, it can read signals such as external buttons and sensor interrupts. The GPIO12_02 pin of the SS928V100 chip can be configured via software to either input mode (for reading high / low levels of external signals) or output mode (for outputting high / low level signals). In output mode, the pin can be controlled to output a high or low level for driving LEDs, controlling MOSFET switches, etc. In input mode, it can read signals from external buttons, sensor interrupts, etc. A first resistor, such as R123, needs to be connected in series to it to provide impedance matching for the control signal during operation, reduce ringing, and protect the chip pin from being burned out by a sudden large current in case of a sensor short circuit or abnormality. The GPIO12_4 pin of the SS928V100 chip can also be configured via software to either input mode (for reading high / low levels of external signals) or output mode (for outputting high / low level signals). In output mode, the pin can be controlled to output a high or low level for driving LEDs, controlling MOSFET switches, etc. In input mode, it can read signals from external buttons, sensor interrupts, etc.

[0043] In some specific embodiments, combined with Figure 9 and Figure 11 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the first bus communication terminal 255 can also be implemented as the SPI0_I2C2_SDA pin of the SS928V100 chip. When configured for I2C function, it is used as the data line of the I2C2 bus. This is a bidirectional data line used to transmit address and data in I2C communication. A first resistor, such as R125, needs to be connected in series on it to provide impedance matching for the data signal during operation, reduce ringing, and protect the chip pins from being burned by instantaneous large current when the sensor is short-circuited or abnormal.

[0044] In some specific embodiments, combined with Figure 9 and Figure 11 As shown, when the vision processing unit 20 uses a chip of model SS928V100, the second bus communication terminal 256 can also be implemented as the SPI1_I2C2_SCL pin of the SS928V100 chip. When configured for I2C function, this pin is used as the clock line of the I2C2 bus. The clock signal is generated by the master device and is used to synchronize the data transmission on the bus. A first resistor, such as R124, needs to be connected in series with it to provide impedance matching for the clock signal during operation, reduce ringing, and protect the chip pin from being burned by a sudden large current when the sensor is short-circuited or abnormal.

[0045] In some embodiments, the SPI0_I2C2_SDA pin and the SPI1_I2C2_SCL pin are used to interface with the register configuration and parameter debugging of the built-in CMOS image sensor of optical endoscopes and electronic endoscopes.

[0046] In some preferred embodiments, the differential clock and differential image data output by the electronic endoscope are connected to the MIPI_RX1 pin, as well as the SENSOR1_HS and SENSOR1_VS pins. Because the electronic endoscope additionally matches the VI_VS field synchronization and VI_HS line synchronization timing pins, it synchronously acquires the timing signals of the electronic endoscope's CMOS sensor, ensuring accurate and error-free timing of dynamic image output. The optical endoscope is connected to the MIPI_RX1 pin, as well as the SENSOR0_HS and SENSOR0_VS pins.

[0047] In some preferred embodiments, such as Figure 4 As shown, the circuit 12 with dual-channel MIPI image reception function also includes a bidirectional level conversion module 50; connected between the auxiliary communication bus interface of the vision processing unit 20 and the external image sensor; the bidirectional level conversion module 50 is used to convert the first logic level on the bus communication end side to the second logic level on the external image sensor side, and to convert the second logic level on the external image sensor side to the first logic level on the bus communication end side; the first logic level is 1.8V, and the second logic level is higher than the first logic level. In some embodiments, the second logic level is 3.3V. Thus, the endoscope host with this circuit 12 with dual-channel MIPI image reception function can be used with the 1.8V level SS928V100 chip, and can also be used with the 3.3V level image sensor and arthroscopic gyroscope. When the sensor outputs a 3.3V HS signal, it needs to be converted from the 3.3V high level to the 1.8V low level by the bidirectional level conversion module 50 before being connected to the SENSOR0_HS pin of the SS928V100 chip to avoid burning out the pin. In some further preferred embodiments, such as Figure 5As shown, the circuit 12 with dual-channel MIPI image receiving function also includes a security module 60; the security module 60 is connected in series between the bidirectional level conversion module 50 and the external image sensor; the first signal terminal of the security module 60 is connected to the bidirectional level conversion module 50 and is used to receive the high-level clock signal and high-level data signal output by the bidirectional level conversion module 50; the second signal terminal of the security module 60 is connected to the reset signal output terminal of the vision processing unit 20 and is used to receive the reset signal output by the vision processing unit 20 and output the reset signal to the external image sensor.

[0048] As one embodiment of the bidirectional level conversion module 50, combined with Figure 4 and Figure 12 As shown, the bidirectional level conversion module 50 includes: a bidirectional level conversion chip, which is a TXS0102DCU chip and has a low-voltage side power supply pin (VCCA), a high-voltage side power supply pin (VCCB), a low-voltage side signal pin group (including A1 and A2), a high-voltage side signal pin group (including B1 and B2), an enable pin (OE), and a ground pin (GND); and pull-up resistors; the low-voltage side power supply pin and the enable pin are respectively connected to a first power supply network through pull-up resistors; the low-voltage side signal pin group is respectively connected to the I2C clock pin and the I2C data pin of the vision processing unit 20; the high-voltage side power supply pin is connected to a second power supply network, the voltage of the second power supply network being higher than that of the first power supply network; the high-voltage side signal pin group is respectively connected to a safety module 60, used to output the level-converted high-voltage I2C clock signal and high-voltage I2C data signal to the safety module 60; and the ground pin is grounded. In some embodiments, the voltage of the first power supply network is 1.8V, and the voltage of the second power supply network is 3.3V.

[0049] As one embodiment of security module 60, combined with Figure 5 and Figure 13As shown, the security module 60 includes: a security encryption chip of model LKT4304, a first current-limiting resistor, a second current-limiting resistor, a third current-limiting resistor, a pull-up resistor, and a filter capacitor; the power supply pin (VCC) of the security encryption chip is connected to a 3.3V power supply network, the ground pin (GND) is grounded, and the filter capacitor is connected in parallel between the power supply pin and ground; the first data pin (SDA) of the security encryption chip is connected to the 3.3V I2C data signal output by the bidirectional level conversion module 50 through the first current-limiting resistor, and the clock pin (SCL) of the security encryption chip is connected to the 3.3V I2C clock signal output by the bidirectional level conversion module 50 through the second current-limiting resistor; the reset pin (RSR) of the security encryption chip is connected to the 3.3V power supply network through the pull-up resistor and to the reset control pin of the vision processing unit 20 through the third current-limiting resistor. The B port of the TXS0102DCU chip is connected to the LKT4304 chip to exchange 3.3V high-level clock and data signals. The A port of the TXS0102DCU chip is connected to the SS928V100 chip; for example, the A port of the TXS0102DCU chip is connected to the SPI0_CSN / I2C3_SDA and SPI0_SDI / I2C3_SCL pins of the SS928V100 chip to provide signals to the SS928V100 chip. The SPI0_CSN / I2C3_SDA and SPI0_SDI / I2C3_SCL pins of the 28V100 chip provide a 1.8V low-level signal. The RST_LKT pin of the LKT4304 chip is connected to the programmable GPIO pin of the SS928V100 chip via a bidirectional level conversion module 50 or directly. The SS928V100 outputs a reset level signal through this pin, realizing hardware reset control of the LKT4304 security encryption chip. The LKT4304 chip not only provides a 3.3V high-level signal for the arthroscopic gyroscope, but also has an independent hardware reset function. When the gyroscope bus is stuck or communication is abnormal, the chip can be used to independently reset the gyroscope peripheral, quickly restoring communication without restarting the entire device, thus improving equipment stability.

[0050] Figures 14 to 15 An endoscope host according to a first embodiment of the present invention is schematically shown.

[0051] like Figure 15 As shown, the endoscope host includes: an optical endoscope interface and an electronic endoscope interface; and the aforementioned circuit 12 with dual-channel MIPI image receiving function; wherein, the optical endoscope interface 112 and the electronic endoscope interface 113 are respectively connected to the optical endoscope dedicated circuit channel 21 and the electronic endoscope dedicated circuit channel 22 of the vision processing unit 20 of the circuit 12 with dual-channel MIPI image receiving function.

[0052] In some preferred embodiments, such as Figure 15 As shown, the endoscope host includes a housing 11 and a circuit 12 with dual-channel MIPI image receiving function; wherein, the housing 11 is integrally formed or machined to form a first receiving cavity 111; the circuit 12 with dual-channel MIPI image receiving function is disposed in the first receiving cavity 111, and is connected to the optical endoscope interface 112 and the electronic endoscope interface 113 disposed on the housing 11; the circuit 12 with dual-channel MIPI image receiving function includes a power supply circuit module 121 and an image processing circuit module 122.

[0053] Since the circuit 12 of this utility model with dual-channel MIPI image receiving function can simultaneously connect the optical endoscope interface 112 and the electronic endoscope interface 113, the optical endoscope and the electronic endoscope can share a single endoscope host, thereby improving the integration of the equipment.

[0054] In some embodiments, such as Figure 15 As shown, the endoscope host also includes a cold light source module 1141 disposed in the first receiving cavity 111 and a cold light source interface 114 disposed on the housing 11 and connected to the cold light source module 1141; the cold light source module 1141 is electrically connected to the power supply circuit module 121 and is used to provide illumination for the external endoscope probe. In some embodiments, such as Figure 14 As shown, the endoscope host also includes a display screen 115 and a switch 116 disposed on the housing 11; the display screen 115 is electrically connected to the circuit 12 with dual-channel MIPI image receiving function, for real-time display of endoscope images and touch adjustment of device parameters.

[0055] In this invention, the connection or installation is a fixed connection unless otherwise specified. A fixed connection can be implemented as a detachable or non-detachable connection commonly used in the prior art. A detachable connection can be implemented using existing technologies, such as threaded connections or keyed connections. A non-detachable connection can also be implemented using existing technologies, such as welding or adhesive bonding.

[0056] The above descriptions are merely some embodiments of this utility model. For those skilled in the art, various modifications and improvements can be made without departing from the inventive concept of this utility model, and all such modifications and improvements fall within the protection scope of this utility model.

Claims

1. A circuit with dual-channel MIPI image receiving function, comprising a power supply noise suppression module, wherein the input terminal of the power supply noise suppression module is connected to an external power supply; characterized in that, Also includes: The vision processing unit is equipped with a dedicated circuit channel for optical endoscopes that can be connected to optical endoscopes, and a dedicated circuit channel for electronic endoscopes that can be connected to electronic endoscopes. A first analog power supply that is electrically connected only to the power supply terminal of the dedicated circuit channel for optical endoscopes; And a second analog power supply that is electrically connected only to the power supply terminal of the dedicated circuit channel for electronic endoscopes; The output of the power supply noise suppression module is connected to a common power supply node, which is connected to the input of the first analog power supply and the input of the second analog power supply, respectively, to filter out ripple noise introduced by the external power supply.

2. The circuit with dual-channel MIPI image receiving function according to claim 1, characterized in that, The dedicated circuit channel for the optical endoscope includes a first data transmission pin group and a first auxiliary control pin group; The first data transmission pin group includes a 4-lane MIPI differential clock pin and four differential data pins, all of which are connected to the MIPI_RX0 interface of the vision processing unit. The first auxiliary control pin group includes: a first independent sensor clock pin, a first line synchronization pin, a first frame synchronization pin, and a first sensor reset pin; each pin is used for the transmission of the corresponding signal.

3. The circuit with dual-channel MIPI image receiving function according to claim 1, characterized in that, The dedicated circuit channel for the electronic endoscope includes a second data transmission pin group and a second auxiliary control pin group. The second data transmission pin group includes a 2-lane MIPI differential clock pin and two differential data pins. The 2-lane MIPI differential clock pin and the two differential data pins are all connected to the MIPI_RX1 interface of the vision processing unit. The second auxiliary control pin group includes: a second independent sensor clock pin, a second line synchronization pin, a second frame synchronization pin, and a second sensor reset pin; each pin is used for the transmission of the corresponding signal.

4. The circuit with dual-channel MIPI image receiving function according to claim 1, characterized in that, The power supply noise suppression module includes isolation components and power supply filter capacitors; One end of the isolation element is connected to a 1.8V system power supply network, and the other end of the isolation element is connected to a common power supply node; The common power supply node is connected to the first analog power supply and the second analog power supply, respectively; One end of the power filter capacitor is connected to the common power supply node, and the other end of the power filter capacitor is grounded.

5. The circuit with dual-channel MIPI image receiving function according to claim 1, characterized in that, The vision processing unit also includes an auxiliary interface for connecting to an external image sensor; The auxiliary interface includes a sensor master clock output terminal, a sensor horizontal synchronization input terminal, a sensor vertical synchronization input terminal, a sensor reset output terminal, a first bus communication terminal, a second bus communication terminal, and a general digital input / output terminal; A first resistor is connected in series at the main clock output terminal of the sensor. The first bus communication terminal and the second bus communication terminal each include a data signal pin and a clock signal pin, and each of the data signal pins and each of the clock signal pins are respectively connected in series with a second resistor; The resistance values ​​of both the first resistor and the second resistor are 33Ω.

6. The circuit with dual-channel MIPI image receiving function according to claim 5, characterized in that, It also includes a bidirectional level conversion module, which is connected between the bus communication terminal of the auxiliary interface of the vision processing unit and an external image sensor; The bidirectional level conversion module is used to convert the first logic level on the bus communication terminal side to the second logic level on the external image sensor side, and to convert the second logic level on the external image sensor side to the first logic level on the bus communication terminal side. The first logic level is 1.8V, and the second logic level is higher than the first logic level.

7. The circuit with dual-channel MIPI image receiving function according to claim 6, characterized in that, It also includes a security module, which is connected in series between the bidirectional level conversion module and the external image sensor; The first signal terminal of the security module is connected to the bidirectional level conversion module and is used to receive the high-level clock signal and high-level data signal output by the bidirectional level conversion module. The second signal terminal of the security module is connected to the reset signal output terminal of the vision processing unit, and is used to receive the reset signal output by the vision processing unit and output the reset signal to the external image sensor.

8. The circuit with dual-channel MIPI image receiving function according to claim 7, characterized in that, The bidirectional level conversion module includes: A bidirectional level conversion chip, specifically the TXS0102DCU chip, features a low-voltage side power supply pin, a high-voltage side power supply pin, a low-voltage side signal pin group, a high-voltage side signal pin group, an enable pin, and a ground pin. And pull-up resistors; The low-voltage side power supply pin and the enable pin are respectively connected to the first power supply network through the pull-up resistor; The low-voltage side signal pin group is respectively connected to the I2C clock pin and the I2C data pin of the vision processing unit; The high-voltage side power supply pin is connected to a second power supply network, the voltage of which is higher than that of the first power supply network; The high-voltage side signal pin group is connected to the safety module respectively, and is used to output the high-voltage I2C clock signal and high-voltage I2C data signal after level conversion to the safety module; The grounding pin is grounded; and The security module includes: a security encryption chip of model LKT4304, a first current-limiting resistor, a second current-limiting resistor, a third current-limiting resistor, a pull-up resistor, and a filter capacitor; The power supply pin of the security encryption chip is connected to a 3.3V power supply network, the ground pin is grounded, and the filter capacitor is connected in parallel between the power supply pin and ground. The first data pin of the security encryption chip is connected to the 3.3V I2C data signal output by the bidirectional level conversion module via the first current-limiting resistor, and the clock pin of the security encryption chip is connected to the 3.3V I2C clock signal output by the bidirectional level conversion module via the second current-limiting resistor. The reset pin of the security encryption chip is connected to the 3.3V power supply network via the pull-up resistor, and is connected to the reset control pin of the vision processing unit via the third current-limiting resistor.

9. The circuit with dual-channel MIPI image receiving function according to any one of claims 1 to 8, characterized in that, The visual processing unit is an SS928V100 chip.

10. An endoscope main unit, comprising an optical endoscope interface and an electronic endoscope interface; characterized in that, It also includes the circuit with dual-channel MIPI image receiving function as described in any one of claims 1 to 9; The optical endoscope interface and the electronic endoscope interface are respectively connected to the optical endoscope dedicated circuit channel and the electronic endoscope dedicated circuit channel of the vision processing unit.

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