A signal driving circuit

Abstract

The utility model discloses a signal machine drive circuit, through setting power input circuit, a plurality of signal lamp drive circuit, main control circuit, address setting circuit and drive signal output circuit, main control circuit receives control signal control drive signal output circuit output drive strobe signal, and to address setting circuit output drive signal output circuit corresponding address code strobe signal, drive signal output circuit receives drive strobe signal drive a plurality of signal lamp drive circuit corresponding signal lamp point bright, address setting circuit and drive signal output circuit can accurate control low -voltage signal's output time sequence and logic, satisfy the various complex control requirement of traffic signal lamp, and staff need not directly contact high -voltage live part and contact low -voltage signal, reduced the occurrence of safety accident, also improved the working stability of system.

Description

Technical Field

[0001] This utility model belongs to the field of traffic signal technology, and in particular relates to a traffic signal drive circuit. Background Technology

[0002] Currently, traffic lights generally employ periodic programmable control technology, relying primarily on experience and historical statistical data to determine the on / off times of traffic lights. In existing road traffic light control systems, road traffic signal controllers (signal controllers) typically provide direct control of road traffic lights (signal lights), meaning each signal light requires independent wiring from the signal controller. With newly constructed roads becoming increasingly wider, the amount of cabling used is vast, resulting in a significant workload for construction and maintenance. However, maintenance of road traffic light control systems usually requires on-site operation by personnel, which poses a safety hazard of electric shock and reduces the efficiency of traffic light control system maintenance. Utility Model Content To address the aforementioned problems, this utility model provides a signal drive circuit that can precisely control the output timing and logic of low-voltage signals, thereby fulfilling various complex control requirements for traffic lights. Workers do not need to directly contact high-voltage live parts, reducing the occurrence of safety accidents and solving the problems mentioned in the background section.

[0003] To achieve the above objectives, the present invention adopts the following technical solution: This utility model provides a signal drive circuit, including a power input circuit, multiple signal light drive circuits, a main control circuit, an address setting circuit, and a drive signal output circuit. The address setting circuit, the drive signal output circuit, and the power input circuit are all connected to the main control circuit, and the multiple signal light drive circuits are connected to the drive signal output circuit. The drive signal output circuit includes a first latch and a second latch. The first latch includes a first drive signal input terminal and a first signal output terminal connected to the main control circuit. The second latch includes a second drive signal input terminal and a second signal output terminal connected to the main control circuit. The first signal output terminal and the second signal output terminal are connected to multiple signal light drive circuits. The main control circuit receives a control signal to control the drive signal output circuit to output a drive selection signal, and outputs an address code selection signal corresponding to the drive signal output circuit to the address setting circuit. The drive signal output circuit receives the drive selection signal to drive the corresponding signal lights in the multiple signal light drive circuits to light up.

[0004] As a preferred embodiment of the above technical solution, the signal drive circuit further includes a watchdog circuit connected to the main control circuit. The watchdog circuit is used to receive the pulse signal output by the main control circuit and output a reset signal to the main control circuit according to the pulse signal.

[0005] As a preferred embodiment of the above technical solution, the watchdog circuit includes a chip U4 of model MAX813. When chip U2 is working normally, it outputs a pulse signal to the sixth pin of chip U4 at regular intervals. When the system is powered on, powered off, or the supply voltage is reduced, the seventh pin of chip U4 outputs a reset signal to the reset pin of chip U2 to reset chip U2.

[0006] As a preferred embodiment of the above technical solution, the main control circuit includes a chip U2 of model AT89C2051. The first pin of chip U2 is a reset pin; the second and third pins of chip U2 are serial communication ports used to receive control signals from the preceding circuit; the twelfth to nineteenth pins of chip U2 are drive signal output terminals and address code detection terminals, and are connected to the address setting circuit, the first latch, and the second latch; the eighth and ninth pins of chip U2 are drive strobe signals for the first latch and the second latch, respectively; and the seventh pin of chip U2 is an RS485 transmit / receive enable signal.

[0007] As a preferred embodiment of the above technical solution, the address setting circuit includes a 74HC245 chip U5 and a DIP switch SW1. The DIP switch SW1 is connected to the chip U5. When the eleventh pin of the chip U2 outputs a low level to the nineteenth pin of the chip U5, the sixth to ninth pins of the chip U5 output the address code corresponding to the DIP switch to the chip U2.

[0008] As a preferred embodiment of the above technical solution, the second to ninth pins of the first latch are first drive signal input terminals, the second to ninth pins of the second latch are second drive signal input terminals, the twelfth to nineteenth pins of the first latch are first signal output terminals, and the twelfth to nineteenth pins of the second latch are second signal output terminals. The first latch includes a 74HC573 chip U1, and the second latch includes a 74HC573 chip U3.

[0009] As a preferred embodiment of the above technical solution, when the ENOUT1 pin of chip U1 is high, chip U1 receives the first byte drive signal output by chip U2 and outputs it from the first signal output terminal, the ENOUT1 pin of chip U1 becomes low, and the output signal of chip U1 is locked. When the ENOUT2 pin of chip U3 is high, chip U3 receives the second byte drive signal output by chip U2 and outputs it from the second signal output terminal. When the ENOUT2 pin of chip U2 goes low, the output signal of chip U3 is locked.

[0010] As a preferred embodiment of the above technical solution, each of the signal light driving circuits includes a signal light, multiple resistors, multiple capacitors, a varistor, an optocoupler, and a thyristor, with the signal light connected to both ends of the varistor.

[0011] As a preferred embodiment of the above technical solution, the optocoupler is model MOC3043.

[0012] As a preferred embodiment of the above technical solution, the power input circuit includes a fuse connected to the mains power input and multiple parallel capacitors.

[0013] Compared with the prior art, the beneficial effects of this utility model are as follows: By setting up a power input circuit, multiple traffic light driver circuits, a main control circuit, an address setting circuit, and a drive signal output circuit, the main control circuit receives control signals to control the drive signal output circuit to output drive selection signals, and outputs the address code selection signal corresponding to the drive signal output circuit to the address setting circuit. The drive signal output circuit receives the drive selection signals and drives the corresponding traffic lights in the multiple traffic light driver circuits to light up. The address setting circuit and the drive signal output circuit can accurately control the output timing and logic of low-voltage signals, meeting various complex control requirements of traffic lights. Workers do not need to directly contact high-voltage live parts but come into contact with low-voltage signals, reducing the occurrence of safety accidents and improving the working stability of the system. Attached Figure Description

[0014] Figure 1 This is a structural block diagram of the signal drive circuit proposed in this utility model; Figure 2 This is a circuit diagram of the main control circuit proposed in this utility model; Figure 3 A circuit diagram of the address setting circuit proposed in this utility model; Figure 4 This is a circuit diagram of the drive signal output circuit proposed in this utility model; Figure 5 The circuit diagram is shown for the watchdog circuit proposed in this utility model. Figure 6 This is a circuit diagram of the signal light driving circuit proposed in this utility model; Figure 7 This is a circuit diagram of the power input circuit proposed in this utility model; Figure 8 This is a circuit diagram of the data transmission circuit proposed in this utility model.

[0015] The symbols for the main components are explained below: 10-Power input circuit; 20-Indicator light drive circuit; 30-Main control circuit; 40-Address setting circuit; 50-Drive signal output circuit; 51-First latch; 52-Second latch; 60-Watchdog circuit. Detailed Implementation

[0016] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0017] See Figure 1 This utility model provides a signal drive circuit, including a power input circuit 10, multiple signal light drive circuits 20, a main control circuit 30, an address setting circuit 40, and a drive signal output circuit 50. The address setting circuit 40, the drive signal output circuit 50, and the power input circuit 10 are all connected to the main control circuit 30, and the multiple signal light drive circuits 20 are connected to the drive signal output circuit 50. The drive signal output circuit 50 includes a first latch 51 and a second latch 52. The first latch 51 includes a first drive signal input terminal and a first signal output terminal connected to the main control circuit 10. The second latch 52 includes a second drive signal input terminal and a second signal output terminal connected to the main control circuit. The first signal output terminal and the second signal output terminal are connected to a plurality of the signal light drive circuits 20. The main control circuit 30 receives a control signal to control the drive signal output circuit 50 to output a drive selection signal, and outputs the address code selection signal corresponding to the drive signal output circuit to the address setting circuit 40. The drive signal output circuit 50 receives the drive selection signal to drive the corresponding signal lights in the multiple signal light drive circuits 20 to light up.

[0018] In this embodiment, the signal drive circuit further includes a watchdog circuit 60 connected to the main control circuit 10. The watchdog circuit 60 receives pulse signals output by the main control circuit 30 and outputs a reset signal to the main control circuit 10 according to the pulse signals. The watchdog circuit 60 includes a MAX813 chip U4. When the chip U2 is working normally, it outputs pulse signals to the sixth pin of the chip U4 at regular intervals. When the system is powered on, powered off, or the supply voltage decreases, the seventh pin of the chip U4 outputs a reset signal to the reset pin of the chip U2 to reset the chip U2. The main control circuit 30 includes a chip U2 of model AT89C2051. The first pin of chip U2 is a reset pin; the second and third pins of chip U2 are serial communication ports used to receive control signals from the front-end circuit; the twelfth to nineteenth pins of chip U2 are drive signal output terminals and address code detection terminals, and are connected to the address setting circuit 40, the first latch 51 and the second latch 52; the eighth and ninth pins of chip U2 are drive strobe signals for the first latch 51 and the second latch 52, respectively; and the seventh pin of chip U2 is an RS485 transmit / receive enable signal.

[0019] It should be noted that the address setting circuit 40 includes a 74HC245 chip U5 and a DIP switch SW1. The DIP switch SW1 is connected to the chip U5. When the eleventh pin of the chip U2 outputs a low level to the nineteenth pin of the chip U5, the sixth to ninth pins of the chip U5 output the address code corresponding to the DIP switch to the chip U2. The second to ninth pins of the first latch 51 are the first drive signal input terminals, and the second to ninth pins of the second latch 52 are the second drive signal input terminals. The twelfth to nineteenth pins of the first latch 51 are the first signal output terminals, and the twelfth to nineteenth pins of the second latch 52 are the second signal output terminals. The first latch 51 includes a 74HC573 chip U1, and the second latch 52 includes a 74HC573 chip U3.

[0020] When the ENOUT1 pin of chip U1 is high, chip U1 receives the first byte drive signal output by chip U2 and outputs it from the first signal output terminal. The ENOUT1 pin of chip U1 then goes low, and the output signal of chip U1 is locked. Chip U3 receives the second byte drive signal output by chip U2 and outputs it from the second signal output terminal. The ENOUT2 pin of chip U2 then goes low, and the output signal of chip U3 is locked. Each of the signal light drive circuits 20 includes a signal light, multiple resistors, multiple capacitors, a varistor, an optocoupler, and a silicon controlled rectifier (SCR). The signal light is connected across the varistor. The optocoupler is a MOC3043. The power input circuit 10 includes a fuse connected to the mains input and multiple parallel capacitors.

[0021] Specifically, such as Figure 2 As shown, the main control circuit 10 includes chip U2, capacitors C23 and C24, and crystal oscillator Y1. Capacitors C23 and C24 are connected in parallel across crystal oscillator Y1 and connected to the fourth and fifth pins (XT2, XT1) of chip U2. The first pin of chip U2 is the reset pin (RST). The second pin (RXD) and the third pin (TXD) of chip U2 are serial communication ports used to receive control signals from the preceding circuit. The twelfth pin (P10) to the nineteenth pin (P17) of chip U2 are drive signal output terminals and address code detection terminals, which are connected to a chip U5 (74HC573) and two latches (U1, U3). The eighth pin (ENOUT1) and the ninth pin (ENOUT2) of chip U2 are strobe signals for the output of two drive signals. The eleventh pin (ENADDR) of chip U2 is the address code strobe signal, the sixth pin (WDI) is the watchdog signal (connected to chip U4), and the seventh pin (RT) is the RS485 receive / transmit enable signal.

[0022] Specifically, such as Figure 3 As shown, the signal controller has four driver boards, one each for the east, west, south, and north. The circuitry is identical, the difference being the address codes. The address codes are set using SW1, a four-position DIP switch. When SW1 is ON, the address is 1; when SW1 is OFF, the address is 0. The address codes for the four driver boards are set to 0001, 0010, 0100, and 1000, respectively. When pin 11 of the microcontroller (chip) U2 outputs a low level to pin 19 of chip U5, pins 6 to 9 of chip U5 output the address code to microcontroller U2.

[0023] Specifically, such as Figure 4As shown, chips U1 and U3 are latches used to receive and latch drive signals. Pins 2 to 9 of chip U1 are drive signal input pins (connected to chip U2). Microcontroller U2 outputs the drive signal in two steps, each time outputting one byte (8 bits), with the second output having 3 valid bits. When ENOUT1 is high, chip U1 receives the first byte of the drive signal and outputs it from pins 12 to 19. Then, ENOUT1 goes low, and chip U1's output signal is latched. When ENOUT2 is high, chip U3 receives the second byte of the drive signal and outputs it from pins 12 to 19. Then, ENOUT2 goes low, and chip U3's output signal is latched.

[0024] Specifically, such as Figure 5 As shown, the watchdog circuit 60 uses the MAX813 chip U4. When the system powers on, powers off, or the supply voltage decreases, the seventh pin of chip U4 outputs a reset signal to the reset pin (RST) of microcontroller U2, resetting the microcontroller. When microcontroller U2 is working normally, it outputs a pulse signal to the sixth pin (WDI) of chip U4 at regular intervals. When the microcontroller is interfered with or the program malfunctions due to other reasons, the sixth pin of chip U4 will not receive the pulse signal, and the eighth pin of chip U4 will output a low level. This level is applied to the first pin, causing the seventh pin to output a reset signal, resetting the microcontroller.

[0025] Specifically, such as Figure 6 As shown, the signal light driving circuit 20 includes an optocoupler M1, a light-emitting diode (LED) D1, resistors R1, R12, and R34, a varistor RV1, capacitors C1 and C12, and an external thyristor Q1. The anode of LED D1 is connected to one end of resistor R34, and the cathode of LED D1 is connected to chip U1 or chip U2. The other end of resistor R34 is connected to optocoupler M1. One end of resistor R23, thyristor Q1, and resistor R1 are all connected to optocoupler M1. The other end of resistor R1 is connected to thyristor Q1. One end of resistor R12 is connected to INL (live wire), and the other end of resistor R12 is connected to capacitor C1. The other end of resistor R23 is connected to one end of varistor RV1, capacitor C12, capacitor C1, and thyristor Q1. The other end of varistor RV1 is connected to INN (neutral wire) and capacitor C12. Figure 7 As shown, the power input circuit 10 includes multiple parallel capacitors and a fuse F1. The fuse is connected across INN and INL, and the multiple parallel capacitors (C25~C31) can filter the input voltage of the power input circuit.

[0026] The signal light driver circuit 20 has eleven identical circuits. Taking one circuit as an example, INN and INL are the power input circuits connected to the AC 220V neutral and live wires respectively; ZR and INN are connected to the signal light (D1). Normally, QD1 is high, the internal LED of optocoupler M1 (MOC3043) is off, and the internal phototransistor and SCR are also off, pin 4 is low, and the external SCR Q1 is also off. When QD1 is low, the internal LED of M1 conducts and emits light, and the internal phototransistor and SCR also conduct. The voltage on INL is applied to the control electrode of Q1 through R1 and the internal SCR of M1, turning Q1 on. This connects ZR and INL, illuminating the signal light connected to ZR and INN.

[0027] Specifically, such as Figure 8 As shown, the signal drive circuit also includes a data transmission circuit, which includes a chip U6 of model MAX485. The first pin (RXD), the third pin (RT), and the fourth pin (TXD) of chip U6 are connected to the second pin, the seventh pin, and the third pin of chip U2. The seventh pin and the sixth pin of chip U6 are connected to the fourth pin (TXB) and the third pin (TXA) of terminal JP1.

[0028] It should be noted that the power input circuit 10 is connected to AC 220V voltage and outputs DC 5V voltage to the main control circuit 30. The signal light drive circuit 20 is mainly connected to the neutral wire and the live wire (high voltage part), that is, the drive signal control part is the low voltage control part, and the high voltage working part is the signal drive circuit, that is, it uses DC 5V to drive the high voltage 220V. The signal drive circuit provided by this utility model has the following characteristics: High safety: The low-voltage control section and the high-voltage working section are electrically isolated by optocouplers, so that the staff only come into contact with low-voltage signals, reducing the risk of electric shock; for example, when performing system maintenance, the staff do not need to directly contact the high-voltage live parts, reducing the possibility of safety accidents. Precise control: The output timing and logic of low-voltage signals can be precisely controlled through programming and other means, thereby realizing various complex control requirements for traffic lights, such as adjusting the signal light timing scheme for different time periods and dynamically changing the signal light status according to traffic flow or pedestrian requests. Good stability: Low-voltage control circuits are less affected by external interference and can work more stably. In addition, low-voltage components usually have a longer lifespan, reducing the number of abnormal signal lights caused by control circuit failures.

[0029] It should be understood that by setting up a power input circuit 10, multiple traffic light drive circuits 20, a main control circuit 30, an address setting circuit 40, and a drive signal output circuit 50, the main control circuit 30 receives control signals to control the drive signal output circuit 50 to output drive selection signals, and outputs the address code selection signal corresponding to the drive signal output circuit 50 to the address setting circuit 40. The drive signal output circuit 50 receives the drive selection signals and drives the corresponding traffic lights in the multiple traffic light drive circuits 20 to light up. The address setting circuit 40 and the drive signal output circuit 50 can accurately control the output timing and logic of low-voltage signals, meeting various complex control requirements of traffic lights. Workers do not need to directly contact high-voltage live parts but come into contact with low-voltage signals, reducing the occurrence of safety accidents and improving the working stability of the system.

[0030] The above description is only a preferred embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the technical scope disclosed in the present utility model, based on the technical solution and the inventive concept of the present utility model, should be included within the protection scope of the present utility model.

Claims

1. A signal drive circuit, characterized in that, It includes a power input circuit, multiple signal light driving circuits, a main control circuit, an address setting circuit, and a drive signal output circuit. The address setting circuit, the drive signal output circuit, and the power input circuit are all connected to the main control circuit, and the multiple signal light driving circuits are connected to the drive signal output circuit. The drive signal output circuit includes a first latch and a second latch. The first latch includes a first drive signal input terminal and a first signal output terminal connected to the main control circuit. The second latch includes a second drive signal input terminal and a second signal output terminal connected to the main control circuit. The first signal output terminal and the second signal output terminal are connected to multiple signal light drive circuits. The main control circuit receives a control signal to control the drive signal output circuit to output a drive selection signal, and outputs an address code selection signal corresponding to the drive signal output circuit to the address setting circuit. The drive signal output circuit receives the drive selection signal to drive the corresponding signal lights in the multiple signal light drive circuits to light up.

2. The signal drive circuit according to claim 1, characterized in that, The signal drive circuit also includes a watchdog circuit connected to the main control circuit. The watchdog circuit is used to receive the pulse signal output by the main control circuit and output a reset signal to the main control circuit according to the pulse signal.

3. The signal drive circuit according to claim 2, characterized in that, The watchdog circuit includes a chip U4 of model MAX813. When chip U2 is working normally, it outputs a pulse signal to the sixth pin of chip U4 at regular intervals. When the system is powered on, powered off, or the supply voltage is reduced, the seventh pin of chip U4 outputs a reset signal to the reset pin of chip U2 to reset chip U2.

4. The signal drive circuit according to claim 2, characterized in that, The main control circuit includes a chip U2 of model AT89C2051. The first pin of chip U2 is a reset pin; the second and third pins of chip U2 are serial communication ports used to receive control signals from the front-end circuit; the twelfth to nineteenth pins of chip U2 are drive signal output terminals and address code detection terminals, and are connected to the address setting circuit, the first latch and the second latch; the eighth and ninth pins of chip U2 are drive strobe signals for the first latch and the second latch, respectively; and the seventh pin of chip U2 is an RS485 transmit / receive enable signal.

5. The signal drive circuit according to claim 4, characterized in that, The address setting circuit includes a 74HC245 chip U5 and a DIP switch SW1. The DIP switch SW1 is connected to the chip U5. When the eleventh pin of the chip U2 outputs a low level to the nineteenth pin of the chip U5, the sixth to ninth pins of the chip U5 output the address code corresponding to the DIP switch to the chip U2.

6. The signal drive circuit according to claim 1, characterized in that, The second to ninth pins of the first latch are the first drive signal input terminals, the second to ninth pins of the second latch are the second drive signal input terminals, the twelfth to nineteenth pins of the first latch are the first signal output terminals, and the twelfth to nineteenth pins of the second latch are the second signal output terminals. The first latch includes a 74HC573 chip U1, and the second latch includes a 74HC573 chip U3.

7. The signal drive circuit according to claim 6, characterized in that, When the ENOUT1 pin of chip U1 is high, chip U1 receives the first byte drive signal output by chip U2 and outputs it from the first signal output terminal. When the ENOUT1 pin of chip U1 goes low, the output signal of chip U1 is locked. When the ENOUT2 pin of chip U3 is high, chip U3 receives the second byte drive signal output by chip U2 and outputs it from the second signal output terminal. When the ENOUT2 pin of chip U2 goes low, the output signal of chip U3 is locked.

8. The signal drive circuit according to claim 1, characterized in that, Each of the aforementioned signal light drive circuits includes a signal light, multiple resistors, multiple capacitors, a varistor, an optocoupler, and a silicon controlled rectifier (SCR), with the signal light connected to both ends of the varistor.

9. The signal drive circuit according to claim 8, characterized in that, The optocoupler is model MOC3043.

10. The signal drive circuit according to claim 1, characterized in that, The power input circuit includes a fuse connected to the mains power input and multiple parallel capacitors.

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