A PCB board applied to a solid state disk

Abstract

The utility model discloses a kind of PCBs applied to solid state drive, the PCB is adapted M.2NVMe solid state drive, 4 layers, 6 layers or 8 layers, each layer is sequentially arranged along the thickness direction;When the number of layers is 4 layers: each layer is L1 layer, L2 layer, L3 layer, L4 layer respectively, L1 layer and L4 layer are signal trace layer;When the number of layers is 6 layers: each layer is L'1 layer, L'2 layer, L'3 layer, L'4 layer, L'5 layer, L'6 layer respectively;When the number of layers is 8 layers: each layer is L''1 layer, L''2 layer, L''3 layer, L''4 layer, L''5 layer, L''6 layer, L''7 layer, L''8 layer respectively;Electroplating via hole that penetrates the thickness direction of each layer, laser blind hole and non-electroplating via hole of connecting specified layer are equipped on the PCB, and main control chip and storage grain are integrated, reduce the number of layers and reduce cost, increase wiring area in combination with multiple type hole structure, shorten signal path and improve performance.

Description

Technical Field

[0001] This utility model relates to the field of PCB board technology, specifically to a PCB board for solid-state drives, which is compatible with PCIe 3.0 and PCIe 4.0 protocols of M.2 NVMe solid-state drives, and can also be compatible with PCIe 4.0 / 5.0 protocols. Background Technology

[0002] M.2 NVMe SSDs, utilizing PCIe channels and the NVMe protocol, offer read and write speeds far exceeding traditional SATA SSDs, making them the mainstream storage solution. However, existing M.2 NVMe SSD PCB designs suffer from the following key issues: Excessive number of layers leads to high costs: To meet the signal transmission and electromagnetic compatibility requirements of the PCIe 3.0 / 4.0 protocol, traditional PCB boards mostly adopt a 6-layer (PCIe 3.0) or 8-layer (PCIe 4.0) structure; the conventional design for the PCIe 4.0 / 5.0 protocol even adopts a 10-layer through-hole structure, resulting in a large amount of copper foil and insulating materials, complex manufacturing processes (such as multi-layer lamination and multiple drilling), and high material and processing costs; Crowded wiring and difficult layout: Traditional PCB boards rely on "through-hole" to achieve interlayer connection. Through-hole occupies a lot of wiring space. However, the main control chip and memory chip have high pin density (such as the main control chip having more than 200 pins), which easily leads to wiring conflicts. Signal path length must be sacrificed to avoid through-hole, resulting in increased signal delay. In 10-layer board structures, the problem of through-hole occupancy is even more prominent, further compressing the wiring space. Utility Model Content

[0003] The purpose of this invention is to provide a PCB board for solid-state drives (SSDs) to solve the technical problems of existing SSD PCB boards having many layers, high cost, and crowded wiring, while adapting to the high-end requirements of PCIe 4.0 / 5.0 protocols.

[0004] To achieve the above objectives, this utility model provides the following technical solution: A PCB board for use in solid-state drives (SSDs), the PCB board is compatible with M.2 NVMe SSDs, the PCB board has 4, 6 or 8 layers, and the layers are arranged sequentially along the thickness direction.

[0005] When there are 4 layers: the layers are L1, L2, L3 and L4, L1 and L4 are signal routing layers, L2 is the ground / power layer and L3 is the signal / ground / power layer.

[0006] When there are 6 layers: the layers are L′1, L′2, L′3, L′4, L′5, and L′6. Layers L′1, L′3, L′4, and L′6 are signal routing layers, and layers L′2 and L′5 are ground / power layers.

[0007] When there are 8 layers: the layers are L′′1, L′′2, L′′3, L′′4, L′′5, L′′6, L′′7, and L′′8. Layers L′′1, L′′3, L′′4, L′′6, and L′′8 are signal routing layers, while layers L′′2, L′′5, and L′′7 are ground / power layers. Furthermore, layers L′′2, L′′5, and L′′7 can be used to locally route signal traces according to actual wiring requirements. The standard size of this 8-layer PCB is 80*22mm.

[0008] As a further embodiment of this utility model, the PCB board is provided with electroplated through holes that penetrate the thickness direction of each layer.

[0009] As a further embodiment of this utility model, the PCB board is provided with L1-L2 laser blind holes connecting the L1 layer and the L2 layer; As a further preferred embodiment of this utility model, when the number of layers is 4, the PCB board is provided with L3-L4 laser blind vias connecting the L3 and L4 layers; when the number of layers is 6, the PCB board is provided with L′5-L′6 laser blind vias connecting the L′5 and L′6 layers; when the number of layers is 8, the PCB board is provided with L′′7-L′′8 laser blind vias connecting the L′′7 and L′′8 layers, so as to realize the effective connection between each signal trace layer and the ground / power layer.

[0010] As a further embodiment of this utility model, when the number of layers is 4, the PCB board is provided with L2-L3 unplated through holes penetrating the L2 and L3 layers; when the number of layers is 6, the PCB board is provided with L′2-L′5 unplated through holes penetrating the L′2 and L′5 layers; when the number of layers is 8, the PCB board can selectively provide L′′2-L′′7 unplated through holes penetrating the L′′2 and L′′7 layers, further optimizing the interlayer connection path and reducing wiring conflicts.

[0011] The above solution reduces the number of PCB layers from the traditional 6, 8, and 10 layers to 4, 6, or 8 layers, reducing the amount of copper foil and insulating materials used, and lowering material and processing costs. By combining "electroplated through-holes + laser blind holes + non-electroplated through-holes", the number of layers is reduced while avoiding wiring congestion, ensuring the high-speed signal transmission requirements of M.2 NVMe solid-state drives and adapting to the read and write characteristics of PCIe 3.0 / 4.0 / 5.0 protocols.

[0012] As a preferred embodiment of this utility model, the main control chip and storage particles of the solid-state drive are soldered on the L1 layer, L′1 layer, or L′′1 layer. The signal pins of the main control chip are electrically connected to the laser blind hole and the electroplated through hole through the signal traces of the L1 layer or L′1 layer, respectively. The signal pins of the storage particles are electrically connected to the signal pins of the main control chip through the signal traces of the L1 layer or L′1 layer.

[0013] The above solution centrally places the main control chip and memory chips on the L1, L′1, or L′′1 layer, simplifying the SMT assembly process, shortening the signal transmission path between the two and the via structure, and reducing signal delay (signal delay is significantly reduced compared to the dispersed component layout); at the same time, it facilitates later fault detection and maintenance, improving production and after-sales efficiency; in the 8-layer structure, the centralized layout can also be combined with the multi-signal routing layer design of L′′1, L′′3, L′′4, L′′6, and L′′8 to further optimize the transmission stability of high-speed signals and adapt to the high bandwidth requirements of the PCIe 5.0 protocol.

[0014] Compared with existing technologies, the PCB board for solid-state drives provided by this utility model has the following advantages: 1. Cost advantage: Compared with traditional multilayer PCBs (PCIe 3.0 corresponds to 6 layers, PCIe 4.0 corresponds to 8 layers, and PCIe 4.0 / 5.0 corresponds to 10 layers), this utility model significantly reduces the overall cost by optimizing the number of layers, reducing material usage and manufacturing processes.

[0015] 2. Performance advantages: Multi-type hole structure and centralized component layout shorten signal transmission path, reduce latency and loss, ensure high-speed data transmission under PCIe 3.0 / 4.0 and PCIe 4.0 / 5.0 protocols, and are suitable for high-performance scenarios such as high-end games, 4K video editing, database processing, professional workstations and servers; 3. Compatibility advantages: It can directly connect to mainstream devices and operating systems without additional drivers or structural modifications, making it easy for users to use; the 8-layer structure can also accommodate the protocol upgrade requirements from PCIe 4.0 to PCIe 5.0, extending the product life cycle; 4. Reliability advantages: Reasonable material selection improves insulation, heat dissipation and structural strength, reduces the risk of failure during high-speed operation, extends service life, simplifies maintenance process and reduces after-sales costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only examples of embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the 4-layer PCB board in Embodiment 1 of this utility model; Figure 2 This is a schematic diagram of the structure of the 6-layer PCB board in Embodiment 2 of this utility model; Figure 3 This is a schematic diagram of the structure of an 8-layer PCB board according to Embodiment 2 of this utility model.

[0018] Figure label: 11-L1 floor, 12-L2 floor, 13-L3 floor, 14-L4 floor; Layer 21-L′1, Layer 22-L′2, Layer 23-L′3, Layer 24-L′4; Layer 25-L′5; Layer 26-L′6; Layer 31-L′′1, Layer 32-L′′2, Layer 32-L′′3, Layer 34-L′′4, Layer 35-L′′-5, Layer 36-L′′31-6, Layer 37-L′′7, Layer 38-L′′8. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0020] In the description of the embodiments of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention.

[0021] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an integral connection, or a detachable connection; they can refer to the internal connection of two components; they can refer to a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present invention should be understood according to the specific circumstances.

[0022] To make the technical solution of this utility model clearer, the following detailed description is provided in conjunction with specific embodiments: Example 1: See Figure 1 The 4-layer PCB board shown is compatible with the PCIe 3.0 protocol: Layer structure: Layer stacking order (from top to bottom): L1 layer 11 (signal trace layer) → PP insulation layer → L2 layer 12 (ground / power layer) → FR-4 core board → L3 layer 13 (signal / ground / power layer) → PP insulation layer → L4 layer 14 (signal trace layer).

[0023] Hole structure: L1-L4 electroplated through holes: to achieve conductivity; L1-L2 laser blind vias: connect the signal trace on layer 11 of L1 layer to the ground / power supply on layer 12 of L2 layer; L3-L4 laser blind aperture: connects L3 layer 13 and L4 layer 14; L2-L3 are unplated through holes.

[0024] The above-mentioned hole structure can be combined in several ways: Combination 1: L1-L4 are electroplated through holes, L1-L2 are laser-drilled blind holes, L3-L4 are laser-drilled blind holes, and L2-L3 are unplated through holes; Combination 2: L1-L4 are electroplated through holes, and L1-L2 are laser-drilled blind holes; Combination 3: L1-L4 are electroplated through holes, L1-L2 are laser-plated blind holes, and L3-L4 are laser-plated blind holes; Combination 4: L1-L4 are electroplated through holes, and L3-L4 are laser-drilled blind holes; Combination 5: L1-L4 are electroplated through holes, L1-L2 are laser-drilled blind holes, and L2-L3 are unplated through holes; Combination 6: L1-L4 are electroplated through holes, L3-L4 are laser-drilled blind holes, and L2-L3 are unplated through holes.

[0025] Example 2: See Figure 2 The 6-layer PCB board shown is compatible with this board. Layer structure: Layer stacking order (from top to bottom): L′1 layer 21 (signal trace layer) → PP insulation layer → L′2 layer 22 (grounding / power layer) → FR-4 core board → L′3 layer 23 (signal trace layer) → PP insulation layer → L′4 layer 24 (signal trace layer) → FR-4 core board → L′5 layer 25 (grounding / power layer) → PP insulation layer → L′6 layer 26 (signal trace layer).

[0026] Hole structure: L′1-L′6 are electroplated through holes; L′1-L′2 and L′5-L′6 are laser blind holes; L′2-L′5 are unplated through holes.

[0027] The above-mentioned hole structure can be combined in several ways: Combination 1: L′1-L′6 are electroplated through holes, L′1-L′2 are laser-drilled blind holes, L′5-L′6 are laser-drilled blind holes, and L′2-L′5 are unplated through holes; Combination 2: L′1-L′6 are electroplated through holes, and L′1-L′2 are laser-drilled blind holes; Combination 3: L′1-L′6 are electroplated through holes, L′1-L′2 are laser-plated blind holes, and L′5-L′6 are laser-plated blind holes; Combination 4: L′1-L′6 are electroplated through holes, and L′5-L′6 are laser-drilled blind holes; Combination 5: L′1-L′6 are electroplated through holes, L′1-L′2 are laser-drilled blind holes, and L′2-L′5 are unplated through holes; Combination 6: L′1-L′6 are electroplated through holes, L′5-L′6 are laser-drilled blind holes, and L′2-L′5 are unplated through holes.

[0028] Example 3: Reference Figure 3 As shown, the 8-layer PCB board is compatible with the protocol. Layer structure: Stacking order (from top to bottom): L′′1 layer (signal trace layer) → PP insulation layer → L′′2 layer (ground / power layer, partial routing allowed) → FR-4 core board → L′′3 layer (signal trace layer) → PP insulation layer → L′′4 layer (signal trace layer) → FR-4 core board → L′′5 layer (ground / power layer, partial routing allowed) → PP insulation layer → L′′6 layer (foil signal trace layer) → FR-4 core board → L′′7 layer (ground / power layer, partial routing allowed) → PP insulation layer → L′′8 layer (signal trace layer).

[0029] Hole Structure: The basic hole structure includes 1-8 plated through-holes (penetrating layers L′′1-L′′8 to achieve full-layer conductivity), L′′1-L′′2 laser-drilled blind vias (connecting the L′′1 signal trace layer and the L′′2 ground / power layer), L′′7-L′′8 laser-drilled blind vias (connecting the L′′7 ground / power layer and the L′′8 signal trace layer), and L′′2-L′′7 unplated through-holes (penetrating layers L′′2 and L′′7 to optimize specific inter-layer connections). The above-mentioned hole structure can be combined in several ways: Combination 1: L′′1-L′′8 are electroplated through holes, L′′1-L′′2 are laser-drilled blind holes, L′′7-L′′8 are laser-drilled blind holes, and L′′2-L′′7 are unplated through holes; Combination 2: L′′1-L′′8 are electroplated through holes, and L′′1-L′′2 are laser-drilled blind holes; Combination 3: L′′1-L′′8 are electroplated through holes, L′′1-L′′2 are laser-plated blind holes, and L′′7-L′′8 are laser-plated blind holes; Combination 4: L′′1-L′′8 are electroplated through holes, and L′′7-L′′8 are laser-drilled blind holes; Combination 5: L′′1-L′′8 are electroplated through holes, L′′1-L′′2 are laser-drilled blind holes, and L′′2-L′′7 are unplated through holes; Combination 6: L′′1-L′′8 are electroplated through holes, L′′7-L′′8 are laser-drilled blind holes, and L′′2-L′′7 are unplated through holes.

[0030] Implementation Results: The traditional 10-layer PCIe 4.0 / 5.0 board is reduced to 8 layers, reducing the amount of 2 insulating core boards (FR-4) and insulating layers (PP), thus reducing material costs by approximately 20%. By replacing some of the 1-8 through-holes with laser-drilled blind vias L′′1-L′′2 and L′′7-L′′8, the wiring area is increased by approximately 15%, avoiding wiring conflicts. The unplated through-holes L′′2-L′′7 further optimize inter-layer connections, ensuring that the high-speed signal transmission delay under the PCIe 5.0 protocol is controlled within 5ns, meeting the performance requirements of high-end storage scenarios.

[0031] Overall technical effect: 1. Cost advantage: Compared with traditional multilayer PCBs (PCIe 3.0 corresponds to 6 layers, PCIe 4.0 corresponds to 8 layers, and PCIe 4.0 / 5.0 corresponds to 10 layers), this utility model significantly reduces the overall cost by optimizing the number of layers, reducing material usage and manufacturing processes.

[0032] 2. Performance advantages: Multi-type hole structure and centralized component layout shorten signal transmission path, reduce latency and loss, ensure high-speed data transmission under PCIe 3.0 / 4.0 and PCIe 4.0 / 5.0 protocols, and are suitable for high-performance scenarios such as high-end games, 4K video editing, database processing, professional workstations and servers; 3. Compatibility advantages: It can directly connect to mainstream devices and operating systems without additional drivers or structural modifications, making it easy for users to use; the 8-layer structure can also accommodate the protocol upgrade requirements from PCIe 4.0 to PCIe 5.0, extending the product life cycle; 4. Reliability advantages: Reasonable material selection improves insulation, heat dissipation and structural strength, reduces the risk of failure during high-speed operation, extends service life, simplifies maintenance process and reduces after-sales costs.

[0033] The foregoing has shown and described the basic principles of the present invention. The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. The above embodiments and descriptions in the specification are only illustrative of the principles of the present invention. Any modifications, equivalent substitutions, and improvements made within the scope of the present invention without departing from the scope of the present invention should be included within the protection scope of the present invention.

Claims

1. A PCB board for use in solid-state drives, characterized in that: The PCB board has 4, 6, or 8 layers, with each layer arranged sequentially along the thickness direction; When there are 4 layers: each layer is L1, L2, L3, and L4, where L1 and L4 are signal routing layers, L2 is a ground / power layer, and L3 is a signal / ground / power layer. When there are 6 layers: each layer is L′1, L′2, L′3, L′4, L′5, and L′6. Layers L′1, L′3, L′4, and L′6 are signal routing layers, and layers L′2 and L′5 are ground / power layers. When there are 8 layers: the layers are L′′1, L′′2, L′′3, L′′4, L′′5, L′′6, L′′7, and L′′8. The L′′1, L′′3, L′′4, L′′6, and L′′8 layers are signal routing layers, and the L′′2, L′′5, and L′′7 layers are ground / power layers. Signal routing can be set locally on the L′′2, L′′5, and L′′7 layers.

2. The PCB board for solid-state drives according to claim 1, characterized in that: The PCB board has electroplated through holes that penetrate the thickness direction of each layer.

3. A PCB board for use in solid-state drives according to claim 2, characterized in that: The PCB board is provided with L1-L2 laser blind vias that connect the L1 layer and the L2 layer.

4. A PCB board for use in solid-state drives according to claim 2 or 3, characterized in that: When there are 4 layers, the PCB board is selectively provided with L3-L4 laser blind vias connecting L3 and L4 layers; when there are 6 layers, the PCB board is selectively provided with L′5-L′6 laser blind vias connecting L′5 and L′6 layers; when there are 8 layers, the PCB board is selectively provided with L′′7L′′8 laser blind vias connecting L′′7 and L′′8 layers.

5. A PCB board for use in solid-state drives according to claim 4, characterized in that: When there are 4 layers, the PCB board is selectively provided with L2-L3 unplated through holes penetrating L2 and L3 layers; when there are 6 layers, the PCB board is selectively provided with L′2-L′5 unplated through holes penetrating L′2 and L′5 layers; when there are 8 layers, the PCB board is selectively provided with L′′2-L′′7 unplated through holes penetrating L′′2 and L′′7 layers.

6. A PCB board for use in solid-state drives according to claim 2, characterized in that: When the number of layers is 4, the PCB board is selectively provided with L2-L3 unplated through holes penetrating the L2 and L3 layers; when the number of layers is 6, the PCB board is selectively provided with L′2-L′5 unplated through holes penetrating the L′2 and L′5 layers; when the number of layers is 8, the PCB board is selectively provided with L′′2-L′′7 unplated through holes penetrating the L′′2 and L′′7 layers.

7. A PCB board for use in solid-state drives according to claim 1, characterized in that: The L1 layer, L′1 layer, and L′′1 layer are all equipped with a solid-state drive controller chip and storage particles. The signal pins of the controller chip are electrically connected to laser blind holes and electroplated through holes through signal traces in the L1 layer or L′1 layer, respectively. The signal pins of the storage particles are electrically connected to the signal pins of the controller chip through signal traces in the L1 layer or L′1 layer.

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