Circuit board

Abstract

The application discloses a circuit board, comprising a board body, a chip and a crystal oscillator, the board body comprises a first board surface and a copper foil layer covering the first board surface, the copper foil layer is provided with an isolation groove, a part of the first board surface located in the isolation groove is exposed via the isolation groove, the isolation groove is enclosed to form an isolation area, and the copper foil layer comprises a first covering part located in the isolation area; the chip is arranged on the board body, the chip is located outside the isolation area, and is electrically connected with a part of the copper foil layer located outside the isolation area; the crystal oscillator is located in the isolation area, and the crystal oscillator is electrically connected with the first covering part and the chip. According to the embodiment, the isolation groove is formed by removing part of the copper foil layer to form the isolation area, the propagation path of electromagnetic interference is blocked, the anti-radiation interference capability of the circuit board is improved, and the reliability is improved.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more particularly to a circuit board. Background Technology

[0002] Clock crystals typically refer to crystal oscillators, which utilize the piezoelectric effect of quartz crystals to generate stable frequency signals. When a crystal is placed in an electric field, it vibrates mechanically, producing an alternating electric field that forms the clock signal. Clock crystals are the core clock source in electronic systems, and their frequency stability and relative noise performance are crucial. With increasing integration and operating frequencies in electronic devices, the electromagnetic environment becomes increasingly complex. Electromagnetic interference from within the system or from the external environment can couple into the clock crystal circuit, causing frequency drift, increased jitter, or even cessation of oscillation, severely impacting system performance. Utility Model Content

[0003] This application provides a circuit board that can improve the circuit board's resistance to radiation interference and increase its reliability.

[0004] This application provides a circuit board, including: The board includes a first board surface and a copper foil layer covering the first board surface. The copper foil layer is provided with isolation grooves. The portion of the first board surface located in the isolation grooves is exposed through the isolation grooves. The isolation grooves enclose an isolation area. The copper foil layer includes a first covering portion located within the isolation area. A chip is disposed on the board, the chip is located outside the isolation area, and is electrically connected to the portion of the copper foil layer located outside the isolation area; A crystal oscillator is located in the isolation region, and the crystal oscillator is electrically connected to both the first cover portion and the chip.

[0005] In some embodiments of this application, an insulating filling layer is provided in the isolation trench.

[0006] In some embodiments of this application, the isolation trench is arranged in a ring around the crystal oscillator, and the circuit board is provided with conductive connection lines that cross the isolation area. The crystal oscillator and the chip are electrically connected through the conductive connection lines.

[0007] In some embodiments of this application, the first cover portion is provided with a plurality of vias, the vias penetrating the plate body and the first cover portion, and the plurality of vias are arranged at intervals along the outer periphery of the crystal oscillator.

[0008] In some embodiments of this application, at least two load capacitors are provided on the first cover portion, and the load capacitors are electrically connected to the crystal oscillator and the chip.

[0009] In some embodiments of this application, a plurality of the vias are arranged at intervals along the outer periphery of the crystal oscillator and the load capacitor.

[0010] In some embodiments of this application, the load capacitor is located between the crystal oscillator and the chip.

[0011] In some embodiments of this application, the plate body further has an insulating layer that covers at least a portion of the first covering portion, and the ground terminal of the load capacitor is connected to the insulating layer.

[0012] In some embodiments of this application, the vias and the isolation trenches are spaced apart, and the shortest interval between each via and the isolation trench is the same.

[0013] In some embodiments of this application, the width of the isolation trench is greater than 0.5 mm.

[0014] In some embodiments of this application, the board body further includes a dielectric layer and a trace layer, wherein the copper foil layer, the dielectric layer and the trace layer are stacked sequentially, and the side of the dielectric layer facing the copper foil layer is the first board surface.

[0015] Based on the circuit board in this embodiment, this embodiment removes part of the copper foil layer to form an isolation area by setting isolation trenches, thereby blocking the propagation path of electromagnetic interference, preventing high-frequency signals in the isolation area from spreading to the outside of the isolation area and interfering with other circuits, and preventing external high-frequency noise interference from directly coupling to the crystal oscillator through the plane, thereby improving the clock signal stability and anti-interference capability of the crystal oscillator. Therefore, this embodiment can reduce costs and improve the anti-radiation interference capability of the circuit board, thereby ensuring the reliable operation of the circuit board system in a high-density, high-frequency working environment. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the circuit board structure in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a portion of the circuit board in one embodiment of this application; Figure 3 This is a schematic diagram of the circuit board structure in another embodiment of this application.

[0018] Figure label: 100. Circuit board; 10. Board body; 11. First board surface; 12. Copper foil layer; 121. First cover; 13. Isolation trench; 131. Isolation area; 14. Via; 15. Insulating layer; 16. Dielectric layer; 17. Tracing layer; 20. Chips; 30. Crystal oscillator; 40. Load capacitance; 50. Conductive connecting wire. Detailed Implementation

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, a clear and complete description will be provided below with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] Clock crystals are the core clock source in electronic systems, and their frequency stability and relative noise performance are crucial. In related technologies, as the integration of electronic devices increases and the operating frequency rises, the electromagnetic environment becomes increasingly complex. Electromagnetic radiation interference from the internal or external environment of the system can couple into the clock crystal circuit, causing the clock crystal to drift, increase relative jitter, or even stop oscillating, which seriously affects the system performance.

[0021] For the above situation, please refer to Figures 1-2 This application proposes a circuit board 100, including a board body 10, a chip 20 and a crystal oscillator 30. The chip 20 and the crystal oscillator 30 are both disposed on the board body 10 and are electrically connected to each other through wiring.

[0022] The board body 10 includes a first board surface 11 and a copper foil layer 12 covering the first board surface 11. An isolation trench 13 is provided on the copper foil layer 12. The portion of the first board surface 11 located in the isolation trench 13 is exposed through the isolation trench 13. The isolation trench 13 encloses and forms an isolation region 131. The copper foil layer 12 includes a first covering portion 121 located within the isolation region 131. A chip 20 is disposed on the board body 10. The chip 20 is located outside the isolation region 131 and is electrically connected to the portion of the copper foil layer 12 located outside the isolation region 131. A crystal oscillator 30 is located in the isolation region 131. The crystal oscillator 30 is electrically connected to both the first covering portion 121 and the chip 20.

[0023] Specifically, the first board surface 11 can be exposed from the isolation trench 13. That is, a portion of the copper foil layer 12 is removed to form the isolation trench 13. The isolation trench 13 is a continuous and closed annular structure that completely surrounds the area where the crystal oscillator 30 is located. The depth of the isolation trench 13 extends through the copper foil layer 12 to the first board surface 11, exposing the first board surface 11. This physically isolates the first covering portion 121 within the isolation area 131 from the copper foil layer 12 in other areas of the board 10, and also electrically isolates the crystal oscillator 30 from other high-noise circuits, thereby blocking the conduction path of electromagnetic interference. An insulating layer 15 is provided on the copper foil layer 12 to cover areas of the copper foil layer 12 that are not electrically connected, thereby preventing the copper foil layer 12 from being oxidized or short-circuited. Figures 1-2 In the middle, the area filled with 45° diagonal lines is the insulating layer 15, the blank area is the copper foil layer 12, the area filled with vertical diagonal lines is the isolation trench 13, and the surface exposed through the isolation trench 13 is the first board surface 11.

[0024] It should be noted that in related technologies, a metal shield is usually placed on the circuit board 100 to cover the clock crystal to suppress electromagnetic interference. However, this method not only increases assembly processes and material costs, but also increases the size and weight of the circuit board 100, affects heat dissipation, and is not conducive to the miniaturization design of the circuit board 100. In this embodiment, by removing part of the copper foil layer 12 to set an isolation trench 13 to form an electromagnetic isolation region 131, that is, the isolation region 131 surrounded by the isolation trench 13 can form a physical isolation boundary on the surface of the circuit board 100, thereby constructing an electromagnetic isolation barrier. The structure of setting the isolation trench 13 on the copper foil layer 12 achieves shielding of the crystal oscillator 30 without the need to add an additional shield, simplifying the process, reducing costs, and improving the integration of the circuit board 100.

[0025] It should also be noted that the isolation trench 13 in this embodiment can block the propagation path of electromagnetic interference, confining high-frequency interference within the isolation area 131 to form a local loop. This prevents high-frequency signals within the isolation area 131 from spreading outside and interfering with other circuits. Simultaneously, it prevents external high-frequency noise interference from directly coupling to the crystal oscillator 30 via planar coupling, improving the clock signal stability and anti-interference capability of the crystal oscillator 30. This is suitable for applications in high-density, high-performance electronic devices. Therefore, this embodiment can improve the radiation interference resistance of the circuit board 100 without adding additional components, thereby ensuring the reliable operation of the circuit board 100 system in high-density, high-frequency operating environments.

[0026] Furthermore, the width of the isolation trench 13 can be optimized according to the actual electromagnetic shielding requirements. If the width of the isolation trench 13 is too small, it may not be able to effectively block the coupling path of high-frequency signals, resulting in a decrease in shielding effect. On the other hand, the larger the width of the isolation trench 13, the more significant the restriction effect on interference signals. Preferably, the width of the isolation trench 13 is greater than 0.5 mm to ensure effective blocking of interference coupling of high-frequency signals.

[0027] Please see Figure 3 In some embodiments of this application, the board body 10 further includes a dielectric layer 16 and a wiring layer 17. The copper foil layer 12, the dielectric layer 16 and the wiring layer 17 are stacked in sequence, and the side of the dielectric layer 16 facing the copper foil layer 12 is the first board surface 11.

[0028] Specifically, the dielectric layer 16 serves as an insulating material between the copper foil layer 12 and the wiring layer 17, providing stable dielectric properties and effectively reducing interlayer signal crosstalk. The wiring layer 17 can be used to lay wires for signal transmission, enabling signal interconnection and electrical connection of functional modules. Furthermore, the wires in the wiring layer 17 can be laid out in multiple layers according to circuit design requirements. The crystal oscillator 30 is located on the first cover portion 121, with the first plate surface 11 below it. In other words, the dielectric layer 16 below the first cover portion 121 acts as a complete ground plane, providing a stable reference potential plane for the crystal oscillator 30.

[0029] In some embodiments, the isolation trench 13 is not filled with copper foil, which can form a high-impedance region of air medium. Since the dielectric constant of air is much lower than that of copper foil, electromagnetic signals will encounter obvious impedance discontinuities when passing through the isolation trench 13, thereby reflecting most of the energy, reducing cross-regional coupling, and enhancing the ability to suppress electromagnetic wave propagation.

[0030] Alternatively, in some embodiments of this application, an insulating filling layer (not shown in the figure) is provided in the isolation trench 13. It is understood that the insulating filling layer is a non-conductive medium, such as solder resist ink, epoxy resin or ceramic material, which, when filled inside the isolation trench 13, can further enhance the insulation performance of the isolation trench 13 and enhance the electromagnetic isolation effect of the isolation trench 13, thereby confining high-frequency interference within the isolation region 131 to form a local loop and preventing it from spreading outside the isolation region 131 and contaminating other circuits.

[0031] Please see Figures 1-2 In some embodiments of this application, an isolation trench 13 is arranged around the crystal oscillator 30, and a conductive connection line 50 is provided on the circuit board 100 that crosses the isolation region 131. The crystal oscillator 30 and the chip 20 are electrically connected through the conductive connection line 50.

[0032] Specifically, the isolation trench 13 forms a completely enclosed isolation zone 131, completely surrounding the area where the crystal oscillator 30 is located, thereby effectively blocking the propagation path of high-frequency noise inside and outside the isolation zone 131 and improving the shielding effectiveness of the crystal oscillator 30. The chip 20 has multiple terminals, and the conductive connecting lines 50 are electrically connected to the pins of the crystal oscillator 30 through the terminals of the chip 20. Each conductive connecting line 50 maintains a minimized crossing angle when crossing the isolation trench 13 to reduce electromagnetic coupling effects.

[0033] It should be noted that the conductive connection line 50 should be as short, straight and wide as possible when it is laid out to reduce the line impedance and reduce the radiation coupling of high frequency signals. Therefore, it is preferable to place the crystal oscillator 30 in the isolation area 131 close to the chip 20. The smaller the distance between the crystal oscillator 30 and the chip 20, the shorter the length of the conductive connection line 50, the lower the signal transmission delay, and the shorter the electromagnetic interference path, which is beneficial to improving the system timing accuracy and noise immunity.

[0034] Please see Figure 2 In some embodiments of this application, at least two load capacitors 40 are provided on the first cover portion 121, and the load capacitors 40 are electrically connected to the crystal oscillator 30 and the chip 20.

[0035] Specifically, two load capacitors 40 are connected between the two pins of the crystal oscillator 30 and ground, respectively. They primarily affect the load resonant frequency and the equivalent load resonant resistance, ensuring that the equivalent capacitance across the crystal oscillator 30 is close to the nominal value of the load capacitors 40. This guarantees the stability and accuracy of the crystal oscillator 30's oscillation frequency. The load capacitors 40 are positioned as close as possible to the crystal oscillator 30 to shorten trace lengths, reduce the influence of parasitic inductance and stray capacitance, and further improve frequency matching accuracy. Simultaneously, placing the load capacitors 40 on the first cover portion 121 allows the lower, complete first board surface 11 to serve as a ground plane, providing a stable reference potential, enhancing filtering, and effectively suppressing high-frequency noise coupling.

[0036] Furthermore, such as Figures 1-2 As shown, chip 20, load capacitor 40 and crystal oscillator 30 are connected in sequence. Load capacitor 40 is located between crystal oscillator 30 and chip 20, which helps to optimize layout space, shorten signal transmission path and reduce electromagnetic interference risk.

[0037] Furthermore, in some embodiments of this application, such as Figures 1-2 As shown, the plate 10 also has an insulating layer 15, which covers at least a portion of the first cover portion 121, and the ground terminal of the load capacitor 40 is connected to the insulating layer 15.

[0038] Understandably, the insulating layer 15 at least covers the portion of the copper foil layer 12 on the first cover portion 121 that is not electrically connected, to prevent the exposed portion of the copper foil layer 12 within the isolation zone 131 from being oxidized or causing electromagnetic reflection or parasitic coupling. Simultaneously, the grounding terminal of the load capacitor 40 is directly connected to the insulating layer 15, ensuring the continuity and reliability of the grounding path and avoiding the introduction of additional impedance or noise interference due to poor grounding, thereby guaranteeing the stability of the circuit operation.

[0039] An insulating layer 15 is also provided on the copper foil layer 12 located outside the isolation zone 131 to cover the areas of the copper foil layer 12 that are not electrically connected, thereby preventing the copper foil layer 12 from being oxidized or short-circuited. The insulating layer 15 is made of a high-resistance material, such as an oil-based coating, epoxy resin, or ceramic coating, which effectively blocks oxidation or leakage current paths on the surface of the copper foil layer 12.

[0040] Please see Figure 2 In some embodiments of this application, a plurality of vias 14 are provided on the first cover portion 121. The vias 14 penetrate the plate body 10 and the first cover portion 121. The plurality of vias 14 are arranged at intervals along the outer periphery of the crystal oscillator 30.

[0041] Specifically, a plurality of vias 14 are uniformly arranged along the outer periphery of the crystal oscillator 30 to form a conductive shielding ring around the crystal oscillator 30. The shielding ring structure can suppress external electromagnetic interference from intruding into the sensitive area of ​​the crystal oscillator 30, and the high-density arrangement of the vias 14 can further enhance the integrity of the RF return path and reduce the divergence of the edge field of high-frequency signals, thereby significantly reducing the impact of electromagnetic interference on the stability of the oscillation frequency. At the same time, the multiple vias 14 can make low-impedance multi-point connections between the first cover 121 and other ground plane layers inside the plate 10 in the vertical direction, thereby effectively reducing the ground loop impedance, improving the overall shielding effectiveness, and suppressing the radiation field.

[0042] The diameter and spacing of the vias 14 are optimized to match the electromagnetic wavelength of the target frequency band and further improve the shielding effectiveness. For example, the spacing between two adjacent vias 14 should be much smaller than the wavelength λ of the highest interference frequency that needs to be suppressed. Preferably, the spacing between two adjacent vias 14 is usually controlled within λ / 10 to achieve effective suppression of high-frequency interference.

[0043] In some embodiments, vias 14 are uniformly distributed along the inner periphery of the isolation trench 13. The number and diameter of the vias 14 are determined comprehensively based on actual electromagnetic shielding requirements and process feasibility. For example, the diameter of the vias 14 can be designed to be between 0.2 mm and 0.5 mm, and the spacing between two adjacent vias 14 is set to be between 1.25 mm and 2.5 mm.

[0044] Furthermore, in some embodiments of this application, such as Figure 2 As shown, multiple vias 14 are arranged at intervals along the outer periphery of the crystal oscillator 30 and the load capacitor 40.

[0045] It is understandable that multiple vias 14 are continuously arranged along the periphery of the crystal oscillator 30 and the load capacitor 40 on the inner circumference side of the isolation trench 13, forming an electromagnetic shielding loop. This shielding loop surrounds the crystal oscillator 30 and the load capacitor 40 in the same shielding area, effectively reducing electromagnetic coupling interference between the crystal oscillator 30 and the load capacitor 40 and the external circuit, and improving the purity and long-term stability of the oscillation signal.

[0046] Please see Figure 2 In some embodiments of this application, the vias 14 and the isolation trenches 13 are spaced apart, and the shortest interval between each via 14 and the isolation trench 13 is the same.

[0047] Specifically, maintaining a uniform minimum spacing between the via 14 and the isolation trench 13 can prevent electromagnetic field leakage in local areas, further enhance the continuity and integrity of the shielding ring, and the equidistant arrangement can reduce parasitic inductance differences and ensure consistent return path impedance.

[0048] In summary, during the fabrication of the circuit board 100 in this embodiment, the load capacitor 40 and the crystal oscillator 30 are preferentially positioned close to the chip 20 to shorten the signal transmission path and to make the conductive connection lines 50 as short, straight, and wide as possible, thereby reducing parasitic inductance and resistance, and minimizing high-frequency signal loss and reflection. Then, during the copper deposition process on the first board surface 11, a portion of the copper foil layer 12 is removed to form an annular isolation trench 13. The crystal oscillator 30 and the load capacitor 40 are then placed within the isolation area 131 enclosed by the isolation trench 13. Finally, a complete electromagnetic shielding structure is formed by uniformly arranging an array of vias 14 along the inner periphery of the isolation trench 13. This array of vias 14 works synergistically with the isolation trench 13 to effectively block electromagnetic coupling paths within and outside the isolation area 131, forming a physical barrier against high-frequency interference.

[0049] In the accompanying drawings of this embodiment, the same or similar reference numerals correspond to the same or similar components. In the description of this application, it should be understood that if terms such as "upper," "lower," "left," and "right" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting this application. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0050] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A circuit board, characterized in that, include: The board includes a first board surface and a copper foil layer covering the first board surface. The copper foil layer is provided with isolation grooves. The portion of the first board surface located in the isolation grooves is exposed through the isolation grooves. The isolation grooves enclose an isolation area. The copper foil layer includes a first covering portion located within the isolation area. A chip is disposed on the board, the chip is located outside the isolation area, and is electrically connected to the portion of the copper foil layer located outside the isolation area; A crystal oscillator is located in the isolation region, and the crystal oscillator is electrically connected to both the first cover portion and the chip.

2. The circuit board according to claim 1, characterized in that, An insulating filling layer is provided in the isolation trench.

3. The circuit board according to claim 1, characterized in that, The isolation trench is arranged in a ring around the crystal oscillator, and the circuit board is provided with conductive connection lines that cross the isolation area. The crystal oscillator and the chip are electrically connected through the conductive connection lines.

4. The circuit board according to claim 1, characterized in that, The first cover has a plurality of vias that penetrate the plate and the first cover, and the plurality of vias are arranged at intervals along the outer periphery of the crystal oscillator.

5. The circuit board according to claim 4, characterized in that, The first cover portion is provided with at least two load capacitors, which are electrically connected to the crystal oscillator and the chip.

6. The circuit board according to claim 5, characterized in that, The vias are spaced apart along the outer periphery of the crystal oscillator and the load capacitor.

7. The circuit board according to claim 5, characterized in that, The load capacitor is located between the crystal oscillator and the chip.

8. The circuit board according to claim 5, characterized in that, The plate also has an insulating layer that covers at least a portion of the first covering portion, and the ground terminal of the load capacitor is connected to the insulating layer.

9. The circuit board according to claim 4, characterized in that, The vias are spaced apart from the isolation trenches, and the shortest interval between each via and the isolation trench is the same.

10. The circuit board according to claim 1, characterized in that, The width of the isolation trench is greater than 0.5 mm.

11. The circuit board according to claim 1, characterized in that, The board body also includes a dielectric layer and a trace layer. The copper foil layer, the dielectric layer and the trace layer are stacked in sequence, and the side of the dielectric layer facing the copper foil layer is the first board surface.

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