A dual-port static random access memory cell and memory

Abstract

The application discloses a dual-port static random access memory unit and a memory. The unit comprises at least one fin extending along a first direction, and the fin is provided with an active region and a gate structure. A first interconnection metal structure is arranged on a first side of the fin to form a row-column arrangement of a first read-write transistor, a second read-write transistor, a first pull-up transistor and a second pull-up transistor. The channel regions of the first pull-up transistor and the second pull-up transistor are arranged in the same column along a second direction, and a wiring space is reserved on one side of the channel regions. The channel regions of the first read-write transistor and the second read-write transistor are located in the reserved wiring space. A second interconnection metal structure is arranged on an opposite second side of the fin. The transistors formed by the two interconnection metal structures share the fin as a channel carrier and are interconnected through a via. The structure can achieve higher storage density under the same area, support dual-port parallel access and improve the performance of multi-core cooperation.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a dual-port static random access memory cell and memory. Background Technology

[0002] Static random access memory (SRAM) is widely used in caches, register files, and on-chip high-speed storage due to its fast access speed and low standby power consumption. To improve parallel bandwidth and port utilization, processors or accelerators often employ dual-port SRAM cells, providing two sets of read / write ports on the same array to enable concurrent access and mitigate conflicts. In advanced fin-type field-effect transistor (FET) processes such as 7nm, layout libraries typically offer various cell types, such as high-density cells, high-current cells, two-port cells with independent read ports, and true dual-port read / write cells, to balance area, speed, and power consumption.

[0003] In related technologies, dual-port cells, compared to high-density or high-current cells, often require the introduction of a second set of port transmission transistors and their associated bit lines, word lines, and interconnects. The area is usually significantly increased, often nearly doubling that of high-density cells, and brings the following engineering constraints: area and wiring congestion. The signals of the two sets of ports must be brought out under limited cell height and strict metal spacing. The bit lines, word lines, and cross-layer vias brought by the second port significantly increase the wiring density, which can easily cause congestion and via blockage in the lower metal layers. It is difficult to complete the regular pin and channel planning within the height of the existing high-density cells, thereby limiting the array density and compilation scale, and adversely affecting the performance and stability of dual-port static random access memory cells.

[0004] Therefore, there is an urgent need to improve the structure and layout of dual-port static random access memory (SRAM) cells. Utility Model Content

[0005] To improve the performance and stability of a dual-port static random access memory (SRAM) cell, this application provides a dual-port SRAM cell and a memory.

[0006] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of this application.

[0007] According to a first aspect of this application, a dual-port static random access memory cell is provided, comprising: A semiconductor structure including at least one fin extending along a first direction, wherein the fin has an active region and a gate structure; A first interconnect metal structure is disposed on a first side of the semiconductor structure and electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first read / write transistor, a second read / write transistor, a first pull-up transistor, and a second pull-up transistor; wherein the channel regions of the first pull-up transistor and the second pull-up transistor are aligned along a second direction, and the channel regions of the first read / write transistor and the second read / write transistor are located on one side of the channel regions of the first pull-up transistor and the second pull-up transistor; the second direction is perpendicular to the first direction; A second interconnect metal structure is disposed on the second side of the semiconductor structure. The second interconnect metal structure is electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first transmission transistor, a second transmission transistor, a first pull-down transistor, and a second pull-down transistor. Wherein, the second side is the opposite side of the first side, the transistor formed by the first interconnect metal structure and the transistor formed by the second interconnect metal structure share the fin as the channel carrier, and the first interconnect metal structure is interconnected with the second interconnect metal structure through a via.

[0008] In some embodiments of this disclosure, one side of the channel region of the first pull-up transistor and the second pull-up transistor has reserved wiring space; the channel regions of the first read-write transistor and the second read-write transistor are disposed within the reserved wiring space.

[0009] In some embodiments of this disclosure, the channel regions of the first read / write transistor and the second read / write transistor are aligned along a second direction.

[0010] In some embodiments of this disclosure, the first interconnect metal structure includes a first word line extending along the first direction and a first conductive electronic structure extending along the second direction; The first conductive substructure is electrically connected to the gate structures of both the first read / write transistor and the second read / write transistor; The first word line is electrically connected to the first conductive substructure via a via to load a signal onto the first conductive substructure.

[0011] In some embodiments of this disclosure, the channel regions of the first read / write transistor and the second read / write transistor are aligned along a second direction; The first read / write transistor includes a first fin extending along the first direction; The second read / write transistor includes a second fin extending along the first direction; Wherein, at least a portion of the orthographic projection of the first conductive substructure onto the semiconductor structure overlaps with the orthographic projection of the first fin onto the semiconductor structure; Another portion of the orthogonal projection of the first conductive electronic structure onto the semiconductor structure overlaps with the orthogonal projection of the second fin onto the semiconductor structure.

[0012] In some embodiments of this disclosure, the first interconnect metal structure includes a second conductive substructure and a third conductive substructure extending along the second direction, and includes a first positive bit line and a first negative bit line extending along the first direction; Along the second direction, both the second conductive substructure and the third conductive substructure are disposed on the side of the first conductive substructure away from the channel region of the first read / write transistor and the channel region of the second read / write transistor. The second conductive substructure is electrically connected to the active region of the first read / write transistor; the first positive position line is electrically connected to the second conductive substructure through a via. The third conductive electronic structure is electrically connected to the active region of the second read / write transistor; the first reverse bit line is electrically connected to the third conductive electronic structure through a via.

[0013] In some embodiments of this disclosure, the second conductive substructure and the third conductive substructure are arranged in the same row along the second direction.

[0014] In some embodiments of this disclosure, adjacent dual-port static random access memory cells are symmetrically arranged along the second direction, such that the second conductive substructure simultaneously loads signals to the first read / write transistors in the adjacent dual-port static random access memory cells. The third conductive electronic structure simultaneously loads signals to the second read / write transistor in the adjacent dual-port static random access memory cell.

[0015] In some embodiments of this disclosure, the channel region of the first read / write transistor and the channel region of the first pull-up transistor are aligned along the first direction; The channel region of the second read / write transistor and the channel region of the second pull-up transistor are aligned along the first direction.

[0016] In some embodiments of this disclosure, the first interconnect metal structure includes a first transition substructure disposed along the first direction and a fourth conductive substructure disposed along the second direction. The fourth conductive electronic structure is simultaneously electrically connected to the active regions of the second read / write transistor and the second pull-up transistor; One end of the first adapter structure is electrically connected to the fourth conductive electronic structure through a via; the other end is electrically connected to the gate structure of the first pull-up transistor through a via.

[0017] In some embodiments of this disclosure, the second interconnect metal structure includes a second word line extending along the first direction, and a fifth conductive electronic structure extending along the second direction; The fifth conductive substructure is electrically connected to the gate structures of both the first and second transmission transistors. The second word line is electrically connected to the fifth conductive electronic structure via a via to load a signal onto the fifth conductive electronic structure.

[0018] In some embodiments of this disclosure, the channel region of the first transmission transistor and the channel region of the second transmission transistor are aligned along a second direction; The first transmission transistor and the first read / write transistor share a first fin extending along the first direction; The second transmission transistor and the second read / write transistor share a second fin extending along the first direction; Wherein, at least a portion of the orthographic projection of the fifth conductive fin structure onto the semiconductor structure overlaps with the orthographic projection of the first fin onto the semiconductor structure; The orthographic projection of the fifth conductive electronic structure onto the semiconductor structure overlaps with the orthographic projection of the second fin onto the semiconductor structure.

[0019] In some embodiments of this disclosure, the first interconnect metal structure includes a first conductive substructure extending along the second direction; The first conductive substructure is electrically connected to the gate structures of both the first read / write transistor and the second read / write transistor; The second interconnect metal structure includes a fifth conductive substructure extending in the second direction; the fifth conductive substructure is electrically connected to the gate structures of both the first transmission transistor and the second transmission transistor. Wherein, the orthogonal projection of the first conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthogonal projection of the fifth conductive electronic structure onto the semiconductor structure.

[0020] In some embodiments of this disclosure, the second interconnect metal structure includes a sixth conductive electronic structure and a seventh conductive electronic structure extending along the second direction, and includes a second positive bit line and a second negative bit line extending along the first direction; Along the second direction, the sixth conductive substructure and the seventh conductive substructure are both located on the side of the fifth conductive substructure away from the channel region of the first pull-down transistor and the channel region of the second pull-down transistor; The sixth conductive electronic structure is electrically connected to the active region of the first transmission transistor; the second positive position line is electrically connected to the sixth conductive electronic structure through a via. The seventh conductive electronic structure is electrically connected to the active region of the second transmission transistor; the second reverse bit line is electrically connected to the seventh conductive electronic structure through a via.

[0021] In some embodiments of this disclosure, the sixth conductive electronic structure and the seventh conductive electronic structure are arranged in the same row along the second direction.

[0022] In some embodiments of this disclosure, the first interconnect metal structure includes a second conductive substructure and a third conductive substructure extending along the second direction; The second conductive substructure is electrically connected to the active region of the first read / write transistor; The third conductive substructure is electrically connected to the active region of the second read / write transistor; The second interconnect metal structure includes a sixth conductive substructure and a seventh conductive substructure extending along the second direction; The sixth conductive electronic structure is electrically connected to the active region of the first transmission transistor; The seventh conductive electronic structure is electrically connected to the active region of the second transmission transistor; Wherein, the orthogonal projection of the sixth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthogonal projection of the second conductive electronic structure onto the semiconductor structure; The orthographic projection of the seventh conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the third conductive electronic structure onto the semiconductor structure.

[0023] In some embodiments of this disclosure, adjacent dual-port static random access memory cells are symmetrically arranged along the second direction, such that the sixth conductive electronic structure simultaneously loads signals to the first transmission transistors in the adjacent dual-port static random access memory cells. The seventh conductive electronic structure simultaneously loads signals to the second transmission transistor in the adjacent dual-port static random access memory cell.

[0024] In some embodiments of this disclosure, the channel region of the first transmission transistor and the channel region of the first pull-down transistor are aligned in a first direction; The channel region of the second transmission transistor and the channel region of the second pull-down transistor are aligned along the first direction.

[0025] In some embodiments of this disclosure, the second interconnect metal structure includes a second transition substructure disposed along the first direction and an eighth conductive substructure disposed along the second direction; The eighth conductive electronic structure is electrically connected to the active regions of both the first transmission transistor and the first pull-down transistor. One end of the second adapter structure is electrically connected to the eighth conductive electronic structure through a via; the other end is electrically connected to the gate structure of the second pull-down transistor through a via.

[0026] In some embodiments of this disclosure, the first interconnect metal structure includes a first transition substructure disposed along the first direction and a fourth conductive substructure disposed along the second direction. The fourth conductive electronic structure is simultaneously electrically connected to the active regions of the second read / write transistor and the second pull-up transistor; One end of the first adapter substructure is electrically connected to the fourth conductive substructure through a via; the other end is electrically connected to the gate structure of the first pull-up transistor through a via. The second interconnect metal structure includes a second transition substructure disposed along the first direction and an eighth conductive substructure disposed along the second direction; The eighth conductive electronic structure is simultaneously electrically connected to the active regions of the first transmission transistor and the second pull-down transistor; One end of the second adapter structure is electrically connected to the eighth conductive substructure through a via; the other end is electrically connected to the gate structure of the first pull-down transistor through a via. The orthographic projection of the first adapter structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the second adapter structure onto the semiconductor structure.

[0027] In some embodiments of this disclosure, the gate structure of the first pull-up transistor is electrically connected to the gate structure of the first pull-down transistor via a via. The gate structure of the second pull-up transistor is electrically connected to the gate structure of the second pull-down transistor through a via.

[0028] According to a second aspect of this application, a memory is provided, the memory comprising a plurality of row-column distributed dual-port static random access memory cells. Attached Figure Description

[0029] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the membrane structure of a dual-port static random access memory cell.

[0031] Figure 2 This is a schematic diagram of the stacking between fins and a first interconnect metal structure in one embodiment of multiple dual-port static random access memory cells.

[0032] Figure 3This is a schematic diagram of the stacking between fins and a second interconnect metal structure in one embodiment of multiple dual-port static random access memory cells.

[0033] Figure 4 This is the equivalent circuit diagram of a dual-port static random access memory (SRAM) cell.

[0034] Figure 5 This is a schematic diagram of the stacking between a fin and a first interconnect metal structure in one embodiment of an adjacent dual-port static random access memory cell.

[0035] Figure 6 This is a schematic diagram of the stacking between a fin and a second interconnect metal structure in one embodiment of an adjacent dual-port static random access memory cell.

[0036] Figure 7 This is a schematic diagram of the stacking between the fin and the first interconnect metal structure in a dual-port static random access memory cell.

[0037] Figure 8 This is a schematic diagram of the arrangement of the metal fins near the first interconnect structure in a dual-port static random access memory cell.

[0038] Figure 9 This is a schematic diagram of a transistor formed by the first interconnect metal structure and fins in a dual-port static random access memory cell.

[0039] Figure 10 This is a schematic diagram of the structure of the first metal layer in the first interconnect metal structure of a dual-port static random access memory cell.

[0040] Figure 11 This is a schematic diagram of the second metal layer in the first interconnect metal structure of a dual-port static random access memory cell.

[0041] Figure 12 This is a schematic diagram of the third metal layer in the first interconnect metal structure of a dual-port static random access memory cell.

[0042] Figure 13 This is a schematic diagram of the stacking between the fin and the second interconnect metal structure in a dual-port static random access memory cell.

[0043] Figure 14 This is a schematic diagram of the arrangement of the metal fins near the second interconnect structure in a dual-port static random access memory cell.

[0044] Figure 15 This is a schematic diagram of a transistor formed by the second interconnect metal structure and fins in a dual-port static random access memory cell.

[0045] Figure 16 This is a schematic diagram of the fourth metal layer in the second interconnect metal structure of a dual-port static random access memory cell.

[0046] Figure 17 This is a schematic diagram of the fifth metal layer in the second interconnect metal structure of a dual-port static random access memory cell.

[0047] Figure 18 This is a schematic diagram of the sixth metal layer in the second interconnect metal structure of a dual-port static random access memory cell.

[0048] Explanation of reference numerals in the attached figures: FEOL, Semiconductor structure; BEOL1, First interconnect metal structure; M1, First metal layer; M2, Second metal layer; M3, Third metal layer; BEOL2, Second interconnect metal structure; PSS1, First power supply structure; PSS2, Second power supply structure; M4, Fourth metal layer; M5, Fifth metal layer; M6, Sixth metal layer; WLP, First word line; WL, Second word line; BLP, First positive bit line; BLBP, First negative bit line; BL, Second positive bit line; BLB, Second negative bit line; VDD, Power supply voltage; VSS, Reference voltage; VDL, Power supply voltage line; VSL, Reference voltage line; PU0, First pull-up transistor; PU1, Second pull-up transistor; PD0. First pull-down transistor; PD1, second pull-down transistor; PGP0, first read / write transistor; PGP1, second read / write transistor; PG0, first transfer transistor; PG1, second transfer transistor; Q1, first memory node; Q2, second memory node; FIN, fin; FIN1, first fin; FIN2, second fin; MA1, first conductive substructure; MA2, second conductive substructure; MA3, third conductive substructure; MA4, fourth conductive substructure; MA5, fifth conductive substructure; MA6, sixth conductive substructure; MA7, seventh conductive substructure; MA8, eighth conductive substructure; MS1, first metal substructure; MS2, second metal substructure; MS3, third metal substructure; Substructure; MS4, Fourth Metal Substructure; MS5, Fifth Metal Substructure; MS6, Sixth Metal Substructure; MS7, Seventh Metal Substructure; HA1, First Lower Via Region; HA2, Second Lower Via Region; HA3, Third Lower Via Region; HA4, Fourth Lower Via Region; HA5, Fifth Lower Via Region; HA6, Sixth Lower Via Region; HA7, Seventh Lower Via Region; HA8, Eighth Lower Via Region; HA9, Ninth Lower Via Region; HA10, Tenth Lower Via Region; HA11, Eleventh Lower Via Region; HA12, Twelfth Lower Via Region; HA13, Thirteenth Lower Via Region; HA14, Fourteenth Lower Via Region; HA15, Fifteenth Lower Via Region; HA16, Sixteenth Lower Via Region; H B1, First upper via area; HB2, Second upper via area; HB3, Third upper via area; HB4, Fourth upper via area; HB5, Fifth upper via area; HB6, Sixth upper via area; HB7, Seventh upper via area; HB8, Eighth upper via area; HB9, Ninth upper via area; HB10, Tenth upper via area; HB11, Eleventh upper via area; HB12, Twelfth upper via area; HB13, Thirteenth upper via area; HB14, Fourteenth upper via area; HB15, Fifteenth upper via area; HB16, Sixteenth upper via area; DH, First direction; DV, Second direction; A1, First side; A2, Second side; CS1, First adapter substructure; CS2, Second adapter substructure. Detailed Implementation

[0049] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0050] The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments, and where possible, the features discussed in the various embodiments are interchangeable. In the above description, numerous specific details are provided to give a full understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0051] Although this application uses relative terms, such as "up" and "down," to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms, such as "high," "low," "top," "bottom," "front," "back," "left," and "right," also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0052] In this application, the terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0053] In related technologies, dual-port cells, compared to high-density or high-current cells, often require the introduction of a second set of port transmission transistors and their associated bit lines, word lines, and interconnects. The area is usually significantly increased, often nearly doubling that of high-density cells, and brings the following engineering constraints: area and wiring congestion. The signals of the two sets of ports must be brought out within the limited cell height and strict metal spacing. The bit lines, word lines, and cross-layer vias brought by the second port significantly increase the wiring density, which can easily cause congestion and via blockage in the lower metal layers. It is difficult to complete the regular pin and channel planning within the height of the existing high-density cells, thereby limiting the array density and compilation scale, and adversely affecting the performance and stability of dual-port static random access memory cells.

[0054] Based on this, this application provides a dual-port static random access memory (SRAM) unit. This dual-port SRAM unit and the memory using it have higher storage density in the same area and can support dual-port parallel access, improving multi-core collaborative performance.

[0055] Figure 1 A schematic diagram of the membrane structure of the dual-port static random access memory cell is shown in this embodiment. Figure 2 This embodiment illustrates a schematic diagram of the stacking of fins (FIN) and the first interconnect metal structure (BEOL1) in a plurality of dual-port static random access memory cells. Figure 3 This example illustrates the stacking diagram between the fin (FIN) and the second interconnect metal structure (BEOL2) in a dual-port static random access memory cell in this embodiment.

[0056] See Figure 1The dual-port static random access memory cell of this application includes a semiconductor structure FEOL, including at least one fin extending along a first direction DH, the fin having an active region and a gate structure (not specifically labeled in this application); a first interconnect metal structure BEOL1, disposed on the first side A1 of the semiconductor structure FEOL, electrically connected to the active region and the gate structure to form a row-and-column arrangement of first read / write transistors PGP0, second read / write transistors PGP1, first pull-up transistors PU0 and second pull-up transistors PU1; wherein, the channel regions of the first pull-up transistors PU0 and second pull-up transistors PU1 are aligned along the second direction DV, and the channel regions of the first read / write transistors PGP0 and PGP1 are located at... The first pull-up transistor PU0 and the second pull-up transistor PU1 are located on one side of the channel region; the second direction DV is perpendicular to the first direction DH; the second interconnect metal structure BEOL2 is located on the second side A2 of the semiconductor structure FEOL and is electrically connected to the active region and the gate structure to form a row-and-column arrangement of the first transmission transistor PG0, the second transmission transistor PG1, the first pull-down transistor PD0 and the second pull-down transistor PD1; wherein, the second side A2 is the opposite side of the first side A1, the transistors formed by the first interconnect metal structure BEOL1 and the transistors formed by the second interconnect metal structure BEOL2 share the same fin FIN as the channel carrier, and the first interconnect metal structure BEOL1 is interconnected with the second interconnect metal structure BEOL2 through vias.

[0057] It should be noted that in this application, "row" refers to the direction extending along the first direction DH, and "column" refers to the second direction DV perpendicular to it. Further, the gate structure refers to the control electrode portion formed above the fin channel, which includes a gate dielectric layer and a gate electrode, used to regulate the on or off state of the fin channel by an applied voltage, thereby achieving precise control of the transistor current. The active region refers to the region in the fin that participates in conduction, including the channel region, source region, and drain region, and is the main region for current carrying and signal transmission in the transistor. The gate structure and the active region work together to enable the transistor to perform the basic functions of logic switching and memory cells in a row-column arrangement.

[0058] In the disclosed embodiment, the dual-port static random access memory cell adopts a dual-sided interconnect structure design (a first interconnect metal structure BEOL1 and a second interconnect metal structure BEOL2). By setting the first interconnect metal structure BEOL1 on the first side A1 of the semiconductor structure FEOL, a first read / write transistor PGP0, a second read / write transistor PGP1, a first pull-up transistor PU0, and a second pull-up transistor PU1 are formed. The channel regions of the first pull-up transistor PU0 and the second pull-up transistor PU1 are arranged in the same column along the second direction DV, and wiring space is reserved on one side of the channel region to embed the first read / write transistor PGP0 and the second read / write transistor PGP1. This layout not only makes the connections between the pull-up transistors (first pull-up transistor PU0 and first pull-up transistor PU1) and the read / write transistors (first read / write transistor PGP0 and second read / write transistor PGP1) shorter and more direct, but also avoids cross wiring and redundant vias, thereby significantly reducing wiring congestion and interconnect complexity. Therefore, it is possible to improve the overall routing efficiency without increasing the layout area, compress the size of dual-port static random access memory cells, and reduce electrical performance fluctuations caused by irregular routing.

[0059] Furthermore, a second interconnect metal structure BEOL2 is formed on the second side A2 of the semiconductor structure FEOL to form the first transfer transistor PG0, the second transfer transistor PG1, the first pull-down transistor PD0, and the second pull-down transistor PD1. The transistors formed on the first side A1 and the second side A2 are interconnected through vias and share the same fin as the channel carrier. This fin reuse design not only reduces the number of fins and lowers the fabrication cost, but also forms a more compact integrated structure between the devices on both sides, avoiding electrical mismatch caused by differences in individual fins, and improving the consistency of device performance and the stability of the memory cell.

[0060] Furthermore, the transistors formed by the first interconnect metal structure BEOL1 and the second interconnect metal structure BEOL2 are directly connected through vias, which can shorten the signal transmission path, significantly reduce interconnect resistance and parasitic capacitance effects, and reduce signal delay and energy loss. Therefore, the dual-port static random access memory cell of this application can maintain high read / write speeds, reduce dynamic power consumption, and improve the energy efficiency ratio of circuit operation while achieving area reduction.

[0061] In summary, the dual-port static random access memory (SRAM) cell proposed in this application, through reasonable transistor layout, fin multiplexing, and dual-sided interconnect design, not only achieves higher integration density than traditional dual-port memory within the same area, but also improves the process adaptability, manufacturing consistency, and reliability of the memory cell. In multi-core processors or high-performance computing systems, this architecture can support multiple cores to access memory resources simultaneously, improving multi-core collaboration efficiency and overall system performance.

[0062] In some embodiments of this disclosure, the channel regions of the first pull-up transistor PU0 and the second pull-up transistor PU1 have reserved wiring space (not specifically marked in this application); the channel regions of the first read / write transistor PGP0 and the second read / write transistor PGP1 are located within the reserved wiring space.

[0063] Figure 4 An equivalent circuit diagram of a dual-port static random access memory cell according to an embodiment of this disclosure is illustrated. See also Figure 4 The basic principle of a dual-port static random access memory (SRAM) cell is explained below, using the example of a dual-port SRAM cell: The source of the first transmission transistor PG0 is electrically connected to the first positive bit line BLP; the gate of the first transmission transistor PG0 is electrically connected to the second word line WL; and the drain of the first transmission transistor PG0 is electrically connected to the first memory node Q1.

[0064] The source of the second transmission transistor PG1 is electrically connected to the first inverted bit line BLBP; the gate of the second transmission transistor PG1 is electrically connected to the second word line WL; and the drain of the second transmission transistor PG1 is electrically connected to the second memory node Q2.

[0065] The source of the first pull-up transistor PU0 is electrically connected to the power supply voltage VDD line; the drain of the first pull-up transistor PU0 is electrically connected to the first memory node Q1.

[0066] The source of the second pull-up transistor PU1 is electrically connected to the power supply voltage VDD line; the drain of the second pull-up transistor PU1 is electrically connected to the second memory node Q2.

[0067] The source of the first read / write transistor PGP0 is electrically connected to the second positive bit line BL, the drain of the first read / write transistor PGP0 is electrically connected to the first memory node Q1, and the gate of the first read / write transistor PGP0 is electrically connected to the first word line WLP.

[0068] The source of the second read / write transistor PGP1 is electrically connected to the second inverted bit line BLB; the drain of the second read / write transistor PGP1 is electrically connected to the second memory node Q2; and the gate of the second read / write transistor PGP1 is electrically connected to the first word line WLP.

[0069] The source of the first pull-down transistor PD0 is electrically connected to the reference voltage VSS trace; the drain of the first pull-down transistor PD0 is electrically connected to the first memory node Q1; the gate of the first pull-down transistor PD0 is electrically connected to the gate of the second memory node Q2 and the gate of the first pull-up transistor PU0.

[0070] The source of the second pull-down transistor PD1 is electrically connected to the reference voltage VSS trace, and the drain of the second pull-down transistor PD1 is electrically connected to the second memory node Q2; the gate of the second pull-down transistor PD1 is electrically connected to the gate of the first memory node Q1 and the second pull-up transistor PU1.

[0071] In this embodiment, the dual-port static random access memory cell includes a cross-coupled first inverter and a second inverter. The first inverter consists of a first pull-up transistor PU0 and a first pull-down transistor PD0, and the second inverter consists of a second pull-up transistor PU1 and a second pull-down transistor PD1. The two are cross-coupled to form a bistable latch structure.

[0072] In one embodiment, the first transmission transistor PG0, the second transmission transistor PG1, the first pull-down transistor PD0, and the second pull-down transistor PD1 are N-type transistors; the first read / write transistor PGP0, the second read / write transistor PGP1, the first pull-up transistor PU0, and the second pull-up transistor PU1 are P-type transistors.

[0073] The following is a detailed explanation of the circuit's operating principle, using this example as an example: During the data holding phase, the first word line WLP remains high, and the second word line WL remains low. Because the first word line WLP is high, the first read / write transistor PGP0 and the second read / write transistor PGP1 are off; simultaneously, the second word line WL is low, causing the first transfer transistor PG0 and the second transfer transistor PG1 to also be off. At this time, both the first memory node Q1 and the second memory node Q2 are disconnected from the four external bit lines (first positive bit line BLP, first negative bit line BLBP, second positive bit line BL, and second negative bit line BLB), completely isolating the cells from the external circuitry.

[0074] If the first storage node Q1 is high, the first pull-up transistor PU0 is turned on, providing current to maintain the high level for the first storage node Q1, while the first pull-down transistor PD0 is turned off to prevent the node from being pulled low. At this time, the second storage node Q2 is low, the second pull-down transistor PD1 is turned on, electrically connecting the second storage node Q2 to the reference voltage VSS trace, maintaining the low level, while the second pull-up transistor PU1 is turned off. This state is maintained stable through cross-coupling; if the initial state is reversed, i.e., the first storage node Q1 is low and the second storage node Q2 is high, the above process occurs in reverse, and the cell can still remain stable.

[0075] The write phase can be implemented using two different sets of ports.

[0076] First, writing is performed through the P-type read / write port. Firstly, complementary levels are applied to the second positive bit line BL and the second negative bit line BLB (for example, when writing logic "1", the second positive bit line BL is loaded with a high level, and the second negative bit line BLB is loaded with a low level). Then, the first word line WLP is pulled low, turning on the first read / write transistor PGP0 and the second read / write transistor PGP1. When the second positive bit line BL is high, the first memory node Q1 is forced high through the first read / write transistor PGP0; simultaneously, the second memory node Q2 is pulled low through the second negative bit line BLB, thus flipping the state through the cross-coupled inverter and stabilizing it in the state of "first memory node Q1 high, second memory node Q2 low". When writing logic "0", the second positive bit line BL is driven low, the first memory node Q1 is pulled low, and the second memory node Q2 is pulled high, thus achieving the state of "first memory node Q1 low, second memory node Q2 high".

[0077] Second, writing is performed through the N-type transmission port. First, complementary levels are applied to the first positive bit line BLP and the first negative bit line BLBP. Then, the second word line WL is pulled high, turning on the first transmission transistor PG0 and the second transmission transistor PG1. When logic "0" needs to be written, the first storage node Q1 is forced down to the reference voltage VSS through the first transmission transistor PG0, keeping the first pull-down transistor PD0 on to ensure node stability. At the same time, the second pull-up transistor PU1 on the opposite side is turned on, pulling the second storage node Q2 high to achieve logic flipping.

[0078] It should be noted that writing via the P-type read / write port: the first read / write transistor PGP0 and the second read / write transistor PGP1 are turned on by the first word line WLP, thereby writing external bit line data into the cell. Writing via the N-type transmit port: the first transmit transistor PG0 and the second transmit transistor PG1 are turned on by the second word line WL, thereby writing external bit line data into the cell.

[0079] Reading phase. To match the conduction characteristics of different types of transistors, this embodiment employs two different pre-charge schemes: First, reading is performed through the N-type transmission port. Before reading, the first positive bit line BLP and the first negative bit line BLBP are pre-charged to a high level. Subsequently, the second word line WL is pulled high, and the first transmission transistor PG0 and the second transmission transistor PG1 are turned on. If the first storage node Q1 is low, the first transmission transistor PG0 will discharge the first positive bit line BLP after it is turned on, forming a level difference, which the external circuit uses to detect the stored logic "0". If the first storage node Q1 is high, the first transmission transistor PG0 is turned off, the first positive bit line BLP remains high, and the second storage node Q2 is low, then a symmetrical differential is formed through the second transmission transistor PG1, causing the amplifier circuit to output logic "1".

[0080] Second, reading is performed through the P-type read / write port. Before reading, the second positive bit line BL and the second negative bit line BLB are both pre-charged to a low level. Subsequently, the first word line WLP is pulled low, turning on the first read / write transistor PGP0 and the second read / write transistor PGP1. If the first storage node Q1 is high, the first read / write transistor PGP0 pulls up the second positive bit line BL to form a level difference, which is then recognized as logic "1" by the external circuit; if the first storage node Q1 is low, the second read / write transistor PGP1 is turned on, pulling up the second negative bit line BLB to form a level difference, which is then recognized as logic "0" by the amplifier circuit.

[0081] Through the above design, the dual-port static random access memory cell of this embodiment utilizes the complementary characteristics of the P-type read / write transistor port and the N-type transmit transistor port, and in conjunction with different bit line precharge strategies, to achieve highly reliable data retention, strong drive writing, and high-speed differential reading, taking into account both the flexibility of multi-port access and the need for circuit area compression, and further improving the overall performance and adaptability of the memory cell.

[0082] It should be noted that writing via the P-type read / write port: the first read / write transistor PGP0 and the second read / write transistor PGP1 are turned on by the first word line WLP, enabling data to be written to the external bit line. Writing via the N-type transmit port: the first transmit transistor PG0 and the second transmit transistor PG1 are turned on by the second word line WL, enabling data to be written to the external bit line.

[0083] In some embodiments of this disclosure, see Figure 5 and Figure 7The first interconnect metal structure BEOL1 includes a first word line WLP extending along a first direction DH and a first conductive substructure MA1 extending along a second direction DV. The first conductive substructure MA1 is electrically connected to the gate structures of both the first read / write transistor PGP0 and the second read / write transistor PGP1. The first word line WLP is electrically connected to the first conductive substructure MA1 through a via (eighth lower via region HA8) to load a signal onto the first conductive substructure MA1. In this embodiment, the first word line WLP loads a signal onto the first conductive substructure MA1 through the via, and the first conductive substructure MA1 then simultaneously drives the gates of both the first read / write transistor PGP0 and the second read / write transistor PGP1, through unified control of the same conductive substructure. This reduces wiring complexity, minimizes congestion caused by cross-layer interconnects, improves signal transmission efficiency, ensures synchronous conduction or cutoff of the first read / write transistor PGP0 and the second read / write transistor PGP1, improves circuit matching and consistency, and enhances array stability.

[0084] Furthermore, the channel regions of the first read / write transistor PGP0 and the second read / write transistor PGP1 are aligned along the second direction DV; the first read / write transistor PGP0 includes a first fin FIN1 extending along the first direction DH; the second read / write transistor PGP1 includes a second fin FIN2 extending along the first direction DH; wherein, at least a portion of the orthographic projection of the first conductive electronic structure MA1 onto the semiconductor structure FEOL overlaps with the orthographic projection of the first fin FIN1 onto the semiconductor structure FEOL; another portion of the orthographic projection of the first conductive electronic structure MA1 onto the semiconductor structure FEOL overlaps with the orthographic projection of the second fin FIN2 onto the semiconductor structure FEOL. This arrangement ensures that the first conductive electronic structure MA1 is continuously arranged along the second direction DV within a dual-port static random access memory cell, thus avoiding multi-segment partitioning and multiple via connections, significantly simplifying the layout design; simultaneously, the first conductive electronic structure MA1 acts on both fins, reducing transistor threshold voltage deviation and conduction characteristic differences.

[0085] In some embodiments of this disclosure, see Figure 6 , Figure 7The first interconnect metal structure BEOL1 further includes a second conductive substructure MA2 and a third conductive substructure MA3 extending along the second direction DV, and a first positive bit line BLP and a first negative bit line BLBP extending along the first direction DH. Along the second direction DV, the second conductive substructure MA2 and the third conductive substructure MA3 are both located on the side of the first conductive substructure MA1 away from the channel region of the first read / write transistor PGP0 and the channel region of the second read / write transistor PGP1. The second conductive substructure MA2 is electrically connected to the active region of the first read / write transistor PGP0. The first positive bit line BLP is electrically connected to the second conductive substructure MA2 through a via (third lower via region HA3). The third conductive substructure MA3 is electrically connected to the active region of the second read / write transistor PGP1. The first negative bit line BLBP is electrically connected to the third conductive substructure MA3 through a via (fifth lower via region HA5).

[0086] In this embodiment, when a signal needs to be loaded onto the first read / write transistor PGP0, the signal is first transmitted through the first positive bit line BLP, then coupled to the second conductive substructure MA2 via a via, and finally loaded onto the active region of the first read / write transistor PGP0. When a signal needs to be loaded onto the second read / write transistor PGP1, the signal is first transmitted through the first negative bit line BLBP, then coupled to the third conductive substructure MA3 via a via, and finally loaded onto the active region of the second read / write transistor PGP1. Thus, by connecting the first positive bit line BLP and the first negative bit line BLBP to the corresponding conductive substructures via vias, the complexity of cross-layer or cross-region wiring is reduced, the signal transmission path is shortened, and latency is reduced. Furthermore, in this embodiment, the second conductive substructure MA2 and the third conductive substructure MA3 are regularly distributed in the layout and are both located on one side of the channel regions of the two read / write transistors, reducing mismatch caused by asymmetrical wiring and improving circuit stability.

[0087] As an example, along the second direction DV, the second conductive substructure MA2 and the third conductive substructure MA3 are arranged in the same column. In this example, by arranging the second conductive substructure MA2 and the third conductive substructure MA3 along the second direction DV in a straight line, the alignment and symmetry of the conductive substructures are ensured, making the circuit layout more regular and facilitating the design of standard cell arrays. Simultaneously, the co-alignment of the second conductive substructure MA2 and the third conductive substructure MA3 along the second direction DV allows the first positive bit line BLP and the first negative bit line BLBP to be accessed respectively through vias at the same regular spacing, reducing crossover or winding designs and lowering wiring congestion and wiring layer complexity.

[0088] Furthermore, during the manufacturing process, the colinear distribution of the second conductive electronic structure MA2 and the third conductive electronic structure MA3 reduces the impact of layout offset and mask alignment error on electrical performance, thereby improving device consistency and yield.

[0089] In some implementations, see Figure 5 Adjacent dual-port static random access memory (DRAM) cells are symmetrically arranged along the second direction DV, such that the second conductive substructure MA2 simultaneously loads signals to the first read / write transistor PGP0 in the adjacent dual-port DRAM cell; and the third conductive substructure MA3 simultaneously loads signals to the second read / write transistor PGP1 in the adjacent dual-port DRAM cell.

[0090] In some embodiments of this disclosure, see Figure 6 The second interconnect metal structure BEOL2 includes a second word line WL extending along a first direction DH, and a fifth conductive substructure MA5 extending along a second direction DV. The fifth conductive substructure MA5 is electrically connected to the gate structures of both the first transmission transistor PG0 and the second transmission transistor PG1. The second word line WL is electrically connected to the fifth conductive substructure MA5 through a via (first lower via region HA1) to load a signal onto the fifth conductive substructure MA5. In this embodiment, the fifth conductive substructure MA5 is electrically connected to the gate structures of both the first transmission transistor PG0 and the second transmission transistor PG1. The second word line WL is electrically connected to the fifth conductive substructure MA5 through a via. When an external control circuit loads a word line signal onto the second word line WL, the signal can be transmitted to the fifth conductive substructure MA5 through the via and simultaneously act on the gates of both the first transmission transistor PG0 and the second transmission transistor PG1, thereby controlling the on or off state of the two transmission transistors.

[0091] This configuration enables the second word line WL to drive the same column of transfer transistors (first transfer transistor PG0 and second transfer transistor PG1) in a unified manner, allowing the first transfer transistor PG0 and the second transfer transistor PG1 to respond synchronously to the word line signal. This simplifies the wiring structure, reduces the need for cross-layer interconnection, and minimizes wiring congestion. At the same time, it maintains the consistency of device driving and improves the stability and speed of the dual-port memory cell during write and read operations.

[0092] As an example, the orthographic projection of the first conductive electronic structure MA1 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the fifth conductive electronic structure MA5 onto the semiconductor structure FEOL. This arrangement allows the first conductive electronic structure MA1 and the fifth conductive electronic structure MA5 to be overlapped within a limited area, effectively saving layout area and increasing wiring density. Simultaneously, this overlap method reduces the length of cross-layer traces and the number of vias, lowering interconnect resistance and parasitic capacitance, thus optimizing signal transmission speed and improving the overall process compatibility and scalability of the circuit.

[0093] In some embodiments of this disclosure, see Figure 7 , Figure 13 The channel region of the first transmission transistor PG0 and the channel region of the second transmission transistor PG1 are aligned along the second direction DV; the first transmission transistor PG0 and the first read / write transistor PGP0 share a first fin FIN1 extending along the first direction DH; the second transmission transistor PG1 and the second read / write transistor PGP1 share a second fin FIN2 extending along the first direction DH; wherein, at least a portion of the orthographic projection of the fifth conductive electronic structure MA5 onto the semiconductor structure FEOL overlaps with the orthographic projection of the first fin FIN1 onto the semiconductor structure FEOL; and another portion of the orthographic projection of the fifth conductive electronic structure MA5 onto the semiconductor structure FEOL overlaps with the orthographic projection of the second fin FIN2 onto the semiconductor structure FEOL.

[0094] In this embodiment, the fifth conductor electronic structure MA5 is continuous and uninterrupted within a memory cell, thus avoiding unnecessary breakpoints or multi-segment splicing. This reduces transition resistance and parasitic capacitance in signal transmission, improving the loading efficiency and stability of the gate signal. The continuous layout reduces complex jumper and cross-layer interconnect designs in the layout, simplifying process implementation, improving alignment accuracy and device consistency during manufacturing, and reducing the risks associated with mismatches and process deviations. The continuous fifth conductor electronic structure MA5 provides lower latency and more uniform gate control signal transmission between different transistors, shortening the signal propagation path, reducing the number of cross-layer vias, thereby reducing power consumption and improving read / write speeds.

[0095] In some embodiments of this disclosure, see Figure 13 The second interconnect metal structure BEOL2 includes a sixth conductive electronic structure MA6 and a seventh conductive electronic structure MA7 extending along the second direction DV, and a second positive bit line BL and a second negative bit line BLB extending along the first direction DH. Along the second direction DV, the sixth conductive electronic structure MA6 and the seventh conductive electronic structure MA7 are both located on the side of the fifth conductive electronic structure MA5 away from the channel region of the first pull-down transistor PD0 and the channel region of the second pull-down transistor PD1. The sixth conductive electronic structure MA6 is electrically connected to the active region of the first transmission transistor PG0. The second positive bit line BL is electrically connected to the sixth conductive electronic structure MA6 through a via. The seventh conductive electronic structure MA7 is electrically connected to the active region of the second transmission transistor PG1. The second negative bit line BLB is electrically connected to the seventh conductive electronic structure MA7 through a via.

[0096] In this embodiment, the sixth conductive electronic structure MA6 is electrically connected to the active region of the first transmission transistor PG0. When the second positive bit line BL is loaded with a high-level or low-level signal, the second positive bit line BL transmits the signal to the sixth conductive electronic structure MA6 through a via, and then the sixth conductive electronic structure MA6 transmits it to the active region of the first transmission transistor PG0, thereby directly driving the change in the potential of the first memory node Q1. The sixth conductive electronic structure MA6 is electrically connected to the active region of the second transmission transistor PG1. When the second negative bit line BLB is loaded with a complementary signal, the second negative bit line BLB is also transmitted to the seventh conductive electronic structure MA7 through a via, and further transmitted to the active region of the second transmission transistor PG1, thereby acting on the second memory node Q2. The second positive bit line BL and the second negative bit line BLB are loaded with complementary signals, which are transmitted to the active regions of the first transmission transistor PG0 and the second transmission transistor PG1 through the sixth conductive electronic structure MA6 and the seventh conductive electronic structure MA7, so that the corresponding memory nodes can be quickly pulled high or low.

[0097] Furthermore, by directly connecting the sixth conductive electronic structure MA6 and the seventh conductive electronic structure MA7 to the active region of the transmission transistor, redundant cross-layer jumpers are avoided, the signal path is shortened, and interconnect resistance and parasitic capacitance are reduced. Signal loading is more direct, enabling the first storage node Q1 and the second storage node Q2 to respond quickly, shortening the write flip-flop and read discharge delay times, and improving the overall operating speed of the dual-port SRAM.

[0098] As an example, along the second direction DV, the sixth conductive electronic structure MA6 and the seventh conductive electronic structure MA7 are arranged in the same column. This arrangement ensures that the sixth conductive electronic structure MA6 and the seventh conductive electronic structure MA7 are arranged along the same straight line, making the metal interconnects of the circuit more symmetrical and regular on the layout, which is beneficial for the arraying and mass production of SRAM cells. Since the sixth conductive electronic structure MA6 and the seventh conductive electronic structure MA7 simultaneously carry complementary signals from the second positive bit line BL and the second negative bit line BLB, the linear symmetrical arrangement ensures that the paths of the signals to the active regions of the two transmission transistors are of equal length and have consistent delays, improving the differential characteristics and speed of read and write operations.

[0099] In some embodiments of this disclosure, the first interconnect metal structure BEOL1 includes a second conductive substructure MA2 and a third conductive substructure MA3 extending along the second direction DV; the second conductive substructure MA2 is electrically connected to the active region of the first read / write transistor PGP0; the third conductive substructure MA3 is electrically connected to the active region of the second read / write transistor PGP1; the second interconnect metal structure BEOL2 includes a sixth conductive substructure MA6 and a seventh conductive substructure MA7 extending along the second direction DV; the sixth conductive substructure MA6 is electrically connected to the active region of the first transmission transistor PG0; the seventh conductive substructure MA7 is electrically connected to the active region of the second transmission transistor PG1; wherein, the orthographic projection of the sixth conductive substructure MA6 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second conductive substructure MA2 onto the semiconductor structure FEOL; the orthographic projection of the seventh conductive substructure MA7 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the third conductive substructure MA3 onto the semiconductor structure FEOL.

[0100] In this embodiment, see Figure 7 , Figure 13 The orthographic projection of the sixth conductive electronic structure MA6 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second conductive electronic structure MA2, enabling the active regions of the first read / write transistor PGP0 and the first transmission transistor PG0 to achieve efficient electrical coupling through compact interconnection; the orthographic projection of the seventh conductive electronic structure MA7 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the third conductive electronic structure MA3, enabling the active regions of the second read / write transistor PGP1 and the second transmission transistor PG1 to also achieve electrical coupling through compact interconnection.

[0101] Furthermore, this configuration significantly shortens the interconnection distance between the first read / write transistor PGP0 and the first transmission transistor PG0, reducing signal transmission resistance and parasitic capacitance, and accelerating signal loading speed. Simultaneously, the overlapping layout between the second read / write transistor PGP1 and the second transmission transistor PG1 achieves a symmetrical structure, making the two data paths more consistent in geometric and electrical characteristics, reducing differential imbalance. Furthermore, the overlapping wiring simplifies the overall layout, reduces cell area, and is beneficial for high-density integration of dual-port SRAM arrays. From a process technology perspective, the overlapping interconnection of the read / write transistors (first read / write transistor PGP0, second read / write transistor PGP1) and the transmission transistors (first transmission transistor PG0, second transmission transistor PG1) reduces complex cross-wiring, improves mask alignment accuracy and metal interconnect process consistency, thereby improving yield and circuit stability.

[0102] In some embodiments of this disclosure, see Figure 6 , Figure 7The adjacent dual-port static random access memory cells are symmetrically arranged along the second direction DV, so that the sixth conductive electronic structure MA6 simultaneously loads signals to the first transmission transistor PG0 in the adjacent dual-port static random access memory cell; the seventh conductive electronic structure MA7 simultaneously loads signals to the second transmission transistor PG1 in the adjacent dual-port static random access memory cell.

[0103] In this embodiment, adjacent dual-port static random access memory (DRAM) cells are symmetrically arranged along the second direction DV. The sixth conductive electronic structure MA6 in the second interconnect metal structure BEOL2 extends to the adjacent DRAM cells and is electrically connected to the active regions of the first transfer transistors PG0 in the adjacent DRAM cells. When an external driving circuit applies a control signal to the sixth conductive electronic structure MA6, the signal is synchronously transmitted to multiple first transfer transistors PG0 in the adjacent cells, achieving parallel turn-on or turn-off control. Similarly, the seventh conductive electronic structure MA7 also extends to the adjacent DRAM cells along the second direction DV and is electrically connected to the active regions of the second transfer transistors PG1 in the adjacent cells. When an external driving circuit applies a signal to the seventh conductive electronic structure MA7, the signal is simultaneously transmitted to multiple second transfer transistors PG1 in the adjacent DRAM cells, achieving synchronous data access channel control.

[0104] With this configuration, the sixth conductive electronic structure MA6 can uniformly control and drive the first transmission transistor PG0 of the dual-port static random access memory (DRAM) cell; the seventh conductive electronic structure MA7 can uniformly control and drive the second transmission transistor PG1 of the DRAM cell. This avoids the complexity of independent wiring for a single DRAM cell and also avoids redundant control wiring, further compressing the cell area and facilitating high-density array integration.

[0105] In some embodiments of this disclosure, see Figure 7The first interconnect metal structure BEOL1 includes a first transition substructure CS1 disposed along a first direction DH and a fourth conductive substructure MA4 disposed along a second direction DV. The fourth conductive substructure MA4 is electrically connected to the active regions of both the second read / write transistor PGP1 and the second pull-up transistor PU1. One end of the first transition substructure CS1 is electrically connected to the fourth conductive substructure MA4 via a via, and the other end is electrically connected to the gate structure of the first pull-up transistor PU0 via a via. In this embodiment, the fourth conductive substructure MA4 is electrically connected to the active regions of both the second read / write transistor PGP1 and the second pull-up transistor PU1, achieving electrical coupling between the active regions of the two transistors. One end of the first transition substructure CS1 is electrically connected to the fourth conductive substructure MA4 via a via, and the other end is electrically connected to the gate structure of the first pull-up transistor PU0 via a via. In this way, the drain of the second pull-up transistor PU1 can be connected to the gate of the first pull-up transistor PU0.

[0106] In some embodiments of this disclosure, see Figure 13 The second interconnect metal structure BEOL2 includes a second transition substructure CS2 disposed along the first direction DH and an eighth conductive substructure MA8 disposed along the second direction DV; the eighth conductive substructure MA8 is electrically connected to the active regions of the first transmission transistor PG0 and the first pull-down transistor PD0; one end of the second transition structure CS2 is electrically connected to the eighth conductive substructure MA8 through a via; the other end is electrically connected to the gate structure of the second pull-down transistor PD1 through a via.

[0107] In this embodiment, the eighth conductive electronic structure MA8 is electrically connected to the active regions of both the first transmission transistor PG0 and the first pull-down transistor PD0, enabling electrical coupling between the active regions of the two transistors. One end of the second adapter structure CS2 is electrically connected to the eighth conductive electronic structure MA8 via a via, and the other end is electrically connected to the gate structure of the second pull-up transistor PU1 via a via. This achieves the connection between the drain of the first transmission transistor PG0 and the gate of the second pull-down transistor PD1.

[0108] As an example, the orthographic projection of the first interposer structure CS1 onto the semiconductor structure FEOL at least partially overlaps with the orthographic projection of the second interposer structure CS2 onto the semiconductor structure FEOL. In this example, the at least partial overlap of the orthographic projections of the first interposer structure CS1 and the second interposer structure CS2 allows for a compact space utilization, reducing the need for additional wiring channels. This arrangement not only helps to shorten interconnect paths, reduce interconnect resistance and parasitic capacitance, but also improves signal transmission speed and consistency.

[0109] In some embodiments of this disclosure, the gate structure of the first pull-up transistor PU0 is electrically connected to the gate structure of the first pull-down transistor PD0 via vias; the gate structure of the second pull-up transistor PU1 is electrically connected to the gate structure of the second pull-down transistor PD1 via vias. In this embodiment, interconnecting the gate structures of the first pull-up transistor PU0 and the first pull-down transistor PD0, and interconnecting the gate structures of the second pull-up transistor PU1 and the second pull-down transistor PD1 vias, not only directly realizes the complementary control relationship between the two memory nodes (first memory node Q1 and second memory node Q2), ensuring the stability of the latch unit and the reliability of data retention, but also shortens the signal transmission path, optimizes the layout area and wiring density, and helps improve process consistency and circuit yield.

[0110] In some embodiments of this disclosure, see Figure 13 The channel regions of the first transfer transistor PG0 and the first pull-down transistor PD0 are aligned along the first direction DH; the channel regions of the second transfer transistor PG1 and the second pull-down transistor PD1 are aligned along the first direction DH. By arranging the first transfer transistor PG0 and the first pull-down transistor PD0, and the second transfer transistor PG1 and the second pull-down transistor PD1 along the first direction DH, not only can the interconnect path be shortened and parasitic effects reduced, but the layout regularity and process consistency of the dual-port static random access memory cell can also be improved, thereby achieving comprehensive optimization of the dual-port static random access memory cell in terms of high speed, low power consumption, and high reliability.

[0111] In some embodiments of this disclosure, see Figure 5 , Figure 7 The channel regions of the first read / write transistor PGP0 and the first pull-up transistor PU0 are aligned along the first direction DH; the channel regions of the second read / write transistor PGP1 and the second pull-up transistor PU1 are aligned along the first direction DH. By arranging the first read / write transistor PGP0 and the first pull-up transistor PU0, and the second read / write transistor PGP1 and the second pull-up transistor PU1 along the first direction DH, the layout regularity and wiring efficiency can be improved. Furthermore, the access speed can be optimized, power consumption reduced, and process consistency and cell area utilization improved, thereby significantly enhancing the performance and adaptability of the dual-port static random access memory cell.

[0112] In some embodiments of this disclosure, the channel regions of the first read / write transistor PGP0 and the second read / write transistor PGP1 are aligned along the second direction DV.

[0113] In this embodiment, by arranging the channel regions of the first read / write transistor PGP0 and the second read / write transistor PGP1 in the same column along the second direction DV, the first read / write transistor PGP0 and the second read / write transistor PGP1 occupy a relatively regular and symmetrical position in the wiring space. This allows the corresponding traces to be laid out in a unified direction, avoiding cross-traces or loops. This reduces wiring length and effectively lowers parasitic capacitance and resistance, thereby shortening signal transmission delay.

[0114] In this embodiment, see Figure 5 The second conductive substructure MA2 extends continuously across two adjacent memory cells, simultaneously connecting with the active regions of the first read / write transistor PGP0 in the adjacent cells. When an external circuit loads a signal via the first positive bit line BLP, the second conductive substructure MA2 can synchronously transmit the signal to multiple first read / write transistors PGP0 in the adjacent cells, achieving simultaneous loading. Similarly, the third conductive substructure MA3 also spans two adjacent memory cells, electrically connecting with the active regions of the second read / write transistor PGP1 in the adjacent cells. When an external circuit loads a signal via the first negative bit line BLBP, the third conductive substructure MA3 can simultaneously transmit the signal to multiple second read / write transistors PGP1 in the adjacent cells. This configuration allows for simultaneous loading of signals to adjacent dual-port static random access memory cells through shared conductive substructures (the second and third sub-conductive structures), thereby achieving synchronous signal transmission, simplified wiring, and improved integration and read / write reliability of the memory array.

[0115] Figure 8 This embodiment illustrates the arrangement of the FIN fins on the side closest to the first interconnect metal structure BEOL1 in a dual-port static random access memory cell. Figure 9 This embodiment illustrates a schematic diagram of a transistor forming near the first interconnect metal structure BEOL1 and the fin FIN in a dual-port static random access memory cell. See also... Figure 8 , Figure 9 The first interconnect metal structure BEOL1 is electrically connected to the active region and the gate structure to form a row-and-column arrangement of the first read / write transistor PGP0, the second read / write transistor PGP1, the first pull-up transistor PU0, and the second pull-up transistor PU1.

[0116] In some implementations, the fin is preferably made of a semiconductor material, such as single-crystal silicon, which can be formed by etching a silicon substrate. To improve device performance, the fin can also be made of strained semiconductors or high-mobility materials, such as silicon-germanium, germanium, or group III-V compound semiconductors, to improve the carrier mobility of the channel. Depending on the process requirements, the fin can have different doped regions, where the active region is generally heavily doped through ion implantation or epitaxial growth, while the channel region remains lightly doped or intrinsic to ensure effective control of the channel conduction by the gate. The gate structure spans the channel region of the fin and typically includes a high-dielectric-constant gate dielectric layer and a metal gate material, which is isolated from the channel region of the fin to achieve modulation of the channel conductivity state.

[0117] Furthermore, to ensure the electrical characteristics of the dual-port static random access memory (SRAM) cell, the fin can have design parameters such as fin width and fin height, thereby achieving precise control over the channel length and channel area to meet the performance requirements of the SRAM cell in high-density integration. This application will not elaborate further on this aspect.

[0118] As an example, the first interconnect metal structure BEOL1 includes a first metal layer M1, a second metal layer M2, and a third metal layer M3 sequentially stacked along the semiconductor structure FEOL.

[0119] Figure 10 This embodiment illustrates a schematic diagram of the first metal layer M1 in the first interconnect metal structure BEOL1 within a dual-port static random access memory cell. See also... Figure 10 The first metal layer M1 includes a first conductive substructure MA1, a first metal substructure MS1, and a fourth conductive substructure MA4.

[0120] The first conductive electronic structure MA1 extends along the second direction DV and has an eighth lower via region HA8. The first interconnect metal structure BEOL1 includes a first word line WLP extending along the first direction DH, and the first word line WLP is electrically connected to the first conductive electronic structure MA1 through the eighth lower via region HA8.

[0121] The first metal substructure MS1 extends along the second direction DV, and the first metal substructure MS1 has a fourteenth lower via region HA14 and a fifteenth upper via region HB15.

[0122] The fourth conductive electronic structure MA4 extends along the second direction DV, and the fourth conductive structure has a sixteenth upper via region HB16.

[0123] As an example, the first metallic substructure MS1 and the fourth conductive substructure MA4 are arranged in the same column along the second direction DV.

[0124] Figure 11 This embodiment illustrates a schematic diagram of the second metal layer M2 in the first interconnect metal structure BEOL1 within a dual-port static random access memory cell. See also... Figure 11 The second metal layer M2 includes a second conductive substructure MA2, a third conductive substructure MA3, a second metal substructure MS2, a fourth conductive substructure MA4, and a third metal substructure MS3. The second conductive electronic structure MA2 extends along the second direction DV, and the second conductive electronic structure MA2 has a third lower via region HA3.

[0125] The third conductive electronic structure MA3 extends along the second direction DV, and has a fifth lower via region HA5. The first interconnect metal structure BEOL1 includes a second reverse bit line BLBP extending along the first direction DH, and the second reverse bit line BLBP is electrically connected to the third conductive electronic structure MA3 through the fifth lower via region HA5.

[0126] The second metal substructure MS2 extends along the second direction DV, and the second metal substructure MS2 has a ninth upper via region HB9.

[0127] The fourth conductive electronic structure MA4 extends along the second direction DV, and the fourth conductive electronic structure MA4 has a thirteenth lower via region HA13 and a twelfth upper via region HB12.

[0128] The third metal substructure MS3 extends along the second direction DV. The third metal substructure MS3 has a sixth lower via region HA6. The power supply voltage trace VDL is electrically connected to the third metal substructure MS3 through the sixth lower via region HA6, so as to achieve the purpose of loading the power supply voltage VDD onto the third metal substructure MS3.

[0129] It should be noted that the power supply voltage trace VDL is used to apply the power supply voltage VDD.

[0130] Figure 12 A schematic diagram of the third metal layer M3 in the first interconnect metal structure BEOL1 within a static random access memory cell is illustrated in this embodiment. See also Figure 12The third metal layer M3 includes a first adapter substructure CS1 extending along a first direction DH. The first adapter substructure CS1 has a thirteenth upper via region HB13 and a fourteenth upper via region HB14. The thirteenth upper via region HB13 is electrically connected to the thirteenth lower via region HA13 to load the signal from the fourth conductive electronic structure MA4 onto the first adapter substructure CS1; the fourteenth upper via region HB14 is electrically connected to the fourteenth lower via region HA14 to load the signal from the fourth conductive electronic structure MA4 onto the first adapter substructure CS1, and then onto the first metal substructure MS1 via the first adapter substructure CS1.

[0131] Figure 14 This embodiment illustrates the arrangement of the FIN fins on the side closest to the second interconnect metal structure BEOL2 in a dual-port static random access memory cell. Figure 15 This embodiment illustrates a schematic diagram of a transistor formed by the second interconnect metal structure BEOL2 and the fin FIN in a dual-port static random access memory cell. See also... Figure 14 , Figure 15 The fin has an active region and a gate structure; the second interconnect metal structure BEOL2 is formed with the fin to form a row-and-column arrangement of the first transmission transistor PG0, the second transmission transistor PG1, the first pull-down transistor PD0 and the second pull-down transistor PD1.

[0132] In some implementations, the fin is preferably made of a semiconductor material, such as single-crystal silicon, which can be formed by etching a silicon substrate. To improve device performance, the fin can also be made of strained semiconductors or high-mobility materials, such as silicon-germanium, germanium, or group III-V compound semiconductors, to improve the carrier mobility of the channel. Depending on the process requirements, the fin can have different doped regions, where the active region is generally heavily doped through ion implantation or epitaxial growth, while the channel region remains lightly doped or intrinsic to ensure effective control of the channel conduction by the gate. The gate structure spans the channel region of the fin and typically includes a high-dielectric-constant gate dielectric layer and a metal gate material, which is isolated from the channel region of the fin to achieve modulation of the channel conductivity state.

[0133] Furthermore, to ensure the electrical characteristics of the static random access memory (SRAM) cells, the fins can have design parameters such as fin width and fin height, thereby achieving precise control over the channel length and channel area to meet the performance requirements of SRAM cells in high-density integration. This application will not elaborate further on this aspect.

[0134] As an example, the second interconnect metal structure BEOL2 includes a fourth metal layer M4, a fifth metal layer M5, and a sixth metal layer M6 sequentially stacked along the semiconductor structure FEOL.

[0135] Figure 16 A schematic diagram of the fourth metal layer M4 in the second interconnect metal structure BEOL2 within a static random access memory cell is illustrated in this embodiment. See also Figure 16 The fourth metal layer M4 includes the fifth conductive substructure MA5, the fourth metal substructure MS4, and the fifth conductive substructure MA5. The fifth conductive electronic structure MA5 extends along the second direction DV and has a first lower via area HA1. The second word line WL is electrically connected to the fifth conductive electronic structure MA5 through the first lower via area HA1 to achieve the purpose of loading a signal onto the fifth conductive electronic structure MA5.

[0136] The fourth metal substructure MS4 extends along the second direction DV, and the fourth metal substructure MS4 has a fifteenth lower via region HA15; the fifteenth lower via region HA15 and the fifteenth upper via region HB15 are electrically connected to realize the purpose of electrically connecting the gate structure of the first pull-up transistor PU0 and the gate structure of the first pull-down transistor PD0.

[0137] The fifth metal substructure MS5 extends along the second direction DV, and the fifth metal substructure MS5 has an eleventh via region HA11.

[0138] Figure 17 A schematic diagram of the fifth metal layer M5 in the second interconnect metal structure BEOL2 within a dual-port static random access memory cell is illustrated in this embodiment. See also... Figure 17 The fifth metal layer M5 includes a sixth conductive substructure MA6, a seventh conductive substructure MA7, a second metal substructure MS2, an eighth conductive substructure MA8, a sixth metal substructure MS6, and a seventh metal substructure MS7.

[0139] The sixth conductive electronic structure MA6 extends along the second direction DV. The sixth conductive electronic structure MA6 has a second lower via region HA2. The second positive position line BL is electrically connected to the sixth conductive electronic structure MA6 through the second lower via region HA2, so as to realize the purpose of loading a signal from the second positive position line BL to the sixth conductive electronic structure MA6.

[0140] The seventh conductive electronic structure MA7 extends along the second direction DV. The seventh conductive electronic structure MA7 has a fourth lower via region HA4. The second reverse bit line BLB is electrically connected to the seventh conductive electronic structure MA7 through the fourth lower via region HA4, so as to realize the purpose of loading a signal from the second reverse bit line BLB to the seventh conductive electronic structure MA7.

[0141] The eighth conductive electronic structure MA8 extends along the second direction DV. The eighth conductive electronic structure MA8 has a ninth lower via region HA9, wherein the ninth lower via region HA9 overlaps with the ninth upper via region HB9 and is connected through vias to realize the interconnection between the eighth conductive electronic structure MA8 and the second metal substructure MS2.

[0142] The sixth metal substructure MS6 extends along the second direction DV. The sixth metal substructure MS6 has a twelfth lower via region HA12, wherein the twelfth lower via region HA12 overlaps with the twelfth upper via region HB12 and is connected through vias to realize the interconnection between the sixth metal substructure MS6 and the fourth conductive substructure MA4.

[0143] The seventh metal substructure MS7 extends along the second direction DV. The sixth metal substructure MS6 has a seventh lower via region HA7. The reference voltage trace VSL is electrically connected to the seventh metal substructure MS7 through the seventh lower via region HA7 to achieve the purpose of loading the reference voltage VSS onto the seventh metal substructure MS7.

[0144] It should be noted that the reference voltage trace VSL is used to apply the reference voltage VSS.

[0145] Figure 18 A schematic diagram of the sixth metal layer M6 in the second interconnect metal structure BEOL2 within a static random access memory cell is illustrated in this embodiment. See also... Figure 18 The sixth metal layer M6 includes a second transition substructure CS2 extending along the first direction DH. The second transition substructure CS2 has a tenth upper via region HB10 and an eleventh upper via region HB11. The tenth upper via region HB10 is electrically connected to the tenth lower via region HA10, and the eleventh upper via region HB11 is electrically connected to the eleventh lower via region HA11, thereby enabling the signal on the sixth metal substructure MS6 to be loaded onto the second transition substructure CS2, and then loaded onto the fifth metal substructure MS5 through the second transition substructure CS2.

[0146] Furthermore, in some embodiments of this disclosure, the dual-port static random access memory cell further includes a first power supply structure PSS1 located on the side of the first interconnect metal structure BEOL1 away from the semiconductor structure FEOL; a second power supply structure PSS2 located on the side of the second interconnect metal structure BEOL2 away from the semiconductor structure FEOL; a power supply voltage line VDL and a reference voltage line VSL extending along the first direction DH; wherein the reference voltage line VSL is disposed on the second power supply structure PSS2; and the power supply voltage line VDL is disposed on the first power supply structure PSS1.

[0147] By setting up a first power supply structure PSS1 and a second power supply structure PSS2 on the side of the first interconnect metal structure BEOL1 and the second interconnect metal structure BEOL2 away from the semiconductor structure FEOL, and routing the reference voltage line VSL on the second power supply structure PSS2 and the power supply voltage line VDL on the first power supply structure PSS1, the power supply voltage VDD and the reference voltage VSS are separated and powered on different interconnect structure layers. This layout not only effectively alleviates the congestion of wiring on the same layer and improves wiring regularity and electrical isolation, but also allows for flexible adjustment based on the wiring resources on different surfaces, optimizing the overall routing strategy and saving wiring space. Furthermore, the distribution of the reference voltage VSS and the power supply voltage VDD on different metal structure layers can reduce coupling interference between power lines, improve the stability and consistency of power supply, thereby improving the performance and manufacturing yield of the memory cell array. At the same time, arranging the reference voltage line VSL on the second power supply structure PSS2 can save the winding resources of the first interconnect metal structure BEOL1.

[0148] It should be understood that this application is not limited to the detailed structure and arrangement of the components proposed in this application. This application can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of this application. It should be understood that the disclosure and definition of this application extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this application. The embodiments described in this application illustrate the best known mode for implementing this application and will enable those skilled in the art to utilize this application.

Claims

1. A dual-port static random access memory (SRAM) unit, characterized in that, include: A semiconductor structure including at least one fin extending along a first direction, wherein the fin has an active region and a gate structure; A first interconnect metal structure is disposed on a first side of the semiconductor structure and electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first read / write transistor, a second read / write transistor, a first pull-up transistor, and a second pull-up transistor; wherein the channel regions of the first pull-up transistor and the second pull-up transistor are aligned along a second direction, and the channel regions of the first read / write transistor and the second read / write transistor are located on one side of the channel regions of the first pull-up transistor and the second pull-up transistor; the second direction is perpendicular to the first direction; A second interconnect metal structure is disposed on the second side of the semiconductor structure. The second interconnect metal structure is electrically connected to the active region and the gate structure to form a row-and-column arrangement of a first transmission transistor, a second transmission transistor, a first pull-down transistor, and a second pull-down transistor. Wherein, the second side is the opposite side of the first side, the transistor formed by the first interconnect metal structure and the transistor formed by the second interconnect metal structure share the fin as the channel carrier, and the first interconnect metal structure is interconnected with the second interconnect metal structure through a via.

2. The dual-port static random access memory unit according to claim 1, characterized in that, The first pull-up transistor and the second pull-up transistor have reserved wiring space on one side of their channel regions; the channel regions of the first read-write transistor and the second read-write transistor are located within the reserved wiring space.

3. The dual-port static random access memory unit according to claim 1, characterized in that, The channel regions of the first read / write transistor and the second read / write transistor are aligned along the second direction.

4. The dual-port static random access memory unit according to claim 1, characterized in that, The first interconnect metal structure includes a first word line extending along the first direction and a first conductive electronic structure extending along the second direction; The first conductive substructure is electrically connected to the gate structures of both the first read / write transistor and the second read / write transistor; The first word line is electrically connected to the first conductive substructure via a via to load a signal onto the first conductive substructure.

5. The dual-port static random access memory unit according to claim 4, characterized in that, The channel region of the first read / write transistor and the channel region of the second read / write transistor are aligned along the second direction; The first read / write transistor includes a first fin extending along the first direction; The second read / write transistor includes a second fin extending along the first direction; Wherein, at least a portion of the orthographic projection of the first conductive substructure onto the semiconductor structure overlaps with the orthographic projection of the first fin onto the semiconductor structure; Another portion of the orthogonal projection of the first conductive electronic structure onto the semiconductor structure overlaps with the orthogonal projection of the second fin onto the semiconductor structure.

6. The dual-port static random access memory unit according to claim 4, characterized in that, The first interconnect metal structure includes a second conductive substructure and a third conductive substructure extending along the second direction, and includes a first positive position line and a first negative position line extending along the first direction; Along the second direction, both the second conductive substructure and the third conductive substructure are disposed on the side of the first conductive substructure away from the channel region of the first read / write transistor and the channel region of the second read / write transistor. The second conductive substructure is electrically connected to the active region of the first read / write transistor; the first positive position line is electrically connected to the second conductive substructure through a via. The third conductive electronic structure is electrically connected to the active region of the second read / write transistor; the first reverse bit line is electrically connected to the third conductive electronic structure through a via.

7. The dual-port static random access memory unit according to claim 6, characterized in that, Along the second direction, the second conductive substructure and the third conductive substructure are arranged in the same column.

8. The dual-port static random access memory unit according to claim 6, characterized in that, The adjacent dual-port static random access memory cells are symmetrically arranged along the second direction, so that the second conductive substructure simultaneously loads signals to the first read / write transistors in the adjacent dual-port static random access memory cells; The third conductive electronic structure simultaneously loads signals to the second read / write transistor in the adjacent dual-port static random access memory cell.

9. The dual-port static random access memory unit according to claim 1, characterized in that, The channel region of the first read / write transistor and the channel region of the first pull-up transistor are aligned along the first direction; The channel region of the second read / write transistor and the channel region of the second pull-up transistor are aligned along the first direction.

10. The dual-port static random access memory unit according to claim 1, characterized in that, The first interconnect metal structure includes a first transition substructure disposed along the first direction and a fourth conductive substructure disposed along the second direction; The fourth conductive electronic structure is simultaneously electrically connected to the active regions of the second read / write transistor and the second pull-up transistor; One end of the first adapter structure is electrically connected to the fourth conductive electronic structure through a via; the other end is electrically connected to the gate structure of the first pull-up transistor through a via.

11. The dual-port static random access memory unit according to claim 4, characterized in that, The second interconnect metal structure includes a second word line extending along the first direction, and a fifth conductive electronic structure extending along the second direction; The fifth conductive substructure is electrically connected to the gate structures of both the first and second transmission transistors. The second word line is electrically connected to the fifth conductive electronic structure via a via to load a signal onto the fifth conductive electronic structure.

12. The dual-port static random access memory unit according to claim 11, characterized in that, The channel region of the first transmission transistor and the channel region of the second transmission transistor are aligned along the second direction; The first transmission transistor and the first read / write transistor share a first fin extending along the first direction; The second transmission transistor and the second read / write transistor share a second fin extending along the first direction; Wherein, at least a portion of the orthographic projection of the fifth conductive fin structure onto the semiconductor structure overlaps with the orthographic projection of the first fin onto the semiconductor structure; The orthographic projection of the fifth conductive electronic structure onto the semiconductor structure overlaps with the orthographic projection of the second fin onto the semiconductor structure.

13. The dual-port static random access memory unit according to claim 1, characterized in that, The first interconnect metal structure includes a first conductive electronic structure extending along the second direction; The first conductive substructure is electrically connected to the gate structures of both the first read / write transistor and the second read / write transistor; The second interconnect metal structure includes a fifth conductive substructure extending in the second direction; the fifth conductive substructure is electrically connected to the gate structures of both the first transmission transistor and the second transmission transistor. Wherein, the orthogonal projection of the first conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthogonal projection of the fifth conductive electronic structure onto the semiconductor structure.

14. The dual-port static random access memory unit according to claim 11, characterized in that, The second interconnect metal structure includes a sixth conductive electronic structure and a seventh conductive electronic structure extending along the second direction, and includes a second positive position line and a second negative position line extending along the first direction; Along the second direction, the sixth conductive substructure and the seventh conductive substructure are both located on the side of the fifth conductive substructure away from the channel region of the first pull-down transistor and the channel region of the second pull-down transistor; The sixth conductive electronic structure is electrically connected to the active region of the first transmission transistor; the second positive position line is electrically connected to the sixth conductive electronic structure through a via. The seventh conductive electronic structure is electrically connected to the active region of the second transmission transistor; the second reverse bit line is electrically connected to the seventh conductive electronic structure through a via.

15. The dual-port static random access memory unit according to claim 14, characterized in that, Along the second direction, the sixth conductive electronic structure and the seventh conductive electronic structure are arranged in the same column.

16. The dual-port static random access memory unit according to claim 1, characterized in that, The first interconnect metal structure includes a second conductive substructure and a third conductive substructure extending along the second direction; The second conductive substructure is electrically connected to the active region of the first read / write transistor; The third conductive substructure is electrically connected to the active region of the second read / write transistor; The second interconnect metal structure includes a sixth conductive substructure and a seventh conductive substructure extending along the second direction; The sixth conductive electronic structure is electrically connected to the active region of the first transmission transistor; The seventh conductive electronic structure is electrically connected to the active region of the second transmission transistor; Wherein, the orthogonal projection of the sixth conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthogonal projection of the second conductive electronic structure onto the semiconductor structure; The orthographic projection of the seventh conductive electronic structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the third conductive electronic structure onto the semiconductor structure.

17. The dual-port static random access memory unit according to claim 16, characterized in that, The adjacent dual-port static random access memory cells are symmetrically arranged along the second direction, so that the sixth conductive electronic structure simultaneously loads signals to the first transmission transistor in the adjacent dual-port static random access memory cells; The seventh conductive electronic structure simultaneously loads signals to the second transmission transistor in the adjacent dual-port static random access memory cell.

18. The dual-port static random access memory unit according to claim 1, characterized in that, The channel region of the first transmission transistor and the channel region of the first pull-down transistor are aligned in the first direction; The channel region of the second transmission transistor and the channel region of the second pull-down transistor are aligned along the first direction.

19. The dual-port static random access memory unit according to claim 1, characterized in that, The second interconnect metal structure includes a second transition substructure disposed along the first direction and an eighth conductive substructure disposed along the second direction; The eighth conductive electronic structure is electrically connected to the active regions of both the first transmission transistor and the first pull-down transistor. One end of the second adapter structure is electrically connected to the eighth conductive electronic structure through a via; the other end is electrically connected to the gate structure of the first pull-down transistor through a via.

20. The dual-port static random access memory unit according to claim 1, characterized in that, The first interconnect metal structure includes a first transition substructure disposed along the first direction and a fourth conductive substructure disposed along the second direction; The fourth conductive electronic structure is simultaneously electrically connected to the active regions of the second read / write transistor and the second pull-up transistor; One end of the first adapter substructure is electrically connected to the fourth conductive substructure through a via; the other end is electrically connected to the gate structure of the first pull-up transistor through a via. The second interconnect metal structure includes a second transition substructure disposed along the first direction and an eighth conductive substructure disposed along the second direction; The eighth conductive electronic structure is simultaneously electrically connected to the active regions of the first transmission transistor and the second pull-down transistor; One end of the second adapter substructure is electrically connected to the eighth conductive substructure through a via; The other end is electrically connected to the gate structure of the first pull-down transistor through a via; The orthographic projection of the first adapter structure onto the semiconductor structure at least partially overlaps with the orthographic projection of the second adapter structure onto the semiconductor structure.

21. The dual-port static random access memory unit according to claim 1, characterized in that, The gate structure of the first pull-up transistor is electrically connected to the gate structure of the first pull-down transistor through a via. The gate structure of the second pull-up transistor is electrically connected to the gate structure of the second pull-down transistor through a via.

22. A memory, characterized in that, The memory includes a plurality of row-column distributed dual-port static random access memory cells as described in any one of claims 1 to 21.

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