Memory device

Abstract

A memory device includes a well formed in a substrate and extending along a first lateral direction, wherein the well has a first conductivity type. The memory device includes an epitaxial structure disposed above the well, wherein the epitaxial structure has a second conductivity type opposite the first conductivity type. The memory device includes a common epitaxial structure disposed above the well, wherein the common epitaxial structure has the first conductivity type and contacts the well. Each of a first group of the epitaxial structures contacts the well, and each of a second group of the epitaxial structures has a bottom surface separated from the well by a corresponding dielectric layer.

Description

Technical Field

[0001] This disclosure concerns a memory device. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more components to be integrated into a given area. Utility Model Content

[0003] Some embodiments disclosed herein provide a memory device including a well, an epitaxial structure, and a shared epitaxial structure. The well is formed in a substrate and extends along a first lateral direction, wherein the well has a first conductivity type. The epitaxial structure is disposed above the well, wherein the epitaxial structure has a second conductivity type relative to the first conductivity type. The shared epitaxial structure is disposed above the well, wherein the shared epitaxial structure has a first conductivity type and contacts the well. Each of a first group of epitaxial structures contacts the well, and each of a second group of epitaxial structures has a bottom surface separated from the well by a corresponding dielectric layer.

[0004] Some embodiments disclosed herein provide a memory device including a well, an epitaxial structure, a gate structure, and a shared epitaxial structure. The well is formed in a substrate and extends along a first lateral direction, wherein the well has a first conductivity type. The epitaxial structure is disposed above the well, wherein the epitaxial structure has a second conductivity type relative to the first conductivity type. The gate structure extends along a second lateral direction perpendicular to the first lateral direction, wherein each of the epitaxial structures is disposed adjacent to a corresponding gate structure along the first lateral direction. The shared epitaxial structure is disposed above the well, wherein the shared epitaxial structure has a first conductivity type and contacts the well. Each of a first group of epitaxial structures contacts the well, and each of a second group of epitaxial structures has a bottom surface separated from the well by a corresponding dielectric layer.

[0005] Some embodiments of this disclosure provide a memory device including a well formed in a substrate and extending along a first lateral direction, wherein the well has a first conductivity type. A plurality of epitaxial structures disposed above the well, wherein the epitaxial structures have a second conductivity type relative to the first conductivity type. A plurality of gate structures extending along a second lateral direction perpendicular to the first lateral direction, wherein each epitaxial structure is disposed adjacent to a corresponding gate structure along the first lateral direction. A common epitaxial structure disposed above the well, wherein the common epitaxial structure has a first conductivity type and contacts the well. A first group of epitaxial structures each contacts the well, and a second group of epitaxial structures each has a bottom surface separated from the well by a corresponding dielectric layer, wherein a corresponding one of the first group of epitaxial structures and the common epitaxial structure operatively function as a first type diode, and a corresponding one of the second group of epitaxial structures and the common epitaxial structure operatively function as a second type diode. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the following detailed description will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic diagram of a read-only memory (ROM) unit according to some embodiments;

[0008] Figure 2 This is another schematic diagram of a ROM unit according to some embodiments;

[0009] Figure 3 This is a layout according to some embodiments for forming a memory array including multiple ROM units;

[0010] Figure 4 Based on some embodiments Figure 3 A hybrid cross-sectional view of the memory array formed by the layout;

[0011] Figure 5 and Figure 6 It is based on some embodiments respectively in Figure 4 A cross-sectional view of the memory array shown;

[0012] Figure 7 This is a layout for forming a memory array including multiple ROM units according to some embodiments;

[0013] Figure 8 Based on some embodiments Figure 7A mixed cross-sectional view of the memory array formed by the layout;

[0014] Figure 9 and Figure 10 It is based on some embodiments respectively in Figure 8 A cross-sectional view of the memory array shown;

[0015] Figure 11 This is a layout for forming a memory array including multiple ROM units according to some embodiments;

[0016] Figure 12 Based on some embodiments Figure 11 A mixed cross-sectional view of the memory array formed by the layout;

[0017] Figure 13 and Figure 14 It is based on some embodiments respectively in Figure 12 A cross-sectional view of the memory array shown;

[0018] Figure 15 This is a layout for forming a memory array including multiple ROM units according to some embodiments;

[0019] Figure 16 Based on some embodiments Figure 15 A mixed cross-sectional view of the memory array formed by the layout;

[0020] Figure 17 and Figure 18 It is based on some embodiments respectively in Figure 16 A cross-sectional view of the memory array shown;

[0021] Figure 19 This is a layout for forming a memory array including multiple ROM units according to some embodiments;

[0022] Figure 20 Based on some embodiments Figure 19 A mixed cross-sectional view of the memory array formed by the layout;

[0023] Figure 21 and Figure 22 It is based on some embodiments respectively in Figure 20 A cross-sectional view of the memory array shown;

[0024] Figure 23 This is a layout for forming a memory array including multiple ROM units according to some embodiments;

[0025] Figure 24 Based on some embodiments Figure 23A mixed cross-sectional view of the memory array formed by the layout;

[0026] Figure 25 and Figure 26 It is based on some embodiments respectively in Figure 24 A cross-sectional view of the memory array shown;

[0027] Figure 27 This is a layout for forming a memory array including multiple ROM units according to some embodiments;

[0028] Figure 28 Based on some embodiments Figure 27 A mixed cross-sectional view of the memory array formed by the layout;

[0029] Figure 29 This is an example flowchart of a method for manufacturing a memory array having multiple ROM cells, according to some embodiments.

[0030] [Symbol Explanation]

[0031] 100: ROM unit

[0032] 110: Diode

[0033] 120A: First terminal / Positive terminal

[0034] 120B: Second terminal / Negative terminal

[0035] 200: ROM unit

[0036] 210: Diode

[0037] 220A: First terminal / Negative terminal

[0038] 220B: Second terminal / positive terminal

[0039] 300: Layout

[0040] 305: Well / p Well

[0041] 310: Dielectric layer

[0042] 312: Active Zone

[0043] 314: Gate structure

[0044] 316: Gate structure

[0045] 318: Gate structure

[0046] 320: Gate structure

[0047] 322: Gate structure

[0048] 324: Gate structure

[0049] 326: Gate structure

[0050] 328A: Epitaxial structure

[0051] 328B: Epitaxial structure

[0052] 328C: Epitaxial structure

[0053] 328D: Epitaxial structure

[0054] 328E: Epitaxial structure

[0055] 328F: Epitaxial structure

[0056] 330A: Source / Drain Contact Structure

[0057] 330B: Source / Drain Contact Structure

[0058] 330C: Source / Drain Contact Structure

[0059] 330D: Source / Drain Contact Structure

[0060] 330E: Source / Drain Contact Structure

[0061] 330F: Source / Drain Contact Structure

[0062] 333: Through-hole structure

[0063] 339: Through-hole structure

[0064] 340: Interconnection structure / M0 track

[0065] 344: Interconnection structure / M0 track

[0066] 346: Interconnection structure / M0 track

[0067] 348: Interconnection structure / M0 track

[0068] 350: Interconnection structure / M0 track

[0069] 352: Interconnection structure / M0 track

[0070] 354: Interconnection structure / M0 track

[0071] 360: Interconnection Structure / M1 Track

[0072] 362: Interconnection structure / M1 track

[0073] 364: Interconnection Structure / M1 Track

[0074] 366: Interconnection structure / M1 track

[0075] 368: Interconnection structure / M1 track

[0076] 410: ROM unit

[0077] 420: ROM unit

[0078] 430: ROM unit

[0079] 440: ROM unit

[0080] 450: ROM unit

[0081] 700: Layout

[0082] 705: Well / n wells

[0083] 710: Dielectric layer

[0084] 712: Active Zone

[0085] 714: Gate Structure

[0086] 716: Gate Structure

[0087] 718: Gate Structure

[0088] 720: Gate Structure

[0089] 722: Gate Structure

[0090] 724: Gate Structure

[0091] 726: Gate Structure

[0092] 728A: Epitaxial structure

[0093] 728B: Epitaxial structure

[0094] 728C: Epitaxial Structure

[0095] 728D: Epitaxial structure

[0096] 728E: Epitaxial structure

[0097] 728F: Epitaxial structure

[0098] 730A: Source / Drain Contact Structure

[0099] 730B: Source / Drain Contact Structure

[0100] 730C: Source / Drain Contact Structure

[0101] 730D: Source / Drain Contact Structure

[0102] 730E: Source / Drain Contact Structure

[0103] 730F: Source / Drain Contact Structure

[0104] 733: Through-hole structure

[0105] 739: Through-hole structure

[0106] 740: Interconnection structure / M0 track

[0107] 744: Interconnection structure / M0 track

[0108] 746: Interconnection structure / M0 track

[0109] 748: Interconnection structure / M0 track

[0110] 750: Interconnection structure / M0 track

[0111] 752: Interconnection structure / M0 track

[0112] 754: Interconnection structure / M0 track

[0113] 760: Interconnection structure / M1 track

[0114] 762: Interconnection structure / M1 track

[0115] 764: Interconnection Structure / M1 Track

[0116] 766: Interconnection structure / M1 track

[0117] 768: Interconnection structure / M1 track

[0118] 810: ROM unit

[0119] 820: ROM unit

[0120] 830: ROM unit

[0121] 840: ROM unit

[0122] 850: ROM unit

[0123] 1100: Layout

[0124] 1105: well / p well

[0125] 1110: Dielectric layer

[0126] 1112: Active Zone

[0127] 1114: Gate Structure

[0128] 1116: Gate Structure

[0129] 1118: Gate Structure

[0130] 1120: Gate Structure

[0131] 1122: Gate Structure

[0132] 1124: Gate Structure

[0133] 1126: Gate Structure

[0134] 1128A: Epitaxial structure

[0135] 1128B: Epitaxial structure

[0136] 1128C: Epitaxial structure

[0137] 1128D: Epitaxial structure

[0138] 1128E: Epitaxial structure

[0139] 1128F: Epitaxial structure

[0140] 1130A: Source / Drain Contact Structure

[0141] 1130B: Source / Drain Contact Structure

[0142] 1130C: Source / Drain Contact Structure

[0143] 1130D: Source / Drain Contact Structure

[0144] 1130E: Source / Drain Contact Structure

[0145] 1130F: Source / Drain Contact Structure

[0146] 1133: Through-hole structure

[0147] 1139: Through-hole structure

[0148] 1140: Interconnection structure / M0 track

[0149] 1144: Interconnection structure / M0 track

[0150] 1146: Interconnection structure / M0 track

[0151] 1148: Interconnection structure / M0 track

[0152] 1150: Interconnection structure / M0 track

[0153] 1152: Interconnection structure / M0 track

[0154] 1154: Interconnection structure / M0 track

[0155] 1160: Interconnection structure / M1 track

[0156] 1162: Interconnection structure / M1 track

[0157] 1164: Interconnection structure / M1 track

[0158] 1166: Interconnection structure / M1 track

[0159] 1168: Interconnection structure / M1 track

[0160] 1210: ROM unit

[0161] 1220: ROM unit

[0162] 1230: ROM unit

[0163] 1240: ROM unit

[0164] 1250: ROM unit

[0165] 1500: Layout

[0166] 1505: Well / n wells

[0167] 1510: Dielectric layer

[0168] 1512: Active Zone

[0169] 1514: Gate Structure

[0170] 1516: Gate Structure

[0171] 1518: Gate Structure

[0172] 1520: Gate Structure

[0173] 1522: Gate Structure

[0174] 1524: Gate Structure

[0175] 1526: Gate Structure

[0176] 1528A: Epitaxial structure

[0177] 1528B: Epitaxial structure

[0178] 1528C: Epitaxial structure

[0179] 1528D: Epitaxial structure

[0180] 1528E: Epitaxial structure

[0181] 1528F: Epitaxial structure

[0182] 1530A: Source / Drain Contact Structure

[0183] 1530B: Source / Drain Contact Structure

[0184] 1530C: Source / Drain Contact Structure

[0185] 1530D: Source / Drain Contact Structure

[0186] 1530E: Source / Drain Contact Structure

[0187] 1530F: Source / Drain Contact Structure

[0188] 1533: Through-hole structure

[0189] 1539: Through-hole structure

[0190] 1540: Interconnection structure / M0 track

[0191] 1544: Interconnection structure / M0 track

[0192] 1546: Interconnection structure / M0 track

[0193] 1548: Interconnection structure / M0 track

[0194] 1550: Interconnection structure / M0 track

[0195] 1552: Interconnection structure / M0 track

[0196] 1554: Interconnection structure / M0 track

[0197] 1560: Interconnection structure / M1 track

[0198] 1562: Interconnection structure / M1 track

[0199] 1564: Interconnection structure / M1 track

[0200] 1566: Interconnection structure / M1 track

[0201] 1568: Interconnection structure / M1 track

[0202] 1610: ROM unit

[0203] 1620: ROM unit

[0204] 1630: ROM unit

[0205] 1640: ROM unit

[0206] 1650: ROM unit

[0207] 1900: Layout

[0208] 1905: Well / p well

[0209] 1910: Dielectric layer

[0210] 1912: Active Zone

[0211] 1914: Gate Structure

[0212] 1916: Gate Structure

[0213] 1918: Gate Structure

[0214] 1920: Gate Structure

[0215] 1922: Gate Structure

[0216] 1924: Gate Structure

[0217] 1926: Gate Structure

[0218] 1928A: Epitaxial structure

[0219] 1928B: Epitaxial structure

[0220] 1928C: Epitaxial structure

[0221] 1928D: Epitaxial structure

[0222] 1928E: Epitaxial structure

[0223] 1928F: Epitaxial structure

[0224] 1930A: Source / Drain Contact Structure

[0225] 1930B: Source / Drain Contact Structure

[0226] 1930C: Source / Drain Contact Structure

[0227] 1930D: Source / Drain Contact Structure

[0228] 1930E: Source / Drain Contact Structure

[0229] 1930F: Source / Drain Contact Structure

[0230] 1933: Through-hole structure

[0231] 1939: Through-hole structure

[0232] 1940: Interconnection structure / M0 track

[0233] 1943: Through-hole structure

[0234] 1944: Interconnection Structure / M0 Track

[0235] 1946: Interconnection Structure / M0 Track

[0236] 1948: Interconnection Structure / M0 Track

[0237] 1950: Interconnection structure / M0 track

[0238] 1952: Interconnection structure / M0 track

[0239] 1954: Interconnection structure / M0 track

[0240] 1960: Interconnection structure / M1 track

[0241] 1962: Interconnection Structure / M1 Track

[0242] 1964: Interconnection Structure / M1 Track

[0243] 1966: Interconnection Structure / M1 Track

[0244] 1968: Interconnection Structure / M1 Track

[0245] 2010: ROM Unit

[0246] 2020: ROM Unit

[0247] 2030: ROM Unit

[0248] 2040: ROM unit

[0249] 2050: ROM unit

[0250] 2300: Layout

[0251] 2305: Well / n wells

[0252] 2310: Dielectric layer

[0253] 2312: Active Zone

[0254] 2314: Gate Structure

[0255] 2316: Gate Structure

[0256] 2318: Gate Structure

[0257] 2320: Gate Structure

[0258] 2322: Gate structure

[0259] 2324: Gate Structure

[0260] 2326: Gate Structure

[0261] 2328A: Epitaxial structure

[0262] 2328B: Epitaxial structure

[0263] 2328C: Epitaxial structure

[0264] 2328D: Epitaxial structure

[0265] 2328E: Epitaxial structure

[0266] 2328F: Epitaxial structure

[0267] 2330A: Source / Drain Contact Structure

[0268] 2330B: Source / Drain Contact Structure

[0269] 2330C: Source / Drain Contact Structure

[0270] 2330D: Source / Drain Contact Structure

[0271] 2330E: Source / Drain Contact Structure

[0272] 2330F: Source / Drain Contact Structure

[0273] 2333: Through-hole structure

[0274] 2339: Through-hole structure

[0275] 2340: Interconnection structure / M0 track

[0276] 2344: Interconnection structure / M0 track

[0277] 2346: Interconnection structure / M0 track

[0278] 2348: Interconnection structure / M0 track

[0279] 2350: Interconnection structure / M0 track

[0280] 2352: Interconnection structure / M0 track

[0281] 2354: Interconnection structure / M0 track

[0282] 2343: Through-hole structure

[0283] 2360: Interconnection Structure / M1 Track

[0284] 2362: Interconnection structure / M1 track

[0285] 2364: Interconnection Structure / M1 Track

[0286] 2366: Interconnection structure / M1 track

[0287] 2368: Interconnection Structure / M1 Track

[0288] 2410: ROM unit

[0289] 2420: ROM unit

[0290] 2430: ROM unit

[0291] 2440: ROM unit

[0292] 2450: ROM unit

[0293] 2700: Layout

[0294] 2705: well / p well

[0295] 2710: Dielectric layer

[0296] 2712: Active Zone

[0297] 2714: Gate Structure

[0298] 2716: Gate Structure

[0299] 2718: Gate Structure

[0300] 2720: Gate Structure

[0301] 2722: Gate Structure

[0302] 2724: Gate Structure

[0303] 2726: Gate Structure

[0304] 2728A: Epitaxial structure

[0305] 2728B: Epitaxial structure

[0306] 2728C: Epitaxial structure

[0307] 2728D: Epitaxial structure

[0308] 2728E: Epitaxial structure

[0309] 2728F: Epitaxial structure

[0310] 2730A: Source / Drain Contact Structure

[0311] 2730B: Source / Drain Contact Structure

[0312] 2730C: Source / Drain Contact Structure

[0313] 2730D: Source / Drain Contact Structure

[0314] 2730E: Source / Drain Contact Structure

[0315] 2730F: Source / Drain Contact Structure

[0316] 2739: Through-hole structure

[0317] 2744:M0 track / interconnection structure

[0318] 2746:M0 track / interconnection structure

[0319] 2748:M0 track / interconnection structure

[0320] 2750:M0 track / interconnection structure

[0321] 2752:M0 track / interconnection structure

[0322] 2754:M0 track / interconnection structure

[0323] 2760: Interconnection structure / M1 track

[0324] 2762: Interconnection structure / M1 track

[0325] 2764: Interconnection Structure / M1 Track

[0326] 2766: Interconnection structure / M1 track

[0327] 2768: Interconnection structure / M1 track

[0328] 2810: ROM unit

[0329] 2820: ROM unit

[0330] 2830: ROM unit

[0331] 2840: ROM unit

[0332] 2850: ROM unit

[0333] 2900: Method

[0334] 2910: Operation

[0335] 2920: Operation

[0336] 2930: Operation

[0337] 2940: Operation

[0338] 2950: Operation

[0339] 2960: Operation

[0340] A-A': line

[0341] B-B': line

[0342] BL: Bitline

[0343] C-C': line

[0344] VDD: Supply voltage

[0345] VSS: Ground voltage / Supply voltage

[0346] WL: Character Line

[0347] WL0: Character Line

[0348] WL1: Character Line

[0349] WL2: Character Line

[0350] WL3: Character Line

[0351] WL4: Character Line

[0352] X: Direction

[0353] Y: direction

[0354] Z: Direction Detailed Implementation

[0355] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0356] Furthermore, the spatially related terms used herein, such as “below,” “under,” “below,” “above,” “on,” “above,” etc., are for descriptive purposes to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, these spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0357] Read-only memory (ROM) arrays are arrays of semiconductor memory chips where data is permanently stored. A ROM array consists of multiple ROM cells, each containing a semiconductor device (e.g., a transistor, switch, etc.) that can be configured (e.g., programmed) to be "on" or "off". Each ROM cell is configured to store data bits reflecting its on or off state (e.g., binary). Programming a ROM cell to be on or off typically depends on whether a via structure is formed that connects the active region of the transistor (e.g., source / drain region) to a voltage carrying ground (e.g., VSS). Therefore, a ROM array containing multiple ROM cells may include multiple locations where via structures are not formed. This "non-uniform" distribution of via structures often leads to manufacturing problems. Consequently, existing ROM devices / arrays are not entirely satisfactory in some respects.

[0358] This disclosure provides various embodiments of a memory device (e.g., a memory array) comprising multiple ROM cells. Each ROM cell can be formed as a diode based on a transistor-like structure and programmed using various process techniques. By programming the ROM cells during formation, a relatively uniformly distributed network of contact vias can be formed across the memory array, advantageously avoiding the aforementioned manufacturing problems. For example, after forming a well (e.g., having a first conductivity type) in the substrate, an active region can be formed above the well, which can have the same length as the well. Next, multiple gate structures can be formed across the active region, and then multiple epitaxial structures can be formed in the active region, alternating with the gate structures. Before forming the epitaxial structures, one or more portions of the well can each be covered by a dielectric layer. At least one first epitaxial structure, having a first conductivity type, can be formed to directly contact the well; at least one second epitaxial structure, having a second, opposite conductivity type, can be formed to directly contact the well; and at least one third epitaxial structure, having a second conductivity type, can be formed above the corresponding dielectric layer (e.g., physically and electrically separated from the well by the dielectric layer). Having the same (first) conductivity type, the first epitaxial structure can be formed as a contact or connector serving as a coupling well. Next, a plurality of first through-hole structures and a plurality of second through-hole structures can be formed to contact the gate structure and the epitaxial structure, respectively.

[0359] Each first via structure coupled to the corresponding gate structure is coupled to a supply voltage (e.g., VDD, VSS), thereby electrically turning off the corresponding transistor according to its own conductivity type. As a non-limiting example, the supply voltage VDD is approximately 0.75V and VSS is approximately 0V. One of the second via structures coupled to the first epitaxial structure is then coupled to a common bit line (BL), while the remaining second via structures coupled to the second or third epitaxial structure are each coupled to a word line (WL). Therefore, the first and second epitaxial structures can operatively form a "connected diode," and the first and third epitaxial structures can operatively form a "disconnected diode." As disclosed herein, the term "disconnected diode" refers to a diode having a first terminal connected to the corresponding word line and a second terminal connected to the corresponding common bit line, wherein the bit line and word line are not connected to each other. The term "connected diode" refers to a diode having a first terminal connected to the corresponding word line and a second terminal connected to the corresponding common bit line, wherein the bit line and word line are coupled to each other. Finally, during configuration, the connected diode can be programmed with a first logic state, and the non-connected diode can be programmed with a second logic state.

[0360] Figure 1 Example circuit diagrams of a single ROM cell 100 are shown according to some embodiments. Multiple ROM cells 100 can be arranged in an array (e.g., two-dimensional) having multiple rows and multiple columns. Each ROM cell 100 is located at the intersection of a corresponding row and a corresponding column. Each row can correspond to an individual bit line (BL), and each column can correspond to an individual word line (WL). Although in Figure 1 The ROM cell 100 shown includes a diode 110, and it should be understood that it provides... Figure 1 The circuit diagrams are for illustrative purposes and are not intended to limit the scope of this disclosure. Therefore, Figure 1 The ROM unit 100 shown may include any various other elements, while remaining within the scope of this disclosure.

[0361] As shown in the figure, the ROM unit 100 includes a diode 110 having a first terminal 120A and a second terminal 120B. The first terminal 120A and the second terminal 120B can correspond to the positive terminal (anode) and the negative terminal (cathode) of the diode 110, respectively. In some embodiments, the positive terminal 120A, which forms a first epitaxial structure, is connected to the bit line BL, and the negative terminal 120B, which forms a second epitaxial structure, is connected to the word line WL.

[0362] In some embodiments of this disclosure, bit line BL and word line WL can be coupled or decoupled from each other by selectively coupling the first and second epitaxial structures to each other, respectively. In some embodiments, bit line BL and word line WL can be coupled or decoupled from each other by selectively forming a via structure between word line WL and positive terminal 120A. In some embodiments, bit line BL and word line WL can be coupled or decoupled from each other by selectively forming V0 between word line WL and MO track connected to positive terminal 120A. Whether ROM cell 100 is in a logic "1" or "0" state can depend on whether bit line BL and word line WL of diode 110 are connected to each other. In other words, ROM cell 100 can be programmed with logic states depending on whether forming diode 110 is connected or not. For example, when word line WL is connected to bit line BL, ROM cell 100 presents logic 1. When word line WL is not connected to bit line BL, ROM cell 100 presents logic 0.

[0363] Figure 2 Example circuit diagrams of a single ROM cell 200 are shown according to some embodiments. Multiple ROM cells 200 can be arranged in an array (e.g., two-dimensional) having multiple rows and multiple columns. Each ROM cell 200 is located at the intersection of a corresponding row and a corresponding column. Each row can correspond to an individual bit line (BL), and each column can correspond to an individual word line (WL). Although in Figure 2 The ROM cell 200 shown includes a diode 210, and it should be understood that it provides... Figure 2 The circuit diagrams are for illustrative purposes and are not intended to limit the scope of this disclosure. Therefore, Figure 2 The ROM unit 200 shown may include any various other elements while remaining within the scope of this disclosure.

[0364] As shown in the figure, the ROM unit 200 includes a diode 210 having a first terminal 220A and a second terminal 220B. The first terminal 220A and the second terminal 220B can correspond to the negative terminal (cathode) and the positive terminal (anode) of the diode 210, respectively. In some embodiments, the negative (first) terminal 220A, which forms a first epitaxial structure, is connected to the bit line BL, and the positive (second) terminal 220B, which forms a second epitaxial structure, is connected to the word line WL.

[0365] In some embodiments of this disclosure, bit line BL and word line WL can be coupled or decoupled from each other by selectively coupling the first and second epitaxial structures to each other, respectively. In some embodiments, bit line BL and word line WL can be coupled or decoupled from each other by selectively forming a via structure between word line WL and negative terminal 220A. In some embodiments, bit line BL and word line WL can be coupled or decoupled from each other by selectively forming V0 between word line WL and the M0 track connecting negative terminal 220A. Whether ROM cell 200 is in a logic "1" or "0" state can depend on whether bit line BL and word line WL of diode 210 are connected to each other. In other words, ROM cell 200 can be programmed with logic states depending on whether forming diode 210 is connected or not. For example, when word line WL is connected to bit line BL, ROM cell 200 presents logic 1. When word line WL is not connected to bit line BL, ROM cell 200 presents logic 0.

[0366] Figure 3 The illustration depicts an example layout 300 configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 4 , Figure 5 and Figure 6 Cross-sectional views of the memory array formed based on layout 300 are shown.

[0367] For example, Figure 4 A mixed cross-sectional view showing a memory array tangent to or parallel to line A-A' (e.g., the X direction). Figure 5 Draw a cross-sectional view of the memory array cut along line B-B' (e.g., the Y direction), and Figure 6 This diagram illustrates a cross-sectional view of a memory array cut along line C-C' (e.g., the Y direction). As disclosed herein, the term "mixed cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 3 layout and Figures 4 to 6 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0368] First, refer to Figure 3 The layout 300 includes, respectively, for forming a well 305, one or more dielectric layers 310 (in... Figures 4 to 5The pattern of the active region 312 and gate structures 314, 316, 318, 320, 322, 324, and 326 is shown better in a cross-sectional view. In some embodiments, the well 305 and the active region 312 may extend along a first lateral direction (e.g., the X direction), while the gate structures 314 to 326 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, the gate structures 314 to 326 may each span the active region 312. The gate structures 314 to 326 may each correspond to an active (e.g., a metal) gate structure. For example, the gate structures 314 to 326 may each be formed as a polysilicon gate structure (sometimes referred to as a dummy gate structure) and then replaced with a corresponding metal gate structure (sometimes referred to as an active gate structure). The well 305, dielectric layer 310, active region 312, and gate structures 314 to 326 formed along the main surface of the substrate are sometimes referred to as a partial front-end-of-line (FEOL) process.

[0369] exist Figures 3 to 6 In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 410 to 450 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 410 to 450 of the memory array (formed by layout 300) can be formed as any of various other transistor structures, while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 312 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes multiple semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack covered by each gate structure 314 to 326 are retained, while other portions are replaced by multiple epitaxial structures 328A to 328F. The reserved portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structures 328A to 328F that couple the two ends of the channel (e.g., along the X direction) can be configured as the source / drain structure of the transistor, and the partial gate structures 314 to 326 that cover (e.g., straddle) the reserved portion of the semiconductor structure can be configured as the gate termination of the transistor.

[0370] exist Figures 3 to 4In this configuration, epitaxial structures 328A, 328B, 328C, 328D, 328E, and 328F (formed in the active region 312) and gate structures 314 to 326 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 328A is located between gate structures 314 and 316, epitaxial structure 328B is located between gate structures 316 and 318, epitaxial structure 328C is located between gate structures 318 and 320, epitaxial structure 328D is located between gate structures 320 and 322, epitaxial structure 328E is located between gate structures 322 and 324, and epitaxial structure 328F is located between gate structures (not shown) and gate structure 326. Furthermore, ROM cells 410 to 450 are programmed using different logic states. The first group of epitaxial structures (e.g., 328A, 328D) can be physically separated (and / or electrically insulated) from well 305 through dielectric layer 310, while the second group of epitaxial structures (e.g., 328B, 328C, 328E) can directly contact well 305.

[0371] According to some embodiments of this disclosure, well 305 is formed having a first conductivity type (e.g., p-type), sometimes referred to as p-well (PW) 305, while one of the epitaxial structures (e.g., 328F) is formed having the same first conductivity type (p-type), and the remaining epitaxial structures (e.g., 328A-E) are formed having a second, opposite conductivity type (e.g., n-type). Epitaxial structure 328F can have a higher doping concentration than p-well 305. All gate structures 314 to 326 can be electrically coupled to a supply voltage (e.g., VSS), for example, to turn off the transistor channel. Similar to ROM cell 100 ( Figure 1 The p-type epitaxial structure 328F and p-well 305 can be operatively used together as a common positive terminal for ROM cells 410 to 450, while each n-type epitaxial structure 328A-E can be operatively used as a negative terminal for an individual ROM cell 410 to 450. As will be discussed below, the common positive terminal of ROM cells 410 to 450 can be coupled to a common bit line BL, and the negative terminal of each ROM cell 410 to 450 can be coupled to an individual word line WL. Furthermore, the positive and negative terminals of each ROM cell 410 to 450 can be electrically coupled to each other or insulated from each other, based on the required logic state to be programmed into the ROM cells 410 to 450.

[0372] The layout 300 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 330A, 330B, 330C, 330D, 330E, and 330F, respectively. Generally, each source / drain contact structure 330A to 330F is positioned above a corresponding one of the epitaxial structures 328A to 328F, as shown below. Figure 4 As shown in the diagram, source / drain contact structures 330A to 330F (formed from a metallic material, such as copper, tungsten, cobalt, etc.) are each disposed to electrically couple corresponding epitaxial structures 328A to 328F to interconnect structures 344-354 formed in the upper metallization layer via via structures 339 (sometimes referred to as VD). For example, layout 300 further includes patterns for forming a plurality of via structures 339 to electrically connect the lower source / drain contact structures 330A to 330F to the upper interconnect structures 344 to 354. Similarly, layout 300 further includes patterns for forming a plurality of other via structures 333 (each sometimes referred to as VG) to electrically connect corresponding lower gate structures 314 to 326 to the upper interconnect structure 340. Layout 300 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. The source / drain contact structures 330A-F, via structures 333 and 339 are sometimes referred to as middle-end-of-line (MEOL) processes, and the interconnect structures in the metallization layer are sometimes referred to as back-end-of-line (BEOL) processes.

[0373] exist Figures 3 to 4In the illustrative example, gate structures 314 to 326 can be coupled via individual via structures 333 to an interconnect structure 340 formed in a bottommost metallization layer M0 (sometimes referred to as M0 track 340). In some embodiments, the M0 track 340 is configured to carry (or couple) a supply voltage (e.g., VSS), which electrically connects gate structures 314 to 326 to the supply voltage (e.g., VSS). Source / drain contact structures 330A to 330F can be coupled via individual via structures 339 to other M0 tracks 344, 346, 348, 350, 352, and 354. M0 tracks 344, 346, 348, 350, and 352 can be further coupled to individual interconnect structures 360, 362, 364, 366, and 368 in the next bottommost metallization layer M1 (sometimes referred to as M1 tracks 360, 362, 364, 366, and 368) via individual via structures. In some embodiments, M1 tracks 360, 362, 364, 366, and 368 are respectively configured as (or coupled to) word lines WL0, WL1, WL2, WL3, and WL4, while M0 track 354 is configured as (or coupled to) common bit line BL.

[0374] In some embodiments, when forming the above interconnection structure (e.g., M0 tracks 340-354, M1 tracks 360-368), ROM cells 410, 420, 430, 440, and 450 ( Figure 4 ROM unit 410 is formed based on epitaxial structure 328A, one of dielectric layers 310, p-well 305, and epitaxial structure 328F. ROM unit 420 is formed based on epitaxial structure 328B, p-well 305, and epitaxial structure 328F. ROM unit 430 is formed based on epitaxial structure 328C, p-well 305, and epitaxial structure 328F. ROM unit 440 is formed based on epitaxial structure 328D, another of dielectric layers 310, p-well 305, and epitaxial structure 328F, and ROM unit 450 is formed based on epitaxial structure 328E, p-well 305, and epitaxial structure 328F.

[0375] Specifically, epitaxial structures 328A and 328F (together with p-well 305) can serve as the negative and positive terminals of ROM unit 410. Epitaxial structures 328B and 328F (together with p-well 305) can serve as the negative and positive terminals of ROM unit 420. Epitaxial structures 328C and 328F (together with p-well 305) can serve as the negative and positive terminals of ROM unit 430. Epitaxial structures 328D and 328F (together with p-well 305) can serve as the negative and positive terminals of ROM unit 440, and epitaxial structures 328E and 328F (together with p-well 305) can serve as the negative and positive terminals of ROM unit 450.

[0376] Dielectric layer 310 is located between epitaxial structure 328A and p-well 305, and ROM cell 410 can be formed as a non-connected diode. For example, epitaxial structure 328A is electrically insulated from each other by dielectric layer 310 and p-well 305. Similarly, assuming dielectric layer 310 is located between epitaxial structure 328D and p-well 305, ROM cell 440 can be formed as a non-connected diode. Although in Figure 4 In the cross-sectional view, dielectric layer 310 is schematically shown having its own sidewalls aligned with the corresponding epitaxial structures (e.g., 328A, 328D). It should be understood that dielectric layer 310 may extend further (in the X direction) than the corresponding epitaxial structures (e.g., 328A, 328D). On the other hand, each epitaxial structure 328B, 328C, and 328E directly contacts p-well 305, thus forming ROM cells 420, 430, and 450 as connection diodes, respectively. In some embodiments, the non-connection diodes may be associated with logic 0, and the connection diodes may be associated with logic 1. Finally, during formation, ROM cells 410, 420, 430, 440, and 450 may be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0377] Next, see Figure 5 and Figure 6 The figures along line B-B' (or) are shown respectively. Figure 3 A cross-sectional view of the epitaxial structure 328A and along line C-C' (or Figure 3 A cross-sectional view of the epitaxial structure (328C) in the image. Figure 5In this embodiment, the epitaxial structure 328A is physically separated from the p-well 305, resulting in electrical insulation between the epitaxial structure 328A and the p-well 305. Furthermore, in some embodiments, the epitaxial structure 328A is electrically coupled to the word line WL0 through the source / drain contact structure 330A and the corresponding via structure 339, while the p-well 305 is electrically coupled to the common bit line BL through the epitaxial structure 328F, the source / drain contact structure 330F, and the corresponding via structure 339. Figure 4 In some embodiments, the source / drain contact structure 330A can be electrically insulated by the dielectric layer 310 and the p-well 305. Figure 6 In the p-well 305, the common bit line BL is electrically coupled through the epitaxial structure 328F, the source / drain contact structure 330F, and the corresponding through-hole structure 339. Figure 4 The epitaxial structure 328C is electrically coupled to the word line WL2 through the source / drain contact structure 330C and the corresponding via structure 339. Furthermore, the epitaxial structure 328C can directly contact the p-well 305. In some embodiments, the source / drain contact structure 330C can be electrically insulated from the p-well 305 through another dielectric layer 310.

[0378] Figure 7 An example layout 700 is shown configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 8 , Figure 9 and Figure 10 Cross-sectional views of the memory array formed based on layout 700 are shown.

[0379] For example, Figure 8 This shows a mixed cross-sectional view of the memory array that is tangent to or parallel to line A-A' (e.g., in the X direction). Figure 9 A cross-sectional view of a memory array cut along line B-B' (e.g., the Y direction) is shown, and Figure 10 This diagram shows a cross-sectional view of a memory array cut along line C-C' (e.g., the Y direction). As disclosed herein, the term "mixed cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 7 layout and Figures 8 to 10 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0380] First, refer to Figure 7 The layout 700 includes, respectively, for forming a well 705, one or more dielectric layers 710 (in... Figures 8 to 9The pattern of the active region 712 and gate structures 714, 716, 718, 720, 722, 724, and 726 is shown better in a cross-sectional view. In some embodiments, the well 705 and the active region 712 may extend along a first lateral direction (e.g., the X direction), while the gate structures 714 to 726 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, the gate structures 714 to 726 may each span the active region 712. The gate structures 714 to 726 may each correspond to an active (e.g., a metal) gate structure. For example, the gate structures 714 to 726 may each be formed as a polysilicon gate structure (sometimes referred to as a dummy gate structure) and then replaced with a corresponding metal gate structure (sometimes referred to as an active gate structure). The well 705, dielectric layer 710, active region 712, and gate structures 714 to 726 formed along the main surface of the substrate are sometimes referred to as partial front-end process (FEOL).

[0381] exist Figures 7 to 10 In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 810 to 850 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 810 to 850 of the memory array (formed by layout 700) can be formed as any various other transistor structures while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 712 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack are retained and covered by each gate structure 714 to 726, while other portions are replaced by a plurality of epitaxial structures 728A-F. The retained portions of the semiconductor structures can be configured as channels of the corresponding transistors, and the epitaxial structures 728A-F coupling the two ends of the channels (e.g., along the X direction) can be configured as source / drain structures of the transistors, and the partial gate structures covering (e.g., spanning) the retained portions of the semiconductor structures can be configured as gate terminals of the transistors.

[0382] exist Figures 7 to 8In this configuration, epitaxial structures 728A, 728B, 728C, 728D, 728E, and 728F (formed in the active region 712) and gate structures 714 to 726 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 728A is located between gate structures 714 and 716, epitaxial structure 728B is located between gate structures 716 and 718, epitaxial structure 728C is located between gate structures 718 and 720, epitaxial structure 728D is located between gate structures 720 and 722, epitaxial structure 728E is located between gate structures 722 and 724, and epitaxial structure 728F is located between gate structures 726 (not shown). Furthermore, ROM cells 810 to 850 are programmed using different logic states. The first group of epitaxial structures (e.g., 728A, 728D) can be physically separated (and / or electrically insulated) from well 705 through dielectric layer 710, while the second group of epitaxial structures (e.g., 728B, 728C, 728E) can directly contact well 705.

[0383] According to some embodiments of this disclosure, well 705 is formed having a first conductivity type (e.g., n-type), sometimes referred to as an n-well (n-well, NW) 705, while one of the epitaxial structures (e.g., 728F) is formed having the same first conductivity type (n-type), and the remaining epitaxial structures (e.g., 728A-E) are formed having a second, opposite conductivity type (e.g., p-type). Epitaxial structure 728F can have a higher doping concentration than n-well 705. All gate structures 714 to 726 can be electrically coupled to a supply voltage (e.g., VDD), for example, to turn off the transistor channel. Similar to ROM cell 200 ( Figure 2 The n-type epitaxial structure 728F and n-well 705 can be operatively used together as a common negative terminal for ROM cells 810 to 850, while each p-type epitaxial structure 728A-E can be operatively used as a positive terminal for an individual ROM cell 810 to 850. As will be discussed below, the common negative terminal of ROM cells 810 to 850 can be coupled to a common bit line BL, and the positive terminal of each ROM cell 810 to 850 can be coupled to an individual word line WL. Furthermore, the positive and negative terminals of each ROM cell 810 to 850 can be electrically coupled to each other or insulated from each other, based on the required logic state to be programmed into the ROM cells 810 to 850.

[0384] The layout 700 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 730A, 730B, 730C, 730D, 730E, and 730F, respectively. Generally, each source / drain contact structure 730A to 730F is positioned above a corresponding one of the epitaxial structures 728A to 728F, as shown below. Figure 8 As shown in the diagram, source / drain contact structures 730A to 730F (formed from a metallic material, such as copper, tungsten, cobalt, etc.) are each disposed to electrically couple corresponding epitaxial structures 728A to 728F to interconnect structures 744 to 754 formed in the upper metallization layer via via structures 739 (sometimes referred to as VD). For example, layout 700 further includes patterns for forming a plurality of via structures 739 to electrically connect the lower source / drain contact structures 730A to 730F to the upper interconnect structures 744 to 754. Similarly, layout 700 further includes patterns for forming a plurality of other via structures 733 (each sometimes referred to as VG) to electrically connect corresponding lower gate structures 314 to 326 to the upper interconnect structure 740. Layout 700 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. The source / drain contact structures 730A-F, via structures 733 and 739 are sometimes referred to as partial middle-stage processes (MEOL), and the interconnect structures in the metallization layer are sometimes referred to as partial back-end processes (BEOL).

[0385] exist Figures 7 to 8 In the illustrative example, gate structures 714 to 726 can be coupled via individual via structures 733 to an interconnect structure 740 formed in a bottommost metallization layer M0 (sometimes referred to as M0 track 740). In some embodiments, the M0 track 740 is configured to carry (or couple) a supply voltage (e.g., VDD), electrically connecting gate structures 714 to 726 to the supply voltage (e.g., VDD). Source / drain contact structures 730A to 730F can be coupled via individual via structures 739 to other M0 tracks 744, 746, 748, 750, 752, and 754. M0 tracks 744, 746, 748, 750, and 752 can further be coupled to individual interconnect structures 760, 762, 764, 766, and 768 in the next bottommost metallization layer M1 (sometimes referred to as M1 tracks 760, 762, 764, 766, and 768) via individual via structures. In some embodiments, M1 tracks 760, 762, 764, 766, and 768 are configured as (or coupled to) word lines WL0, WL1, WL2, WL3, and WL4, respectively, while M0 track 754 is configured as (or coupled to) a common bit line BL.

[0386] In some embodiments, when forming the above interconnection structure (e.g., M0 tracks 740-754, M1 tracks 760-768), ROM cells 810, 820, 830, 840, and 850 ( Figure 8 ROM unit 810 is formed based on epitaxial structure 728A, one of dielectric layers 710, n-well 705, and epitaxial structure 728F. ROM unit 820 is formed based on epitaxial structure 728B, n-well 705, and epitaxial structure 728F. ROM unit 830 is formed based on epitaxial structure 728C, n-well 705, and epitaxial structure 728F. ROM unit 840 is formed based on epitaxial structure 728D, another of dielectric layers 710, n-well 705, and epitaxial structure 728F, and ROM unit 850 is formed based on epitaxial structure 728E, n-well 705, and epitaxial structure 728F.

[0387] Specifically, epitaxial structures 728A and 728F (together with n-well 705) can serve as the positive and negative terminals of ROM unit 810. Epitaxial structures 728B and 728F (together with n-well 705) can serve as the positive and negative terminals of ROM unit 820. Epitaxial structures 728C and 728F (together with n-well 705) can serve as the positive and negative terminals of ROM unit 830. Epitaxial structures 728D and 728F (together with n-well 705) can serve as the positive and negative terminals of ROM unit 840, and epitaxial structures 728E and 728F (together with n-well 705) can serve as the positive and negative terminals of ROM unit 850.

[0388] A dielectric layer 710 is interposed between the epitaxial structure 728A and the n-well 705, and the ROM cell 810 can be formed as a non-connected diode. For example, the epitaxial structure 728A and the n-well 705 are electrically insulated from each other through the dielectric layer 710. Similarly, assuming the dielectric layer 710 is interposed between the epitaxial structure 728D and the n-well 705, the ROM cell 840 can be formed as a non-connected diode. Although in Figure 8In the cross-sectional view, dielectric layer 710 is schematically shown having its own sidewalls aligned with the corresponding epitaxial structures (e.g., 728A, 728D). It should be understood that dielectric layer 710 may extend further (in the X direction) than the corresponding epitaxial structures (e.g., 728A, 728D). On the other hand, each epitaxial structure 728B, 728C, and 728E directly contacts n-well 705, thus forming ROM cells 820, 830, and 850 as connection diodes, respectively. In some embodiments, the non-connection diodes may be associated with logic 0, and the connection diodes may be associated with logic 1. Finally, ROM cells 810, 820, 830, 840, and 850 can be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0389] Next, see Figure 9 and Figure 10 The figures along line B-B' (or) are shown respectively. Figure 7 A cross-sectional view of the epitaxial structure 728A and along line C-C' (or Figure 7 A cross-sectional view of the epitaxial structure (728C) in the image. Figure 9 In this embodiment, the epitaxial structure 728A is physically separated from the n-well 705, resulting in electrical insulation between the epitaxial structure 728A and the n-well 705. Furthermore, in some embodiments, the epitaxial structure 728A is electrically coupled to the word line WL0 through the source / drain contact structure 730A and the corresponding via structure 739, while the n-well 705 is electrically coupled to the common bit line BL through the epitaxial structure 728F, the source / drain contact structure 730F, and the corresponding via structure 739. Figure 8 In some embodiments, the source / drain contact structure 730A can be electrically insulated by the dielectric layer 710 and the n-well 705. Figure 10 In the n-well 705, the common bit line BL is electrically coupled through the epitaxial structure 728F, the source / drain contact structure 730F, and the corresponding through-hole structure 739. Figure 8 The epitaxial structure 728C is electrically coupled to the word line WL2 through the source / drain contact structure 730C and the corresponding via structure 739. Furthermore, the epitaxial structure 728C can directly contact the n-well 705. In some embodiments, the source / drain contact structure 730C can be electrically insulated from the n-well 705 through another dielectric layer 710.

[0390] Figure 11 An example layout 1100 is shown configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 12 , Figure 13 and Figure 14 Cross-sectional views of the memory array formed based on layout 1100 are shown.

[0391] For example, Figure 12 This shows a mixed cross-sectional view of the memory array that is tangent to or parallel to line A-A' (e.g., in the X direction). Figure 13 A cross-sectional view of a memory array cut along line B-B' (e.g., the Y direction) is shown, and Figure 14 This diagram shows a cross-sectional view of a memory array cut along line C-C' (e.g., the Y direction). As disclosed herein, the term "mixed cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 11 layout and Figures 12 to 14 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0392] First, refer to Figure 11 The layout 1100 includes, respectively, for forming wells 1105, one or more dielectric layers 1110 (in... Figures 13 to 14 The pattern of active region 1112 and gate structures 1114, 1116, 1118, 1120, 1122, 1124, and 1126 is shown in a cross-sectional view (better illustrated in the image). In some embodiments, well 1105 and active region 1112 may extend along a first lateral direction (e.g., the X direction), while gate structures 1114 to 1126 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, gate structures 1114 to 1126 may each span active region 1112. Gate structures 1114 to 1126 may each correspond to an active (e.g., a metal) gate structure. For example, gate structures 1114 to 1126 may each be formed as a polysilicon gate structure (sometimes referred to as a dummy gate structure) and then replaced with a corresponding metal gate structure (sometimes referred to as an active gate structure). The well 1105, dielectric layer 1110, active region 1112, and gate structures 1114 to 1126 formed along the main surface of the substrate are sometimes referred to as partial front-end process (FEOL).

[0393] exist Figures 11 to 14In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 1210 to 1250 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 1210 to 1250 of the memory array (formed by layout 1100) can be formed as any various other transistor structures, while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 1112 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack covered by each gate structure 1114 to 1126 are retained, while other portions are replaced by a plurality of epitaxial structures 1128A-F. The reserved portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structures 1128A-F that couple the two ends of the channel (e.g., along the X direction) can be configured as the source / drain structure of the transistor, and the partial gate structures 1114 to 1126 that cover (e.g., span) the reserved portion of the semiconductor structure can be configured as the gate termination of the transistor.

[0394] exist Figures 11 to 12 In this configuration, epitaxial structures 1128A, 1128B, 1128C, 1128D, 1128E, and 1128F (formed in the active region 1112) and gate structures 1114 to 1126 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 1128A is located between gate structures 1114 and 1116, epitaxial structure 1128B is located between gate structures 1116 and 1118, epitaxial structure 1128C is located between gate structures 1118 and 1120, epitaxial structure 1128D is located between gate structures 1120 and 1122, epitaxial structure 1128E is located between gate structures 1122 and 1124, and epitaxial structure 1128F is located between gate structures (not shown) and gate structure 1126. Furthermore, ROM cells 1210 to 1250 are programmed using different logic states. A first group of epitaxial structures (e.g., 1128A, 1128D) can be electrically insulated from the upper interconnect structures 1144, 1150, which are individual character lines WL, and a second group of epitaxial structures (e.g., 1128B, 1128C, 1128E) can be electrically coupled to the upper interconnect structures 1146, 1148, and 1152, which are individual character lines WL. In some embodiments, all epitaxial structures 1128A to 1128F can contact well 1105.

[0395] According to some embodiments of this disclosure, well 1105 is formed having a first conductivity type (e.g., p-type), sometimes referred to as p-well (PW) 1105, while one of the epitaxial structures (e.g., 1128F) is formed having the same first conductivity type (p-type), and the remaining epitaxial structures (e.g., 1128A-E) are formed having a second, opposite conductivity type (e.g., n-type). Epitaxial structure 1128F can have a higher doping concentration than p-well 1105. All gate structures 1114 to 1126 can be electrically coupled to a supply voltage (e.g., VSS), for example, to turn off the transistor channel. Similar to ROM cell 100 ( Figure 1 The p-type epitaxial structure 1128F and p-well 1105 can be operatively used together as a common positive terminal for ROM cells 1210 to 1250, while each n-type epitaxial structure 1128A-E can be operatively used as a negative terminal for an individual ROM cell 1210 to 1250. As will be discussed below, the common positive terminal for ROM cells 1210 to 1250 can be coupled to a common bit line BL, and the negative terminal for each ROM cell 1210 to 1250 can be selectively coupled to an individual word line WL. Furthermore, the negative terminal for each ROM cell 1210 to 1250 can be electrically coupled to an individual word line WL or insulated from an individual word line WL, based on the required logic state to be programmed into the ROM cell 1210 to 1250.

[0396] The layout 1100 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 1130A, 1130B, 1130C, 1130D, 1130E, and 1130F, respectively. Generally, each source / drain contact structure 1130A to 1130F is positioned above a corresponding one of the epitaxial structures 1128A to 1128F, as shown below. Figure 12 As shown in the diagram. Source / drain contact structures 1130B, 1130C, 1130E, and 1130F in source / drain contact structures 1130A to 1130F (formed from metallic materials such as copper, tungsten, cobalt, etc.) are each configured to electrically couple corresponding epitaxial structures 1128B, 1128C, 1128E, and 1128F to interconnect structures 1146, 1148, 1152, and 1154 formed in the upper metallization layer via via structures 1139 (sometimes referred to as VD). For example, layout 1100 further includes patterns for forming a plurality of via structures 1139 to electrically connect the lower source / drain contact structures 1130B, 1130C, 1130E, and 1130F to the upper interconnect structures 1146, 1148, 1152, and 1154. Figures 11 to 14In the example, epitaxial structures 1128B, 1128C, 1128E and 1128F are connected to individual via structures 1139, while epitaxial structures 1128A and 1128D are not connected to via structures 1139.

[0397] Layout 1100 further includes patterns for forming a plurality of other via structures 1133 (each sometimes referred to as VG) to electrically connect the corresponding lower gate structures 1114 to 1126 to the upper interconnect structure 1140. Layout 1100 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. Source / drain contact structures 1130A-F, via structures 1133 and 1139 are sometimes referred to as partial middle-of-line (MEOL) processes, and the interconnect structures in the metallization layer are sometimes referred to as partial back-of-line (BEOL) processes.

[0398] exist Figures 11 to 12 In the illustrative example, gate structures 1114 to 1126 can be coupled via individual via structures 1133 to an interconnect structure 1140 formed in a bottommost metallization layer M0 (sometimes referred to as M0 track 1140). In some embodiments, the M0 track 1140 is configured to carry (or couple) a supply voltage (e.g., VSS), which electrically connects gate structures 1114 to 1126 to the supply voltage (e.g., VSS). Source / drain contact structures 1130B, 1130C, 1130E, and 1130F can be coupled via individual via structures 1139 to other M0 tracks 1146, 1148, 1152, and 1154. M0 tracks 1144, 1146, 1148, 1150, and 1152 can be further coupled to individual interconnect structures 1160, 1162, 1164, 1166, and 1168 in the next bottommost metallization layer M1 (sometimes referred to as M1 tracks 1160, 1162, 1164, 1166, and 1168) via individual via structures. In some embodiments, M1 tracks 1160, 1162, 1164, 1166, and 1168 are respectively configured as (or coupled to) word lines WL0, WL1, WL2, WL3, and WL4, while M0 track 1154 is configured as (or coupled to) common bit line BL.

[0399] In some embodiments, when forming the above-described interconnection structure (e.g., M0 tracks 1140-1154, M1 tracks 1160-1168), ROM cells 1210, 1220, 1230, 1240, and 1250 can be configured. Figure 12ROM units are programmed as follows: ROM unit 1210 is formed based on epitaxial structure 1128A, p-well 1105, and epitaxial structure 1128F. ROM unit 1220 is formed based on epitaxial structure 1128B, p-well 1105, and epitaxial structure 1128F. ROM unit 1230 is formed based on epitaxial structure 1128C, p-well 1105, and epitaxial structure 1128F. ROM unit 1240 is formed based on epitaxial structure 1128D, p-well 1105, and epitaxial structure 1128F, and ROM unit 1250 is formed based on epitaxial structure 1128E, p-well 1105, and epitaxial structure 1128F.

[0400] Specifically, epitaxial structures 1128A and 1128F (together with p-well 1105) can serve as the negative and positive terminals of ROM unit 1210. Epitaxial structures 1128B and 1128F (together with p-well 1105) can serve as the negative and positive terminals of ROM unit 1220. Epitaxial structures 1128C and 1128F (together with p-well 1105) can serve as the negative and positive terminals of ROM unit 1230. Epitaxial structures 1128D and 1128F (together with p-well 1105) can serve as the negative and positive terminals of ROM unit 1240, and epitaxial structures 1128E and 1128F (together with p-well 1105) can serve as the negative and positive terminals of ROM unit 1250.

[0401] Without a via structure 1139 formed between the M0 track 1144 (connecting word line WL0) and the source / drain contact structure 1130A, the ROM cell 1210 can be formed as a non-connected diode. For example, by not forming a via structure 1139 on the source / drain contact structure 1130A, the source / drain contact structure 1130A is electrically insulated from the M0 track 1144 or the word line WL0. Similarly, assuming that without a via structure 1139 formed between the source / drain contact structure 1130D and the M0 track 1150 (connecting word line WL3), the ROM cell 1240 can be formed as a non-connected diode. On the other hand, epitaxial structures 1128B, 1128C, and 1128E are coupled to word lines WL1 (through M0 track 1146 and via structure 1139), WL2 (through M0 track 1148 and via structure 1139), and WL4 (through M0 track 1152 and via structure 1139), respectively, thus forming ROM cells 1220, 1230, and 1250 as connection diodes. In some embodiments, the non-connection diodes may be associated with logic 0, and the connection diodes may be associated with logic 1. Finally, ROM cells 1210, 1220, 1230, 1240, and 1250 can be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0402] Next, see Figure 13 and Figure 14 The figures along line B-B' (or) are shown respectively. Figure 11 A cross-sectional view of the epitaxial structure 1128A and along line C-C' (or Figure 11 A cross-sectional view of the epitaxial structure 1128C in the image. Figure 13 In the p-well 1105, the common bit line BL is electrically coupled through the epitaxial structure 1128F, the source / drain contact structure 1130F, and the corresponding through-hole structure 1139. Figure 12 The epitaxial structure 1128A is electrically decoupled from the character line WL0 through the absence of a via structure 1139. Furthermore, the epitaxial structure 1128A can directly contact the p-well 1105. In some embodiments, the source / drain contact structure 1130A can be electrically insulated from the p-well 1105 through a dielectric layer 1110. Figure 14 In the p-well 1105, the common bit line BL is electrically coupled through the epitaxial structure 1128F, the source / drain contact structure 1130F, and the corresponding through-hole structure 1139. Figure 12 The epitaxial structure 1128C is electrically coupled to the word line WL2 through the source / drain contact structure 1130C and the corresponding via structure 1139. Furthermore, the epitaxial structure 1128C can directly contact the p-well 1105. In some embodiments, the source / drain contact structure 1130C can be electrically insulated from the p-well 1105 through another dielectric layer 1110.

[0403] Figure 15 An example layout 1500 is shown configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 16 , Figure 17 and Figure 18 Cross-sectional views of the memory array formed based on layout 1500 are shown.

[0404] For example, Figure 16 This shows a mixed cross-sectional view of the memory array that is tangent to or parallel to line A-A' (e.g., in the X direction). Figure 17 A cross-sectional view of a memory array cut along line B-B' (e.g., the Y direction) is shown, and Figure 18 This diagram shows a cross-sectional view of a memory array cut along line C-C' (e.g., the Y direction). As disclosed herein, the term "mixed cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 15 layout and Figures 16 to 18 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0405] First, refer to Figure 15 The layout 1500 includes, respectively, for forming a well 1505, one or more dielectric layers 1510 (in... Figures 16 to 18 The pattern of active region 1512 and gate structures 1514, 1516, 1518, 1520, 1522, 1524, and 1526 is shown in a cross-sectional view (better illustrated in the image). In some embodiments, well 1505 and active region 1512 may extend along a first lateral direction (e.g., the X direction), while gate structures 1514 to 1526 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, gate structures 1514 to 1526 may each span active region 1512. Gate structures 1514 to 1526 may each correspond to an active (e.g., a metal) gate structure. For example, gate structures 1514 to 1526 may each be formed as a polysilicon gate structure (sometimes referred to as a dummy gate structure) and then replaced with a corresponding metal gate structure (sometimes referred to as an active gate structure). The well 1505, dielectric layer 1510, active region 1512, and gate structures 1514 to 1526 formed along the main surface of the substrate are sometimes referred to as partial front-end process (FEOL).

[0406] exist Figures 15 to 18 In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 1610 to 1650 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 1610 to 1650 of the memory array (formed by layout 1500) can be formed as any various other transistor structures while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 1512 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack covered by each gate structure 1514 to 1526 are retained, while other portions are replaced by a plurality of epitaxial structures 1528A-F. The reserved portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structures 1528A-F that couple the two ends of the channel (e.g., along the X direction) can be configured as the source / drain structure of the transistor, and the partial gate structures 1514 to 1526 that cover (e.g., span) the reserved portion of the semiconductor structure can be configured as the gate termination of the transistor.

[0407] exist Figures 15 to 16In this configuration, epitaxial structures 1528A, 1528B, 1528C, 1528D, 1528E, and 1528F (formed in the active region 1512) and gate structures 1514 to 1526 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 1528A is located between gate structures 1514 and 1516, epitaxial structure 1528B is located between gate structures 1516 and 1518, epitaxial structure 1528C is located between gate structures 1518 and 1520, epitaxial structure 1528D is located between gate structures 1520 and 1522, epitaxial structure 1528E is located between gate structures 1522 and 1524, and epitaxial structure 1528F is located between gate structures (not shown) and gate structure 1526. Furthermore, ROM cells 1610 to 1650 are programmed using different logic states. A first group of epitaxial structures (e.g., 1528A, 1528D) can be electrically insulated from the upper interconnect structures 1544, 1550, which are individual character lines WL, and a second group of epitaxial structures (e.g., 1528B, 1528C, 1528E) can be electrically coupled to the upper interconnect structures 1546, 1548, and 1552, which are individual character lines WL. In some embodiments, all epitaxial structures 1528A to 1528F can contact well 1505.

[0408] According to some embodiments of this disclosure, well 1505 is formed having a first conductivity type (e.g., n-type), sometimes referred to as n-well (NW) 1505, while one of the epitaxial structures (e.g., 1528F) is formed having the same first conductivity type (n-type), and the remaining epitaxial structures (e.g., 1528A-E) are formed having a second, opposite conductivity type (e.g., p-type). Epitaxial structure 1528F can have a higher doping concentration than n-well 1505. All gate structures 1514 to 1526 can be electrically coupled to a supply voltage (e.g., VDD), for example, to turn off the transistor channel. Similar to ROM cell 200 ( Figure 2 The n-type epitaxial structure 1528F and n-well 1505 can be operatively used together as a common negative terminal for ROM cells 1610 to 1650, while each p-type epitaxial structure 1528A-E can be operatively used as a positive terminal for an individual ROM cell 1610 to 1650. As will be discussed below, the common negative terminal for ROM cells 1610 to 1650 can be coupled to a common bit line BL, and the positive terminal for each ROM cell 1610 to 1650 can be selectively coupled to an individual word line WL. Furthermore, the positive terminal for each ROM cell 1610 to 1650 can be electrically coupled to an individual word line WL or insulated from an individual word line WL, based on the required logic state to be programmed into the ROM cell 1610 to 1650.

[0409] The layout 1500 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 1530A, 1530B, 1530C, 1530D, 1530E, and 1530F, respectively. Generally, each source / drain contact structure 1530A to 1530F is positioned above a corresponding one of the epitaxial structures 1528A to 1528F, as shown below. Figure 16 As shown in the diagram. Source / drain contact structures 1530B, 1530C, 1530E, and 1530F in source / drain contact structures 1530A to 1530F (formed from metallic materials such as copper, tungsten, cobalt, etc.) are each configured to electrically couple corresponding epitaxial structures 1528B, 1528C, 1528E, and 1528F to interconnect structures 1546, 1548, 1552, and 1554 formed in the upper metallization layer via via structures 1539 (sometimes referred to as VD). For example, layout 1500 further includes patterns for forming a plurality of via structures 1539 to electrically connect the lower source / drain contact structures 1530B, 1530C, 1530E, and 1530F to the upper interconnect structures 1546, 1548, 1552, and 1554. Figures 15 to 18 In the example, epitaxial structures 1528B, 1528C, 1528E and 1528F are connected to individual via structures 1539, while epitaxial structures 1528A and 1528D are not connected to via structures 1539.

[0410] Layout 1500 further includes patterns for forming a plurality of other via structures 1533 (each sometimes referred to as VG) to electrically connect the corresponding lower gate structures 1514 to 1526 to the upper interconnect structure 1540. Layout 1500 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. Source / drain contact structures 1530A-F, via structures 1533 and 1539 are sometimes referred to as partial middle-end processes (MEOL), and the interconnect structures in the metallization layer are sometimes referred to as partial back-end processes (BEOL).

[0411] exist Figures 15 to 16In the illustrative example, gate structures 1514 to 1526 can be coupled via individual via structures 1533 to an interconnect structure 1540 formed in a bottommost metallization layer M0 (sometimes referred to as M0 track 1540). In some embodiments, the M0 track 1540 is configured to carry (or couple) a supply voltage (e.g., VDD), which electrically connects gate structures 1514 to 1526 to the supply voltage (e.g., VDD). Source / drain contact structures 1530B, 1530C, 1530E, and 1530F can be coupled via individual via structures 1539 to other M0 tracks 1546, 1548, 1552, and 1554. M0 tracks 1544, 1546, 1548, 1550, and 1552 can be further coupled to individual interconnect structures 1560, 1562, 1564, 1566, and 1568 in the next bottommost metallization layer M1 (sometimes referred to as M1 tracks 1560, 1562, 1564, 1566, and 1568) via individual via structures. In some embodiments, M1 tracks 1560, 1562, 1564, 1566, and 1568 are respectively configured as (or coupled to) word lines WL0, WL1, WL2, WL3, and WL4, while M0 track 1554 is configured as (or coupled to) common bit line BL.

[0412] In some embodiments, when forming the above interconnection structure (e.g., M0 tracks 1540-1554, M1 tracks 1560-1568), ROM cells 1610, 1620, 1630, 1640, and 1650 can be configured. Figure 16 ROM units are programmed as follows: ROM unit 1610 is formed based on epitaxial structure 1528A, n-well 1505, and epitaxial structure 1528F. ROM unit 1620 is formed based on epitaxial structure 1528B, n-well 1505, and epitaxial structure 1528F. ROM unit 1630 is formed based on epitaxial structure 1528C, n-well 1505, and epitaxial structure 1528F. ROM unit 1640 is formed based on epitaxial structure 1528D, n-well 1505, and epitaxial structure 1528F, and ROM unit 1650 is formed based on epitaxial structure 1528E, n-well 1505, and epitaxial structure 1528F.

[0413] Specifically, epitaxial structures 1528A and 1528F (together with n-well 1505) can serve as the positive and negative terminals of ROM unit 1610. Epitaxial structures 1528B and 1528F (together with n-well 1505) can serve as the positive and negative terminals of ROM unit 1620. Epitaxial structures 1528C and 1528F (together with n-well 1505) can serve as the positive and negative terminals of ROM unit 1630. Epitaxial structures 1528D and 1528F (together with n-well 1505) can serve as the positive and negative terminals of ROM unit 1640, and epitaxial structures 1528E and 1528F (together with n-well 1505) can serve as the positive and negative terminals of ROM unit 1650.

[0414] Without a via structure 1539 formed between the M0 track 1544 (connecting word line WL0) and the source / drain contact structure 1530A, the ROM cell 1610 can be formed as a non-connected diode. For example, by not forming a via structure 1539 on the source / drain contact structure 1530A, the source / drain contact structure 1530A is electrically insulated from the M0 track 1544 or the word line WL0. Similarly, assuming that without a via structure 1539 formed between the source / drain contact structure 1530D and the M0 track 1550 (connecting word line WL3), the ROM cell 1640 can be formed as a non-connected diode. On the other hand, epitaxial structures 1528B, 1528C, and 1528E are coupled to word lines WL1 (through M0 track 1546 and via structure 1539), WL2 (through M0 track 1548 and via structure 1539), and WL4 (through M0 track 1552 and via structure 1539), respectively, thus forming ROM cells 1620, 1630, and 1650 as connection diodes. In some embodiments, the non-connection diodes may be associated with logic 0, and the connection diodes may be associated with logic 1. Finally, ROM cells 1610, 1620, 1630, 1640, and 1650 can be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0415] Next, see Figure 17 and Figure 18 The figures along line B-B' (or) are shown respectively. Figure 15 A cross-sectional view of the epitaxial structure 1528A and along line C-C' (or Figure 15 A cross-sectional view of the epitaxial structure (1528C) in the image. Figure 17 In the n-well 1505, the common bit line BL is electrically coupled through the epitaxial structure 1528F, the source / drain contact structure 1530F, and the corresponding through-hole structure 1539. Figure 16The epitaxial structure 1528A is electrically decoupled from the character line WL0 through the absence of a via structure 1539. Furthermore, the epitaxial structure 1528A can directly contact the n-well 1505. In some embodiments, the source / drain contact structure 1530A can be electrically insulated from the n-well 1505 through a dielectric layer 1510. Figure 18 In the n-well 1505, the common bit line BL is electrically coupled through the epitaxial structure 1528F, the source / drain contact structure 1530F, and the corresponding through-hole structure 1539. Figure 16 The epitaxial structure 1528C is electrically coupled to the word line WL2 through the source / drain contact structure 1530C and the corresponding via structure 1539. Furthermore, the epitaxial structure 1528C can directly contact the n-well 1505. In some embodiments, the source / drain contact structure 1530C can be electrically insulated from the n-well 1505 through another dielectric layer 1510.

[0416] Figure 19 An example layout 1900 is shown configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 20 , Figure 21 and Figure 22 Cross-sectional views of the memory array formed based on layout 1900 are shown.

[0417] For example, Figure 20 This shows a mixed cross-sectional view of the memory array that is tangent to or parallel to line A-A' (e.g., in the X direction). Figure 21 A cross-sectional view of a memory array cut along line B-B' (e.g., the Y direction) is shown, and Figure 22 This diagram shows a cross-sectional view of a memory array cut along line C-C' (e.g., the Y direction). As disclosed herein, the term "mixed cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 19 layout and Figures 20 to 22 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0418] First, refer to Figure 19 The layout 1900 includes, respectively, for forming well 1905, one or more dielectric layers 1910 (in... Figures 21 to 22The pattern of active region 1912 and gate structures 1914, 1916, 1918, 1920, 1922, 1924, and 1926 is shown in a cross-sectional view (better illustrated in the figure). In some embodiments, well 1905 and active region 1912 may extend along a first lateral direction (e.g., the X direction), while gate structures 1914 to 1926 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, gate structures 1914 to 1926 may each span active region 1912. Gate structures 1914 to 1926 may each correspond to an active (e.g., metal) gate structure. For example, gate structures 1914 to 1926 may each be formed as a polysilicon gate structure (sometimes referred to as a dummy gate structure) and then replaced with a corresponding metal gate structure (sometimes referred to as an active gate structure). The well 1905, dielectric layer 1910, active region 1912, and gate structures 1914 to 1926 formed along the main surface of the substrate are sometimes referred to as partial front-end process (FEOL).

[0419] exist Figures 19 to 22 In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 2010 to 2050 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 2010 to 2050 of the memory array (formed by layout 1900) can be formed as any of various other transistor structures, while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 1912 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes multiple semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack covered by each gate structure 1914 to 1926 are retained, while other portions are replaced by multiple epitaxial structures 1928A-F. The reserved portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structure 1928A-F that couples the two ends of the channel (e.g., along the X direction) can be configured as the source / drain structure of the transistor, and the partial gate structure 1914 to 1926 that covers (e.g., spans) the reserved portion of the semiconductor structure can be configured as the gate terminal of the transistor.

[0420] exist Figures 19 to 20In this configuration, epitaxial structures 1928A, 1928B, 1928C, 1928D, 1928E, and 1928F (formed in the active region 1912) and gate structures 1914 to 1926 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 1928A is located between gate structures 1914 and 1916, epitaxial structure 1928B is located between gate structures 1916 and 1918, epitaxial structure 1928C is located between gate structures 1918 and 1920, epitaxial structure 1928D is located between gate structures 1920 and 1922, epitaxial structure 1928E is located between gate structures 1922 and 1924, and epitaxial structure 1928F is located between gate structures (not shown) and gate structure 1926. Furthermore, ROM cells 2010 to 2050 are programmed using different logic states. A first group of epitaxial structures (e.g., 1928A, 1928D) can be electrically insulated from the upper interconnect structures 1960, 1966, which are individual character lines WL, and a second group of epitaxial structures (e.g., 1928B, 1928C, 1928E) can be electrically coupled to the upper interconnect structures 1962, 1964, and 1968, which are individual character lines WL. In some embodiments, all epitaxial structures 1928A to 1928F can contact well 1905.

[0421] According to some embodiments of this disclosure, well 1905 is formed having a first conductivity type (e.g., p-type), sometimes referred to as p-well (PW) 1905, while one of the epitaxial structures (e.g., 1928F) is formed having the same first conductivity type (p-type), and the remaining epitaxial structures (e.g., 1928A-E) are formed having a second, opposite conductivity type (e.g., n-type). Epitaxial structure 1928F can have a higher doping concentration than p-well 1905. All gate structures 1914 to 1926 can be electrically coupled to a supply voltage (e.g., VSS), for example, to turn off the transistor channel. Similar to ROM cell 100 ( Figure 1 The p-type epitaxial structure 1928F and p-well 1905 can be operatively used together as a common positive terminal for ROM cells 2010 to 2050, while each n-type epitaxial structure 1928A-E can be operatively used as a negative terminal for an individual ROM cell 2010 to 2050. As will be discussed below, the common positive terminal of ROM cells 2010 to 2050 can be coupled to a common bit line BL, and the negative terminal of each ROM cell 2010 to 2050 can be selectively coupled to an individual word line WL. Furthermore, the negative terminal of each ROM cell 2010 to 2050 can be electrically coupled to an individual word line WL or insulated from an individual word line WL, based on the required logic state to be programmed into the ROM cell 2010 to 2050.

[0422] The layout 1900 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 1930A, 1930B, 1930C, 1930D, 1930E, and 1930F, respectively. Generally, each source / drain contact structure 1930A to 1930F is positioned above a corresponding one of the epitaxial structures 1928A to 1928F, as shown below. Figure 20 As shown in the diagram, source / drain contact structures 1930A to 1930F (formed from metallic materials such as copper, tungsten, cobalt, etc.) are each disposed to electrically couple corresponding epitaxial structures 1928A-F to interconnect structures 1944-1954 formed in the upper metallization layer via via structures 1939 (sometimes referred to as VD). For example, layout 1900 further includes a pattern for forming a plurality of via structures 1939 to electrically connect the lower source / drain contact structures 1930A to 1930F to the upper interconnect structures 1944-1954. Figures 19 to 20 In the example, epitaxial structures 1928A to 1928F are connected to individual through-hole structures 1939.

[0423] Layout 1900 further includes patterns for forming a plurality of other via structures 1933 (each sometimes referred to as VG) to electrically connect the corresponding lower gate structures 1914 to 1926 to the upper interconnect structure 1940. Layout 1900 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. Source / drain contact structures 1930A-F, via structures 1933 and 1939 are sometimes referred to as partial middle-of-line (MEOL) processes, and the interconnect structures in the metallization layer are sometimes referred to as partial back-of-line (BEOL) processes.

[0424] exist Figures 19 to 20In the illustrative example, gate structures 1914 to 1926 can be coupled via individual via structures 1933 to an interconnect structure 1940 formed in a bottommost metallization layer M0 (sometimes referred to as M0 track 1940). In some embodiments, the M0 track 1940 is configured to carry (or couple) a supply voltage (e.g., VSS), which electrically connects gate structures 1914 to 1926 to the supply voltage (e.g., VSS). Source / drain contact structures 1930A to 1930F can be coupled via individual via structures 1939 to other M0 tracks 1944, 1946, 1948, 1950, 1952, and 1954. M0 orbitals 1946, 1948, and 1952 can be further coupled to individual interconnect structures 1962, 1964, and 1968 in the next bottommost metallization layer M1 (sometimes referred to as M1 orbitals 1962, M1 orbitals 1964, and M1 orbitals 1968) via individual via structures 1943, while M0 orbital 1944 is isolated from M1 orbital 1960 (e.g., where no via structure 1943 is formed), and M0 orbital 1950 is isolated from M1 orbital 1966 (e.g., where no via structure 1943 is formed). The via structure 1943 is sometimes referred to as V0. In some embodiments, M1 tracks 1960, 1962, 1964, 1966, and 1968 are respectively configured as (or coupled to) character lines WL0, WL1, WL2, WL3, and WL4, while M0 track 1954 is configured as (or coupled to) common bit line BL.

[0425] In some embodiments, when forming the above-described interconnection structure (e.g., M0 tracks 1940-1954, M1 tracks 1960-1968), ROM cells 2010, 2020, 2030, 2040, and 2050 can be configured. Figure 20 ROM unit 2010 is formed based on epitaxial structure 1928A, p-well 1905, and epitaxial structure 1928F. ROM unit 2020 is formed based on epitaxial structure 1928B, p-well 1905, and epitaxial structure 1928F. ROM unit 2030 is formed based on epitaxial structure 1928C, p-well 1905, and epitaxial structure 1928F. ROM unit 2040 is formed based on epitaxial structure 1928D, p-well 1905, and epitaxial structure 1928F, and ROM unit 2050 is formed based on epitaxial structure 1928E, p-well 1905, and epitaxial structure 1928F.

[0426] Specifically, epitaxial structures 1928A and 1928F (together with p-well 1905) can serve as the negative and positive terminals of ROM unit 2010. Epitaxial structures 1928B and 1928F (together with p-well 1905) can serve as the negative and positive terminals of ROM unit 2020. Epitaxial structures 1928C and 1928F (together with p-well 1905) can serve as the negative and positive terminals of ROM unit 2030. Epitaxial structures 1928D and 1928F (together with p-well 1905) can serve as the negative and positive terminals of ROM unit 2040, and epitaxial structures 1928E and 1928F (together with p-well 1905) can serve as the negative and positive terminals of ROM unit 2050.

[0427] Since no via structure 1943 is formed between M0 track 1944 and M1 track 1960 (as word line WL0), ROM cell 2010 can be formed as a non-connected diode. For example, by not forming via structure 1943 on the source / drain contact structure 1930A, the source / drain contact structure 1930A is electrically insulated from the word line WL0. Similarly, assuming no via structure 1943 is formed between M0 track 1950 and M1 track 1966 (as word line WL3), ROM cell 2040 can be formed as a non-connected diode. On the other hand, epitaxial structures 1928B, 1928C, and 1928E are coupled to word lines WL1 (through M0 track 1946), WL2 (through M0 track 1948), and WL4 (through M0 track 1952), respectively, thus forming ROM cells 2020, 2030, and 2050 as connected diodes. In some embodiments, the non-connected diode may be associated with logic 0, and the connected diode may be associated with logic 1. Finally, during configuration, ROM cells 2010, 2020, 2030, 2040, and 2050 can be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0428] Next, see Figure 21 and Figure 22 The figures along line B-B' (or) are shown respectively. Figure 19 A cross-sectional view of the epitaxial structure in 1928A and along line C-C' (or Figure 19 A cross-sectional view of the epitaxial structure (1928C) in the image. Figure 21 In the p-well 1905, the common bit line BL is electrically coupled through the epitaxial structure 1928F, the source / drain contact structure 1930F, and the corresponding through-hole structure 1939. Figure 20By not forming a via structure 1943 on the epitaxial structure 1928A, the epitaxial structure 1928A is electrically decoupled from the word line WL0. Furthermore, the epitaxial structure 1928A can directly contact the p-well 1905. In some embodiments, the source / drain contact structure 1930A can be electrically insulated from the p-well 1905 through a dielectric layer 1910. Figure 22 In the p-well 1905, the common bit line BL is electrically coupled through the epitaxial structure 1928F, the source / drain contact structure 1930F, and the corresponding through-hole structure 1939. Figure 20 The epitaxial structure 1928C is electrically coupled to the word line WL2 through the source / drain contact structure 1930C, the corresponding via structure 1939, the M0 track 1948, and the corresponding via structure 1943. Furthermore, the epitaxial structure 1928C can directly contact the p-well 1905. In some embodiments, the source / drain contact structure 1930C can be electrically insulated from the p-well 1905 through another dielectric layer 1910.

[0429] Figure 23 An example layout 2300 is shown configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 24 , Figure 25 and Figure 26 Cross-sectional views of the memory array formed based on layout 2300 are shown.

[0430] For example, Figure 23 This shows a mixed cross-sectional view of the memory array that is tangent to or parallel to line A-A' (e.g., in the X direction). Figure 24 A cross-sectional view of a memory array cut along line B-B' (e.g., the Y direction) is shown, and Figure 25 This diagram shows a cross-sectional view of a memory array cut along line C-C' (e.g., the Y direction). As disclosed herein, the term "mixed cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 23 layout and Figures 24 to 26 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0431] First, refer to Figure 23 The layout 2300 includes, respectively, for forming wells 2305 and one or more dielectric layers 2310 (in... Figures 25 to 26The pattern of active region 2312 and gate structures 2314, 2316, 2318, 2320, 2322, 2324, and 2326 is shown better in a cross-sectional view. In some embodiments, well 2305 and active region 2312 may extend along a first lateral direction (e.g., the X direction), while gate structures 2314 to 2326 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, gate structures 2314 to 2326 may each span active region 2312. Gate structures 2314 to 2326 may each correspond to an active (e.g., a metal) gate structure. For example, gate structures 2314 to 2326 may each be formed as a polysilicon gate structure (sometimes referred to as a dummy gate structure) and then replaced with a corresponding metal gate structure (sometimes referred to as an active gate structure). The well 2305, dielectric layer 2310, active region 2312 and gate structures 2314 to 2326 formed along the main surface of the substrate are sometimes referred to as partial front-end process (FEOL).

[0432] exist Figures 23 to 26 In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 2410 to 2450 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 2410 to 2450 of the memory array (formed by layout 2300) can be formed as any of various other transistor structures, while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 2312 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes multiple semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack covered by each gate structure 2314 to 2326 are retained, while other portions are replaced by multiple epitaxial structures 2328A-F. The reserved portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structures 2328A-F that couple the two ends of the channel (e.g., along the X direction) can be configured as the source / drain structures of the transistor, and the partial gate structures 2314 to 2326 that cover (e.g., span) the reserved portion of the semiconductor structure can be configured as the gate termination of the transistor.

[0433] exist Figures 23 to 24In this configuration, epitaxial structures 2328A, 2328B, 2328C, 2328D, 2328E, and 2328F (formed in the active region 2312) and gate structures 2314 to 2326 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 2328A is located between gate structures 2314 and 2316, epitaxial structure 2328B is located between gate structures 2316 and 2318, epitaxial structure 2328C is located between gate structures 2318 and 2320, epitaxial structure 2328D is located between gate structures 2320 and 2322, epitaxial structure 2328E is located between gate structures 2322 and 2324, and epitaxial structure 2328F is located between gate structures (not shown) and gate structure 2326. Furthermore, ROM cells 2410 to 2450 are programmed using different logic states. A first group of epitaxial structures (e.g., 2328A, 2328D) can be electrically insulated from the upper interconnect structures 2360, 2366, which are individual character lines WL, and a second group of epitaxial structures (e.g., 2328B, 2328C, 2328E) can be electrically coupled to the upper interconnect structures 2362, 2364, and 2368, which are individual character lines WL. In some embodiments, all epitaxial structures 2328A to 2328F can contact well 2305.

[0434] According to some embodiments of this disclosure, well 2305 is formed having a first conductivity type (e.g., n-type), sometimes referred to as n-well (NW) 2305, while one of the epitaxial structures (e.g., 2328F) is formed having the same first conductivity type (n-type), and the remaining epitaxial structures (e.g., 2328A-E) are formed having a second, opposite conductivity type (e.g., p-type). Epitaxial structure 2328F can have a higher doping concentration than n-well 2305. All gate structures 2314 to 2326 can be electrically coupled to a supply voltage (e.g., VDD), for example, to turn off the transistor channel. Similar to ROM cell 200 ( Figure 2 The n-type epitaxial structure 2328F and the n-well 2305 can be operatively used together as a common negative terminal for ROM cells 2410 to 2450, while each p-type epitaxial structure 2328A-E can be operatively used as a positive terminal for an individual ROM cell 2410 to 2450. As will be discussed below, the common negative terminal of ROM cells 2410 to 2450 can be coupled to a common bit line BL, and the positive terminal of each ROM cell 2410 to 2450 can be selectively coupled to an individual word line WL. Furthermore, the positive terminal of each ROM cell 2410 to 2450 can be electrically coupled to an individual word line WL or insulated from an individual word line WL, based on the required logic state to be programmed into the ROM cell 2410 to 2450.

[0435] The layout 2300 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 2330A, 2330B, 2330C, 2330D, 2330E, and 2330F, respectively. Generally, each source / drain contact structure 2330A to 2330F is positioned above a corresponding one of the epitaxial structures 2328A to 2328F, as shown below. Figure 24 As shown in the diagram, source / drain contact structures 2330A to 2330F (formed from a metallic material, such as copper, tungsten, cobalt, etc.) are each disposed to electrically couple corresponding epitaxial structures 2328A to 2328F to interconnect structures 2344-2354 formed in the upper metallization layer via via structures 2339 (sometimes referred to as VD). For example, layout 2300 further includes a pattern for forming a plurality of via structures 2339 to electrically connect the lower source / drain contact structures 2330A to 2330F to the upper interconnect structures 2344-2354. Figures 23 to 24 In the example, epitaxial structures 2328A and 2328F are connected to individual through-hole structures 2339.

[0436] Layout 2300 further includes patterns for forming a plurality of other via structures 2333 (each sometimes referred to as VG) to electrically connect the corresponding lower gate structures 2314 to 2326 to the upper interconnect structure 2340. Layout 2300 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. Source / drain contact structures 2330A-F, via structures 2333 and via structure 2339 are sometimes referred to as partial middle-of-line (MEOL) processes, and the interconnect structures in the metallization layer are sometimes referred to as partial back-of-line (BEOL) processes.

[0437] exist Figures 23 to 24In the illustrative example, gate structures 2314 to 2326 can be coupled via individual via structures 2333 to an interconnect structure 2340 formed in a bottommost metallization layer M0 (sometimes referred to as M0 track 2340). In some embodiments, the M0 track 2340 is configured to carry (or couple) a supply voltage (e.g., VDD), which electrically connects gate structures 2314 to 2326 to the supply voltage (e.g., VDD). Source / drain contact structures 2330A to 2330F can be coupled via individual via structures 2339 to other M0 tracks 2344, 2346, 2348, 2350, 2352, and 2354. M0 orbitals 2346, 2348, and 2352 can be further coupled to individual interconnect structures 2362, 2364, and 2368 in the next bottommost metallization layer M1 (sometimes referred to as M1 orbitals 2362, M1 orbitals 2364, and M1 orbitals 2368) via individual via structures 2343, while M0 orbital 2344 is isolated from M1 orbital 2360 (e.g., where no via structure 2343 is formed), and M0 orbital 2350 is isolated from M1 orbital 2366 (e.g., where no via structure 2343 is formed). The via structure 2343 is sometimes referred to as V0. In some embodiments, M1 tracks 2360, 2362, 2364, 2366, and 2368 are respectively configured as (or coupled to) character lines WL0, WL1, WL2, WL3, and WL4, while M0 track 2354 is configured as (or coupled to) common bit line BL.

[0438] In some embodiments, when forming the above-described interconnection structure (e.g., M0 tracks 2340-2354, M1 tracks 2360-2368), ROM cells 2410, 2420, 2430, 2440, and 2450 can be configured. Figure 24 ROM unit 2410 is formed based on epitaxial structure 2328A, n-well 2305, and epitaxial structure 2328F. ROM unit 2420 is formed based on epitaxial structure 2328B, n-well 2305, and epitaxial structure 2328F. ROM unit 2430 is formed based on epitaxial structure 2328C, n-well 2305, and epitaxial structure 2328F. ROM unit 2440 is formed based on epitaxial structure 2328D, n-well 2305, and epitaxial structure 2328F, and ROM unit 2450 is formed based on epitaxial structure 2328E, n-well 2305, and epitaxial structure 2328F.

[0439] Specifically, epitaxial structures 2328A and 2328F (together with n-well 2305) can serve as the positive and negative terminals of ROM unit 2410. Epitaxial structures 2328B and 2328F (together with n-well 2305) can serve as the negative and positive terminals of ROM unit 2420. Epitaxial structures 2328C and 2328F (together with n-well 2305) can serve as the negative and positive terminals of ROM unit 2430. Epitaxial structures 2328D and 2328F (together with n-well 2305) can serve as the negative and positive terminals of ROM unit 2440, and epitaxial structures 2328E and 2328F (together with n-well 2305) can serve as the negative and positive terminals of ROM unit 2450.

[0440] Since no via structure 2343 is formed between M0 track 2344 and M1 track 2360 (as word line WL0), ROM cell 2410 can be formed as a non-connected diode. For example, by not forming via structure 2343 on the source / drain contact structure 2330A, the source / drain contact structure 2330A is electrically insulated from the word line WL0. Similarly, assuming no via structure 2343 is formed between M0 track 2350 and M1 track 2366 (as word line WL3), ROM cell 2440 can be formed as a non-connected diode. On the other hand, epitaxial structures 2328B, 2328C, and 2328E are coupled to word lines WL1 (through M0 track 2346), WL2 (through M0 track 2348), and WL4 (through M0 track 2352), respectively, thus forming ROM cells 2420, 2430, and 2450 as connected diodes. In some embodiments, the non-connected diode may be associated with logic 0, and the connected diode may be associated with logic 1. Finally, during configuration, ROM cells 2410, 2420, 2430, 2440, and 2450 can be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0441] Next, see Figure 25 and Figure 26 The figures along line B-B' (or) are shown respectively. Figure 23 A cross-sectional view of the epitaxial structure 2328A and along line C-C' (or Figure 23 A cross-sectional view of the epitaxial structure (2328C) in the image. Figure 25 In the n-well 2305, the common bit line BL is electrically coupled through the epitaxial structure 2328F, the source / drain contact structure 2330F, and the corresponding through-hole structure 2339. Figure 25By not forming a via structure 2343 on the epitaxial structure 2328A, the epitaxial structure 2328A is electrically decoupled from the character line WL0. Furthermore, the epitaxial structure 2328A can directly contact the n-well 2305. In some embodiments, the source / drain contact structure 2330A can be electrically insulated from the n-well 2305 through a dielectric layer 2310. Figure 26 In the n-well 2305, the common bit line BL is electrically coupled through the epitaxial structure 2328F, the source / drain contact structure 2330F, and the corresponding through-hole structure 2339. Figure 24 The epitaxial structure 2328C is electrically coupled to the word line WL2 through the source / drain contact structure 2330C, the corresponding via structure 2339, the M0 track 2348, and the corresponding via structure 2343. Furthermore, the epitaxial structure 2328C can directly contact the n-well 2305. In some embodiments, the source / drain contact structure 2330C can be electrically insulated from the n-well 2305 through another dielectric layer 2310.

[0442] Figure 27 An example layout 2700 is shown configured to form (or program) a memory array comprising a plurality of ROM cells (e.g., 5 ROM cells) arranged along the X direction. In some embodiments, these ROM cells may be programmed with individual logic states based on process technology. Figure 28 A cross-sectional view of a memory array formed based on layout 2700 is shown. For example, Figure 28 This diagram shows a hybrid cross-sectional view of a memory array tangent to or parallel to line A-A' (e.g., the X direction). As disclosed herein, the term "hybrid cross-sectional view" refers to a combination of multiple cross-sectional views that are along the same direction and overlap each other. It should be understood that providing... Figure 27 layout and Figure 28 The corresponding cross-sectional views are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0443] First, refer to Figure 27 The layout 2700 includes, respectively, for forming wells 2705 and one or more dielectric layers 2710 (in... Figure 28The pattern of active region 2712 and gate structures 2714, 2716, 2718, 2720, 2722, 2724, and 2726 is shown better in a cross-sectional view. In some embodiments, well 2705 and active region 2712 may extend along a first lateral direction (e.g., the X direction), while gate structures 2714 to 2726 may each extend along a second lateral direction perpendicular to the first lateral direction (e.g., the Y direction). Thus, gate structures 2714 to 2726 may each span active region 2712. Gate structures 2714 to 2726 may each correspond to a dummy (e.g., dielectric) gate structure. For example, gate structures 2714 to 2726 may each be formed as a polysilicon gate structure and then replaced with a corresponding dielectric gate structure. The well 2705, dielectric layer 2710, active region 2712, and gate structures 2714 to 2726 formed along the main surface of the substrate are sometimes referred to as partial front-end process (FEOL).

[0444] exist Figures 27 to 28 In the example, based on a gate-all-around (GAA) transistor structure, the ROM cells 2810 to 2850 of the memory array are each formed as diodes with bit lines and word lines connected to or not connected to each other. However, the ROM cells 2810 to 2850 of the memory array (formed by layout 2700) can be formed as any of various other transistor structures, while remaining within the scope of this disclosure. With a GAA transistor structure, the active region 2712 can be formed by a stacked structure protruding from the front surface of the substrate. The stack includes multiple semiconductor nanostructures (e.g., nanosheets) extending along the X direction and perpendicularly separated from each other. Individual portions of the semiconductor structures in the stack covered by each gate structure 2714 to 2726 are retained, while other portions are replaced by multiple epitaxial structures 2728A-F. The reserved portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structures 2728A-F that couple the two ends of the channel (e.g., along the X direction) can be configured as the source / drain structures of the transistor, and the partial gate structures 2714 to 2726 that cover (e.g., span) the reserved portion of the semiconductor structure can be configured as the gate termination of the transistor.

[0445] exist Figures 27 to 28In this configuration, epitaxial structures 2728A, 2728B, 2728C, 2728D, 2728E, and 2728F (formed in the active region 2712) and gate structures 2714 to 2726 can be arranged alternately along the X direction. For example, along the X direction, epitaxial structure 2728A is located between gate structures 2714 and 2716, epitaxial structure 2728B is located between gate structures 2716 and 2718, epitaxial structure 2728C is located between gate structures 2718 and 2720, epitaxial structure 2728D is located between gate structures 2720 and 2722, epitaxial structure 2728E is located between gate structures 2722 and 2724, and epitaxial structure 2728F is located between gate structures (not shown) and gate structure 2726. Furthermore, ROM cells 2810 to 2850 are programmed using different logic states. The first group of epitaxial structures (e.g., 2728A, 2728D) can be physically separated (and / or electrically insulated) from the upper interconnect structures 2760, 2766, which are individual character lines WL, respectively, through dielectric layer 2710 and well 2705. The second group of epitaxial structures (e.g., 2728B, 2728C, 2728E) can directly contact well 2705.

[0446] According to some embodiments of this disclosure, well 2705 is formed having a first conductivity type (e.g., p-type), sometimes referred to as p-well (PW) 2705, while one of the epitaxial structures (e.g., 2728F) is formed having the same first conductivity type (p-type), and the remaining epitaxial structures (e.g., 2728A-E) are formed having a second, opposite conductivity type (e.g., n-type). Epitaxial structure 2728F can have a higher doping concentration than p-well 2705. Gate structures 2714 to 2726 may not require a coupling supply voltage (e.g., VSS). Similar to ROM cell 100 ( Figure 1 The p-type epitaxial structure 2728F and p-well 2705 can be operatively used together as a common positive terminal for ROM cells 2810 to 2850, while each n-type epitaxial structure 2728A-E can be operatively used as a negative terminal for an individual ROM cell 2810 to 2850. As will be discussed below, the common positive terminal of ROM cells 2810 to 2850 can be coupled to a common bit line BL, and the negative terminal of each ROM cell 2810 to 2850 can be coupled to an individual word line WL. Furthermore, the positive and negative terminals of each ROM cell 2810 to 2850 can be electrically coupled to or insulated from each other, based on the required logic state to be programmed into the ROM cells 2810 to 2850.

[0447] The layout 2700 further includes patterns for forming source / drain contact structures (each sometimes referred to as MD) 2730A, 2730B, 2730C, 2730D, 2730E, and 2730F, respectively. Generally, each source / drain contact structure 2730A to 2730F is positioned above a corresponding one of the epitaxial structures 2728A to 2728F, as shown below. Figure 28 As shown in the diagram, source / drain contact structures 2730A to 2730F (formed from metallic materials such as copper, tungsten, cobalt, etc.) are each configured to electrically couple corresponding epitaxial structures 2728A-F to interconnect structures 2744-2754 formed in the upper metallization layer via via structures 2739 (sometimes referred to as VD). For example, layout 2700 further includes patterns for forming a plurality of via structures 2739 to electrically connect the lower source / drain contact structures 2730A to 2730F to the upper interconnect structures 2744-2754. Layout 2700 further includes patterns for forming those interconnect structures in the upper metallization layer, which will be discussed below. The source / drain contact structures 2730A-F and via structures 2739 are sometimes referred to as partial middle-of-line (MEOL) processes, and the interconnect structures in the metallization layer are sometimes referred to as partial back-of-line (BEOL) processes.

[0448] exist Figures 27 to 28 In the illustrative example, gate structures 2714 to 2726 may not require coupling to the interconnect structures formed in the bottommost metallization layer M0 (sometimes referred to as the M0 track). Source / drain contact structures 2730A to 2730F may be coupled to the M0 tracks 2744, 2746, 2748, 2750, 2752, and 2754 via individual via structures 2739. The M0 tracks 2744, 2746, 2748, 2750, and 2752 may be further coupled to individual interconnect structures 2760, 2762, 2764, 2766, and 2768 in the next bottommost metallization layer M1 (sometimes referred to as M1 tracks 2760, M1 tracks 2762, M1 tracks 2764, M1 tracks 2766, and M1 tracks 2768) via individual via structures. In some embodiments, M1 tracks 2760, 2762, 2764, 2766, and 2768 are respectively configured as (or coupled to) character lines WL0, WL1, WL2, WL3, and WL4, while M0 track 2754 is configured as (or coupled to) common bit line BL.

[0449] In some embodiments, when forming the above-described interconnection structure (e.g., M0 tracks 2740-2754, M1 tracks 2760-2768), ROM cells 2810, 2820, 2830, 2840, and 2850 can be configured. Figure 28ROM cells are programmed based on epitaxial structure 2728A, one of dielectric layers 2710, p-well 2705, and epitaxial structure 2728F. ROM cells 2820 are formed based on epitaxial structure 2728B, p-well 2705, and epitaxial structure 2728F. ROM cells 2830 are formed based on epitaxial structure 2728C, p-well 2705, and epitaxial structure 2728F. ROM cells 2840 are formed based on epitaxial structure 2728D, another of dielectric layers 2710, p-well 2705, and epitaxial structure 2728F, and ROM cells 2850 are formed based on epitaxial structure 2728E, p-well 2705, and epitaxial structure 2728F.

[0450] Specifically, epitaxial structures 2728A and 2728F (together with p-well 2705) can serve as the negative and positive terminals of ROM unit 2810. Epitaxial structures 2728B and 2728F (together with p-well 2705) can serve as the negative and positive terminals of ROM unit 2820. Epitaxial structures 2728C and 2728F (together with p-well 2705) can serve as the negative and positive terminals of ROM unit 2830. Epitaxial structures 2728D and 2728F (together with p-well 2705) can serve as the negative and positive terminals of ROM unit 2840, and epitaxial structures 2728E and 2728F (together with p-well 2705) can serve as the negative and positive terminals of ROM unit 2850.

[0451] A dielectric layer 2710 is situated between epitaxial structure 2728A and p-well 2705, and ROM cell 2810 can be formed as a non-connected diode. For example, epitaxial structure 2728A and p-well 2705 are electrically insulated from each other by dielectric layer 2710. Similarly, assuming dielectric layer 2710 is situated between epitaxial structure 2728D and p-well 2705, ROM cell 2840 can be formed as a non-connected diode. Although in Figure 28In a cross-sectional view, dielectric layer 2710 is schematically shown having its own sidewalls aligned with the corresponding epitaxial structures (e.g., 2728A, 2728D). It should be understood that dielectric layer 2710 may extend further (in the X direction) than the corresponding epitaxial structures (e.g., 2728A, 2728D). On the other hand, each epitaxial structure 2728B, 2728C, and 2728E directly contacts p-well 2705, thus forming ROM cells 2820, 2830, and 2850 as connection diodes, respectively. In some embodiments, the non-connection diodes may be associated with logic 0, and the connection diodes may be associated with logic 1. Finally, during formation, ROM cells 2810, 2820, 2830, 2840, and 2850 may be programmed with logic 0, logic 1, logic 1, logic 0, and logic 1, respectively.

[0452] This disclosure illustrates a flowchart of an example method 2900 for forming a memory device (e.g., a memory array) according to various embodiments of the present disclosure. In some embodiments, the memory device may be based on layout 300 ( Figure 3 ), 700 Figure 7 ), 1100 ( Figure 11 ), 1500 ( Figure 15 ), 1900 Figure 19 ) or 2700 ( Figure 27 This allows at least one memory cell to be programmed into a logical state different from the other memory cells. Therefore, the following discussion of method 2900 can be referenced to some of the figures above. It should be noted that, as... Figure 29 The method 2900 shown is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 29 The order of operations in method 2900 can be changed. For example, additional operations can be provided before, during, and after method 2900, and this document may only briefly describe some of the operations.

[0453] Method 2900 begins with operation 2910, forming a well extending along a first lateral direction in a substrate. In some embodiments, the substrate may be a silicon substrate. The substrate may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate may include various doping configurations, depending on design requirements known in the preceding embodiments, such as a p-type silicon substrate. Using layout 300 ( Figure 3 As a representative example, a well 305 having a p-type shape can be defined in such a p-type substrate and extended along a first lateral direction (e.g., the X direction) using one or more photolithography processes. Using layout 700 ( Figure 7 As another representative example, a well 705 with a conductivity type opposite to that of a p-type substrate can be formed by one or more photolithography processes and doping processes (e.g., ion implantation).

[0454] Method 2900 continues to operation 2920, forming an active zone extending along the first lateral direction above the well. Continue. Figure 3 For example, active region 312 can be formed as a stack of alternating first and second semiconductor layers. The stack (or each of the included first / second semiconductor layers) can extend along the same direction as well 305 (e.g., the X direction). The first and second semiconductor layers can be epitaxially grown alternately from a substrate. The first and second semiconductor layers can have different compositions, for example, selective etching with a particular etchant. For example, the first semiconductor layer can include silicon germanium (SiGe), and the second semiconductor layer can include silicon (Si). Furthermore, the first semiconductor layer can then be replaced with one or more gate structures, and the second semiconductor layer can be configured as a channel for one or more GAA transistors.

[0455] As described above, the currently disclosed ROM diode can be formed based on other transistor structures while remaining within the scope of this disclosure. For example, the diode can be formed based on a FinFET structure. In this embodiment, the active region can be formed as one or more fin-like structures protruding from the substrate, wherein all the fin-like structures extend along a first lateral direction and are separated from each other along a second lateral direction perpendicular to the first lateral direction.

[0456] Method 2900 continues to operation 2930, forming a plurality of gate structures above the active region, each gate structure extending along a second lateral direction perpendicular to the first lateral direction. Continuing upwards... Figure 3 For example, gate structures 314 to 326, extending in the Y direction, can be formed above the active region 312. Each gate structure 314 to 326 can span the active region 312. In the example, gate structures 314 to 326 can be first formed as dummy gate structures and then replaced by metal gate structures respectively.

[0457] Method 2900 continues to operation 2940, forming multiple dielectric layers in the well. Still using the example above, after forming or defining gate structures 314 to 326, portions of the active regions 312 not covered or spanned by gate structures 314 to 326 can be removed (e.g., etched). In some embodiments, further, individual portions of those uncovered portions of the active regions 312 vertically aligned in the well can also be removed (e.g., etched), followed by filling with dielectric material. Thus, multiple dielectric layers (e.g., 310) aligned with the epitaxial structure to be formed (e.g., 328A to 328F) can be formed in well 305. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low dielectric constant dielectrics, combinations thereof, and / or other suitable materials.

[0458] Method 2900 continues to operation 2950, ​​selectively removing one or more dielectric layers. Still using the example above, after forming dielectric layer 310 in well 305, dielectric layer 310 can be alternately arranged with gate structures 314 to 326 in the X direction, and one or more dielectric layers 310 can be removed to re-expose well 305. For example, in Figure 4 In one approach, a majority portion of the dielectric layer 310 of each of the aligned epitaxial structures 328B-C, 328E, and 328F can be removed to expose the well 305. Alternatively, the dielectric layer 310 of the aligned epitaxial structures 328A and 328D can be retained, thereby isolating the lower well 305 from the upper epitaxial structures 328A and 328D, respectively.

[0459] Method 2900 continues to operation 2960, forming a plurality of epitaxial structures 328A-F in the active region 312, with each gate structure 314 to 326 situated between adjacent epitaxial structures. Still using the example above, after selectively removing one or more dielectric layers 310, epitaxial structures 328A-F can be epitaxially grown from the overlying second semiconductor layer (e.g., silicon) or further from the exposed portion of well 305. For example, epitaxial structures 328B-C, 328E, and 328F can be epitaxially grown from the silicon layer and well 305, and epitaxial structures 328A and 328D can be epitaxially grown from the silicon layer. In some embodiments, one of the epitaxial structures (e.g., 328F) is in-situ doped with the same conductivity type as well 305 during its own epitaxial process by introducing a doping type including p-type doping such as boron or BF2, while the remaining epitaxial structures (e.g., 328A-E) are in-situ doped with the opposite conductivity type to well 305 during their epitaxial processes by introducing a doping type including n-type doping such as phosphorus or arsenic.

[0460] Method 2900 continues to operation 2960, forming a plurality of first interconnect structures extending along a first lateral direction and a plurality of second interconnect structures extending along a second lateral direction, wherein one of the first interconnect structures is configured to share a bit line BL, and the plurality of second interconnect structures are respectively configured as word lines WL. Continue Figure 3 For example, multiple via structures 333 and multiple via structures 339 may be formed above the gate structures 314 to 326 and the epitaxial structures 328A to 328F, respectively.

[0461] In some embodiments, via structures 333 can electrically couple gate structures 314 to 326 to interconnect structure 340 carrying a supply voltage (e.g., VSS), thereby shutting down individual channels. Via structures 339 can electrically couple epitaxial structures 328A-E to individual interconnect structures 360-368 used as word lines WL, wherein one of the via structures 339 is configured to electrically couple epitaxial structure 328F to interconnect structure 354 used as a common bit line BL. Interconnect structures 340 and 354 extending in the X direction can be disposed in the bottommost metallization layer above the substrate (e.g., M0 layer), and interconnect structures 360-368 extending in the Y direction can be disposed in the next bottommost metallization layer above the substrate (e.g., M1 layer).

[0462] In one aspect of this disclosure, a memory device is disclosed. The memory device includes a well formed in a substrate and extending along a first lateral direction, wherein the well has a first conductivity type. A plurality of epitaxial structures disposed above the well, wherein the epitaxial structures have a second conductivity type relative to the first conductivity type. A common epitaxial structure disposed above the well, wherein the common epitaxial structure has a first conductivity type and contacts the well. A first group of epitaxial structures each contacts the well, and a second group of epitaxial structures each has a bottom surface separated from the well by a corresponding dielectric layer. In one embodiment, the memory device further includes a gate structure extending along a second lateral direction perpendicular to the first lateral direction. The gate structure and the epitaxial structures are alternately arranged along the first lateral direction. In one embodiment, the memory device further includes a first interconnect structure, a second interconnect structure, and a third interconnect structure. The first interconnect structure extends along the first lateral direction and is electrically coupled to the gate structures. The second interconnect structure extends along the first lateral direction and is electrically coupled to the common epitaxial structure, and the third interconnect structure extends along the second lateral direction and is electrically coupled to the epitaxial structures respectively. In one embodiment, the first conductivity type and the second conductivity type are p-type and n-type, respectively, wherein the second interconnect structure is coupled to the supply voltage VSS. In one embodiment, the first conductivity type and the second conductivity type are n-type and p-type, respectively, wherein the second interconnect structure is coupled to the supply voltage VDD. In one embodiment, a corresponding epitaxial structure in a first group of epitaxial structures and a shared epitaxial structure operatively function as a first type diode. In one embodiment, a corresponding epitaxial structure in a second group of epitaxial structures and a shared epitaxial structure operatively function as a second type diode. In one embodiment, the first type diode presents a first logic state, and the second type diode presents a second logic state. In one embodiment, the memory device further includes a stack, each of the stacks including semiconductor nanostructures perpendicularly spaced from each other. In one embodiment, each of the gate structures surrounds the corresponding semiconductor nanostructure in the plurality of stacks.

[0463] In another aspect of this disclosure, a memory device is disclosed. The memory device includes a well formed in a substrate and extending along a first lateral direction, wherein the well has a first conductivity type. A plurality of epitaxial structures disposed above the well, wherein the epitaxial structures have a second conductivity type relative to the first conductivity type. A plurality of gate structures extending along a second lateral direction perpendicular to the first lateral direction, wherein each epitaxial structure is disposed adjacent to a corresponding gate structure along the first lateral direction. A common epitaxial structure disposed above the well, wherein the common epitaxial structure has a first conductivity type and contacts the well. A first group of epitaxial structures each contacts the well, and a second group of epitaxial structures each has a bottom surface separated from the well by a corresponding dielectric layer. In one embodiment, the memory device further includes a first interconnect structure, a second interconnect structure, and a third interconnect structure. The first interconnect structure extends along the first lateral direction and is electrically coupled to the gate structure. The second interconnect structure extends along the first lateral direction and is electrically coupled to the common epitaxial structure. The third interconnect structure extends along the second lateral direction and is electrically coupled to the epitaxial structures respectively. In one embodiment, the first conductivity type and the second conductivity type are p-type and n-type, respectively, wherein the second interconnect structure is coupled to the supply voltage VSS. In one embodiment, the first conductivity type and the second conductivity type are n-type and p-type, respectively, wherein the second interconnect structure is coupled to the supply voltage VDD. In one embodiment, a corresponding one and a shared epitaxial structure in a first group of epitaxial structures operatively serve as a first type diode. In one embodiment, a corresponding one and a shared epitaxial structure in a second group of epitaxial structures operatively serve as a second type diode. In one embodiment, the first type diode presents a first logic state, and the second type diode presents a second logic state.

[0464] In another aspect of this disclosure, a method for manufacturing a memory device is disclosed. The method includes forming a well in a substrate, wherein the well extends along a first lateral direction and has a first conductivity type. The method includes forming an active region above the well, wherein the active region extends along the first lateral direction. The method includes forming a plurality of gate structures above the active region, wherein the gate structures extend along a second lateral direction perpendicular to the first lateral direction. The method includes forming a dielectric layer in a first portion of the well, exposing a second and third portion of the well. The method includes forming a common epitaxial structure to contact the second portion of the well, wherein the common epitaxial structure has a first conductivity type. The method includes forming a first epitaxial structure separated from the well by the dielectric layer, wherein the first epitaxial structure has a second conductivity type. The method includes forming a second epitaxial structure to contact a third portion of the well, wherein the second epitaxial structure has a second conductivity type. In one embodiment, the first conductivity type and the second conductivity type are p-type and n-type, respectively, wherein the gate structure is coupled to a supply voltage VSS. In one embodiment, the first conductivity type and the second conductivity type are n-type and p-type, respectively, wherein the gate structure is coupled to a supply voltage VDD.

[0465] In another aspect of this disclosure, a memory device is disclosed. The memory device includes a well formed in a substrate and extending along a first lateral direction, wherein the well has a first conductivity type. A plurality of epitaxial structures disposed above the well, wherein the epitaxial structures have a second conductivity type relative to the first conductivity type. A plurality of gate structures extending along a second lateral direction perpendicular to the first lateral direction, wherein each epitaxial structure is disposed adjacent to a corresponding gate structure along the first lateral direction. A common epitaxial structure disposed above the well, wherein the common epitaxial structure has a first conductivity type and contacts the well. A first group of epitaxial structures each contacts the well, and a second group of epitaxial structures each has a bottom surface separated from the well by a corresponding dielectric layer, wherein a corresponding one of the first group of epitaxial structures and the common epitaxial structure operatively function as a first type diode, and a corresponding one of the second group of epitaxial structures and the common epitaxial structure operatively function as a second type diode.

[0466] As used herein, the terms “approximately” and “substantially” generally indicate that a given quantity of value may vary based on a specific technology node associated with the target semiconductor device. Based on a specific technology node, the term “approximately” may indicate that a given quantity of value varies, for example, within 10-30% of that value (e.g., ±10%, ±20%, ±30% of that value).

[0467] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoint of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, include: A well is formed in a substrate and extends along a first lateral direction, wherein the well has a first conductivity type; Multiple epitaxial structures are disposed above the well, wherein the multiple epitaxial structures have a second conductivity type relative to the first conductivity type; as well as A common epitaxial structure is disposed above the well, wherein the common epitaxial structure has the first conductivity type and is in contact with the well; Each of the plurality of epitaxial structures in a first group contacts the well, and each of the plurality of epitaxial structures in a second group has a bottom surface separated from the well by a corresponding dielectric layer.

2. The memory device as claimed in claim 1, characterized in that, Further includes: Multiple gate structures extend along a second lateral direction, which is perpendicular to the first lateral direction; The plurality of gate structures and the plurality of epitaxial structures are arranged alternately with each other along the first lateral direction.

3. The memory device as claimed in claim 2, characterized in that, Further includes: A first interconnect structure extends along the first lateral direction and is electrically coupled to the plurality of gate structures; A second interconnect structure extends along the first lateral direction and is electrically coupled to the shared epitaxial structure; as well as Multiple third interconnect structures extend along the second lateral direction and are electrically coupled to the multiple epitaxial structures, respectively.

4. The memory device as claimed in claim 1, characterized in that, The first group of the plurality of epitaxial structures corresponds to one and the shared epitaxial structure is operatively used as a first type of diode.

5. The memory device as claimed in claim 4, characterized in that, The second group of the plurality of epitaxial structures corresponds to one and the shared epitaxial structure is operatively used as a second type of diode.

6. The memory device as claimed in claim 5, characterized in that, The first type of diode presents a first logic state, and the second type of diode presents a second logic state.

7. The memory device as claimed in claim 2, characterized in that, Further includes: Multiple stacks, each of which includes multiple semiconductor nanostructures that are perpendicularly spaced from each other.

8. The memory device as claimed in claim 7, characterized in that, Each of the plurality of gate structures surrounds one of the plurality of stacked semiconductor nanostructures.

9. A memory device, characterized in that, include: A well is formed in a substrate and extends along a first lateral direction, wherein the well has a first conductivity type; Multiple epitaxial structures are disposed above the well, wherein the multiple epitaxial structures have a second conductivity type relative to the first conductivity type; Multiple gate structures extend along a second lateral direction perpendicular to the first lateral direction, wherein each of the multiple epitaxial structures is disposed next to one of the multiple gate structures along the first lateral direction; as well as A common epitaxial structure is disposed above the well, wherein the common epitaxial structure has the first conductivity type and is in contact with the well; Each of the plurality of epitaxial structures in a first group contacts the well, and each of the plurality of epitaxial structures in a second group has a bottom surface separated from the well by a corresponding dielectric layer.

10. A memory device, characterized in that, include: A well is formed in a substrate and extends along a first lateral direction, wherein the well has a first conductivity type; Multiple epitaxial structures are disposed above the well, wherein the multiple epitaxial structures have a second conductivity type relative to the first conductivity type; Multiple gate structures extend along a second lateral direction perpendicular to the first lateral direction, wherein each of the multiple epitaxial structures is disposed next to one of the multiple gate structures along the first lateral direction; as well as A common epitaxial structure is disposed above the well, wherein the common epitaxial structure has the first conductivity type and is in contact with the well; Each of the plurality of epitaxial structures in a first group contacts the well, and each of the plurality of epitaxial structures in a second group has a bottom surface separated from the well by a corresponding dielectric layer, wherein one of the plurality of epitaxial structures in the first group corresponds to one of the shared epitaxial structures and operably functions as a first type diode, and one of the plurality of epitaxial structures in the second group corresponds to one of the shared epitaxial structures and operably functions as a second type diode.

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